KR940027172A - Manufacturing method of stack capacitor of DRAM cell - Google Patents

Manufacturing method of stack capacitor of DRAM cell Download PDF

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Publication number
KR940027172A
KR940027172A KR1019930009165A KR930009165A KR940027172A KR 940027172 A KR940027172 A KR 940027172A KR 1019930009165 A KR1019930009165 A KR 1019930009165A KR 930009165 A KR930009165 A KR 930009165A KR 940027172 A KR940027172 A KR 940027172A
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KR
South Korea
Prior art keywords
layer
polysilicon layer
tantalum silicide
storage electrode
polysilicon
Prior art date
Application number
KR1019930009165A
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Korean (ko)
Other versions
KR100252541B1 (en
Inventor
김명선
Original Assignee
김주용
현대전자산업 주식회사
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019930009165A priority Critical patent/KR100252541B1/en
Publication of KR940027172A publication Critical patent/KR940027172A/en
Application granted granted Critical
Publication of KR100252541B1 publication Critical patent/KR100252541B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers

Abstract

본 발명은 디램셀의 스택케패시터 제조방법에 있어서, 특히 핀구조의 스택캐패시터 제조시 저장전극용 제1폴리실리콘층과 제2폴리실리콘층 사이에 형성되는 산화막 대신 탄탈실리사이드층을 형성하여 제2폴리실리콘층을 이방성 식각하는 저장전극 패턴 공정에서 탄탈실리사이드층은 저절로 등방성 식각이 되도록 하여 습식식각을 별도로 실시하지 않아도 되는 스택캐패시터 제조방법이다.The present invention relates to a method of manufacturing a stack capacitor of a DRAM cell, in particular, in the manufacture of a fin capacitor stack capacitor, a tantalum silicide layer is formed instead of an oxide film formed between the first polysilicon layer and the second polysilicon layer for a storage electrode. In the storage electrode pattern process of anisotropically etching a polysilicon layer, the tantalum silicide layer is an isotropic etching by itself and thus does not require a separate wet etching process.

Description

디램셀의 스택캐패시터 제조방법Manufacturing method of stack capacitor of DRAM cell

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도 내지 제3도는 종래기술에 의해 디램셀의 스택캐패시터를 제조하는 단계를 도시한 단면도.1 to 3 are cross-sectional views illustrating a step of manufacturing a stack capacitor of a DRAM cell according to the prior art.

Claims (3)

디램셀의 스택캐패시터 제조방법에 있어서, 실리콘기판에 소자분리 산화막, 워드라인 및 층간절연층을 각각 형성하는 공정과, 층간절연층 상부에 저장전극용 제1 폴리실리콘층과 탄탈실리사이드층을 적층하고, 그 상부에 저장전극 콘택마스크용 감광막패턴을 형성하는 공정과, 감광막이 제거된 지역의 제1 폴리실리콘층, 탄탈실리사이드층 및 층간 절연층을 순차적으로 건식식각하여 실리콘기판이 노출된 콘택홀을 형성하고 감광막패턴을 제거하는 공정과, 탄탈실리사이드층 상부에 저장전극용 제2 폴리실리콘층을 증착하고, 그 상부에 저장전극 마스크용 감광막패턴을 형성하는 공정과, 감광막이 제거된 지역의 제2 폴리실리콘층, 탄탈실리사이드층, 제1 폴리실리콘층을 식각하되, CF4/Cl2개스비를 조절하여 제2 폴리실리콘층을 이방성 식각할 때 노출되는 탄탈실리사이드는 등방성 식각이 되도록 하는 공정과, 남아있는 감광막패턴을 제거하여 제1 폴리실리콘층과 제2 폴리실리콘층으로 구비되는 핀 구조의 저장전극을 형성하는 공정을 포함하는 디램셀의 스택캐패시터의 제조방법.In the method for manufacturing a stack capacitor of a DRAM cell, a process of forming a device isolation oxide film, a word line, and an interlayer dielectric layer on a silicon substrate, and laminating a first polysilicon layer and a tantalum silicide layer for a storage electrode on the interlayer dielectric layer, Forming a photoresist pattern for a storage electrode contact mask thereon; and sequentially dry etching the first polysilicon layer, the tantalum silicide layer, and the interlayer insulating layer in the region where the photoresist film is removed to expose the contact hole where the silicon substrate is exposed. Forming and removing the photoresist pattern, depositing a second polysilicon layer for the storage electrode on the tantalum silicide layer, and forming a photoresist pattern for the storage electrode mask on the second layer; When the polysilicon layer, tantalum silicide layer, and first polysilicon layer are etched, the second polysilicon layer is anisotropically etched by adjusting the CF 4 / Cl 2 gas ratio. The tantalum silicide emitted is an isotropic etching process, and a stack of DRAM cells including a process of forming a fin structure storage electrode including a first polysilicon layer and a second polysilicon layer by removing the remaining photoresist pattern. Method of manufacturing a capacitor. 제1항에 있어서,상기 제1 폴리실리콘층과 탄탈실리사이드층을 폴리실리콘 식각장치에서 식각하고, 상기 평탄화용 절연층은 절연층 식각장치에서 식각하는 것을 특징으로 하는 디램셀의 스택캐패시터 제조방법.The method of claim 1, wherein the first polysilicon layer and the tantalum silicide layer are etched by a polysilicon etching device, and the planarization insulating layer is etched by an insulating layer etching device. 제1 항에 있어서, 상기 CF4/Cl2의 개스비가 3 : 1인 것을 특징으로 하는 디램셀의 스택캐패시터 제조방법.The method of claim 1, wherein the CF 4 / Cl 2 gas ratio is 3: 1 method of manufacturing a stack capacitor of the DRAM cell. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930009165A 1993-05-26 1993-05-26 Method for fabricating a stacked capacitor of dram cell KR100252541B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930009165A KR100252541B1 (en) 1993-05-26 1993-05-26 Method for fabricating a stacked capacitor of dram cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930009165A KR100252541B1 (en) 1993-05-26 1993-05-26 Method for fabricating a stacked capacitor of dram cell

Publications (2)

Publication Number Publication Date
KR940027172A true KR940027172A (en) 1994-12-10
KR100252541B1 KR100252541B1 (en) 2000-04-15

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KR1019930009165A KR100252541B1 (en) 1993-05-26 1993-05-26 Method for fabricating a stacked capacitor of dram cell

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100491420B1 (en) * 2002-11-06 2005-05-25 매그나칩 반도체 유한회사 Method of forming a capacitor in a semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100491420B1 (en) * 2002-11-06 2005-05-25 매그나칩 반도체 유한회사 Method of forming a capacitor in a semiconductor device

Also Published As

Publication number Publication date
KR100252541B1 (en) 2000-04-15

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