KR940022861A - Capacitor Manufacturing Method of Memory Device - Google Patents

Capacitor Manufacturing Method of Memory Device Download PDF

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Publication number
KR940022861A
KR940022861A KR1019930004335A KR930004335A KR940022861A KR 940022861 A KR940022861 A KR 940022861A KR 1019930004335 A KR1019930004335 A KR 1019930004335A KR 930004335 A KR930004335 A KR 930004335A KR 940022861 A KR940022861 A KR 940022861A
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KR
South Korea
Prior art keywords
storage node
capacitor
insulating film
forming
node
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KR1019930004335A
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Korean (ko)
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KR960008573B1 (en
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김홍선
박승현
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문정환
금성일렉트론주식회사
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Priority to KR93004335A priority Critical patent/KR960008573B1/en
Publication of KR940022861A publication Critical patent/KR940022861A/en
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Publication of KR960008573B1 publication Critical patent/KR960008573B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 메모리 소자의 커패시터 제조방법에 관한 것으로 커패시터를 쉽게 제조하고 안정적이고 면적이 증가된 메모리 소자의 커패시터 제조방법을 제공함에 그 목적이 있다.The present invention relates to a method of manufacturing a capacitor of a memory device, and an object of the present invention is to provide a method of manufacturing a capacitor of a memory device having a stable and increased area.

본 발명은 상기 목적을 달성하기 위해서, 메모리 소자의 트랜지스터 제조하는 제1공정, 전면에 완충절연막(20)과 제1축적노드(21) 및 제1절연막(8)을 차례로 증착하고 패터닝하여 상기 드레인 영역(6)에 축적노드 접촉홀(10)을 형성하는 제2공정, 제2축적노드(11)와 제2절연막(12) 및 반구형 반도체층(13)을 차례로 증착하여 커패시터 형성 영역이외의 제2축적노드(11)의 일정 깊이까지 식각하는 제3공정, 상기 반구형 반도체층(13)을 제거한 후 상기 제2절연막(12)을 마스크로 하여 커패시터 형성 이외의 제2축적노드(11)가 완전히 제거될 수 있는 깊이까지 상기 제2축적노드(11)를 삭감함으로써 상기 축적노드(11)가 주름살 형태가 되도록 한 후 상기 제1 및 제2절연막(8,12)을 제거하는 제4공정, 상기 제2축적노드(11)를 마스크로하여 상기 제1축적노드(21)를 식각하고 상기 제1 및 제2축적노드(11,21)상에 유전체막(15)을 형성한 후 커패시터 극판(16)을 형성하는 제5공정, 제3절연막(17,18)을 증착하고 비트라인 영역은 정의한 후 금속을 증착하여 비트라인(14)을 형성하는 제6공정으로 이루어짐을 특정으로 한다.In order to achieve the above object, the present invention provides a first process of manufacturing a transistor of a memory device, and sequentially depositing and patterning a buffer insulating film 20, a first storage node 21, and a first insulating film 8 on the entire surface of the drain. In the second process of forming the storage node contact hole 10 in the region 6, the second accumulation node 11, the second insulating layer 12, and the hemispherical semiconductor layer 13 are sequentially deposited to form a non-capacitor-exposed region. After removing the hemispherical semiconductor layer 13 and removing the hemispherical semiconductor layer 13, the second storage node 11 other than capacitor formation is completely removed. A fourth process of removing the first and second insulating layers 8 and 12 after the second accumulation node 11 is reduced to a depth that can be removed so that the accumulation node 11 is in the shape of a wrinkle; The first storage node 21 is etched using the second storage node 11 as a mask, and After the dielectric film 15 is formed on the first and second storage nodes 11 and 21, the fifth process of forming the capacitor electrode plate 16 is performed. The third insulating film 17 and 18 is deposited, and the bit line region is defined. It is specified that the sixth step of forming a bit line 14 by depositing a metal afterwards.

Description

메모리 소자의 커패시터 제조방법Capacitor Manufacturing Method of Memory Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 메모리 소자의 커패시터 제조 방법을 나타낸 공정순서도.2 is a process flowchart showing a capacitor manufacturing method of the memory device of the present invention.

Claims (5)

실리콘 기판(1)상에 형성한 게이트 전극(3)과 이온 주입 공정으로 형성한 소오스/드레인 영역(5,6)을 구비한 트랜지스터를 형성하는 제1공정, 전면에 완충 절연막(20)과 제1축적노드(21) 및 제1절연막(8)을 차례로 증착하고 패터닝하여, 상기 드레인영역(6)에 축적노드 접촉홀(10)을 형성하는 제2공정, 제2축적노드(11)와 제2절연막(12) 및 반구형 반도체층(13)을 차례로 증착하여 커패서터 형성 영역이외의 제2축적노드(11)의 일정 깊이까지 식각하는 제3공정, 상기 반구형 반도체층(13)을 제거한 후 상기 제2절연막(12)을 마스크로 하여 커패시터 형성 이외의 제2축적노드(11)가 완전히 제거될 수 있는 깊이까지 상기 제2축적노드(11)를 삭각함으로써, 상기 축적노드(11)가 주름살 형태가 되도록 한 후 상기 제1 및 제2절연막(8)(12)을 제거하는 제4공정, 상기 제2축적노드(11)를 마스크로 하여 상기 제1축적노드(21)를 식각하고, 상기 제1 및 제2축적노드(11,21)상에 유전체막(15)을 형성한 후 커패시터 극판(16)을 형성하는 제5공정, 제3절연막(17,18)을 증착하고 비트라인 영역을 정의한 후 금속을 증착하여 비트라인(14)을 형성하는 제6공정으로 이루어짐을 특징으로 하는 메모리 소자의 커패시터 제조방법.A first step of forming a transistor having a gate electrode 3 formed on a silicon substrate 1 and a source / drain regions 5 and 6 formed by an ion implantation process. A second process of forming the accumulation node contact hole 10 in the drain region 6 by depositing and patterning the first accumulation node 21 and the first insulating layer 8 in sequence, and the second accumulation node 11 and the first accumulation layer. A second process of depositing the insulating film 12 and the hemispherical semiconductor layer 13 in order to etch to a predetermined depth of the second storage node 11 other than the capacitor formation region, and then removing the hemispherical semiconductor layer 13. By using the second insulating film 12 as a mask, the storage node 11 is wrinkled by cutting the second storage node 11 to a depth where the second storage node 11 other than capacitor formation can be completely removed. The fourth step of removing the first and second insulating films 8 and 12 after forming the shape, and the second accumulation node 11 A fifth process of etching the first storage node 21 using a mask, forming a dielectric film 15 on the first and second storage nodes 11 and 21, and then forming the capacitor electrode plate 16. And a sixth process of depositing a third insulating layer (17,18), defining a bit line region, and then depositing a metal to form a bit line (14). 제1항에 있어서, 상기 제4공정의 절연막(18,12)을 습식 식각으로 제거함으로 특징으로 하는 메모리 소자의 커패시터 제조방법.2. The method of claim 1, wherein the insulating film (18, 12) of the fourth process is removed by wet etching. 제1항에 있어서, 상기 제5공정의 제1축적노드(21)를 건식 식각으로 제거함을 특징으로 하는 메모리 소자의 커패시터 제조방법.The method of claim 1, wherein the first storage node (21) of the fifth process is removed by dry etching. 제1항에 있어서, 상기 제2절연막(12)을 산화막으로 실행함을 특징으로 하는 메모리 소자의 커패시터 제조방법.The method of manufacturing a capacitor of a memory device according to claim 1, wherein said second insulating film (12) is implemented as an oxide film. 제1항에 있어서, 상기 제2절연막(12)을 절연막으로 실행함을 특징으로 하는 메모리 소자의 커패시터 제조방법.The method of manufacturing a capacitor of a memory device according to claim 1, wherein said second insulating film (12) is implemented as an insulating film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR93004335A 1993-03-20 1993-03-20 Manufacture method of memory device capacitor KR960008573B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR93004335A KR960008573B1 (en) 1993-03-20 1993-03-20 Manufacture method of memory device capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR93004335A KR960008573B1 (en) 1993-03-20 1993-03-20 Manufacture method of memory device capacitor

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KR940022861A true KR940022861A (en) 1994-10-21
KR960008573B1 KR960008573B1 (en) 1996-06-28

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100226754B1 (en) * 1996-09-13 1999-10-15 구본준 Capacitor fabricating method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100226754B1 (en) * 1996-09-13 1999-10-15 구본준 Capacitor fabricating method

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Publication number Publication date
KR960008573B1 (en) 1996-06-28

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