KR940016504A - Contact manufacturing method of semiconductor device - Google Patents

Contact manufacturing method of semiconductor device Download PDF

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Publication number
KR940016504A
KR940016504A KR1019920027093A KR920027093A KR940016504A KR 940016504 A KR940016504 A KR 940016504A KR 1019920027093 A KR1019920027093 A KR 1019920027093A KR 920027093 A KR920027093 A KR 920027093A KR 940016504 A KR940016504 A KR 940016504A
Authority
KR
South Korea
Prior art keywords
polysilicon layer
etching
forming
contact hole
bit line
Prior art date
Application number
KR1019920027093A
Other languages
Korean (ko)
Other versions
KR960008551B1 (en
Inventor
이헌철
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR92027093A priority Critical patent/KR960008551B1/en
Publication of KR940016504A publication Critical patent/KR940016504A/en
Application granted granted Critical
Publication of KR960008551B1 publication Critical patent/KR960008551B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 고집적 반도체의 콘택제조방법에 관한 것으로, 특히 워드라인과 비트라인의 절연성을 높이고, 단차를 줄이기 위하여 게이트 산화막 상부에 폴리실리콘층/산화막/폴리실리콘층으로 구성되는 워드라인을 형성하고, 워드라인 측벽에 산화막 스페이서를 형성한후, 예정된 공정으로 워드라인 상부측벽에 폴리실리콘 스페이서를 형성하고, 비트라인용 콘택홀을 형성하고, 이 콘택홀에 폴리실리콘 플러그를 형성한후 비트라인을 형성하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a contact of a highly integrated semiconductor, in particular to form a word line consisting of a polysilicon layer / oxide film / polysilicon layer on the gate oxide layer in order to increase the insulation of the word line and bit line, and to reduce the step difference, After forming the oxide spacer on the sidewall of the word line, a polysilicon spacer is formed on the upper sidewall of the wordline by a predetermined process, a contact hole for the bit line is formed, a polysilicon plug is formed on the contact hole, and then the bit line is formed. It is about how to.

Description

반도체 소자의 콘택 제조방법Contact manufacturing method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도 내지 제10도는 본 발명에 의해 콘택을 제조하는 단계를 도시한 단면도.1 through 10 are cross-sectional views illustrating steps of manufacturing a contact in accordance with the present invention.

Claims (1)

기판 상부에 제 1 폴리실리콘층/산화막/제 2 폴리실리콘층으로 이루어지는 워드라인을 형성하는 단계와, 워드라인 측벽에 산화막 스페이서를 형성하고, 다시 BPSG막을 도포하되, 워드라인의 산화막 상부면에서 평탄하게 도포하는 단계와, 전체구조 상부에 제 3 폴리실리콘층을 증착하고 비트라인 콘택홀 보다 크게 오픈된 감광막 패턴을 이용하여 제 3 폴리실리콘층을 식각하여 제 3 폴리실리콘층 패턴을 형성하는 동시에 제 2 폴리실리콘층 측벽에 제 3 폴리실리콘층 스페이서를 형성하는 단계와, 노출된 BPSG막을 식각하여 비트라인 콘택홀을 형성하고 제 4 폴리실리콘층을 전체적으로 두껍게 증착하는 단계와, 제4, 제3 및 제 2 폴리실리콘층을 에치백하되 BPSG막이 노출되기까지 식각하여 콘택홀에 제 4 폴리실리콘층 플러그를 형성하는 단계와, 그 상부에 제 5 폴리실리콘층을 증착하고 패턴 공정으로 소정부분의 제 5 폴리실리콘층을 식각하여 비트라인을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 콘택 제조방법.Forming a word line comprising a first polysilicon layer / oxide / second polysilicon layer on the substrate, forming an oxide spacer on the sidewall of the wordline, and then applying a BPSG film, which is flat on the oxide film upper surface of the wordline. The third polysilicon layer is formed by depositing a third polysilicon layer on the entire structure and etching the third polysilicon layer by using a photosensitive film pattern that is larger than the bit line contact hole to form a third polysilicon layer pattern. Forming a third polysilicon layer spacer on the sidewalls of the polysilicon layer, etching the exposed BPSG film to form a bitline contact hole, and depositing a thick overall fourth polysilicon layer; Etching back the second polysilicon layer but etching until the BPSG film is exposed to form a fourth polysilicon layer plug in the contact hole; 5 Poly contact method of producing a semiconductor device, characterized in that the deposition of the silicon layer and forming a bit line by etching the first polysilicon layer 5 of the predetermined portion of the patterning process. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR92027093A 1992-12-31 1992-12-31 Contact manufacturing method of semiconductor device KR960008551B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR92027093A KR960008551B1 (en) 1992-12-31 1992-12-31 Contact manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR92027093A KR960008551B1 (en) 1992-12-31 1992-12-31 Contact manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
KR940016504A true KR940016504A (en) 1994-07-23
KR960008551B1 KR960008551B1 (en) 1996-06-28

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ID=19348240

Family Applications (1)

Application Number Title Priority Date Filing Date
KR92027093A KR960008551B1 (en) 1992-12-31 1992-12-31 Contact manufacturing method of semiconductor device

Country Status (1)

Country Link
KR (1) KR960008551B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100399934B1 (en) * 1996-06-28 2003-12-24 주식회사 하이닉스반도체 Method for forming contact of semiconductor device
KR100972908B1 (en) * 2008-03-17 2010-07-28 주식회사 하이닉스반도체 Method for Manufacturing Semiconductor Device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100399934B1 (en) * 1996-06-28 2003-12-24 주식회사 하이닉스반도체 Method for forming contact of semiconductor device
KR100972908B1 (en) * 2008-03-17 2010-07-28 주식회사 하이닉스반도체 Method for Manufacturing Semiconductor Device

Also Published As

Publication number Publication date
KR960008551B1 (en) 1996-06-28

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