KR930014976A - Bit line manufacturing method of memory device - Google Patents
Bit line manufacturing method of memory device Download PDFInfo
- Publication number
- KR930014976A KR930014976A KR1019910023619A KR910023619A KR930014976A KR 930014976 A KR930014976 A KR 930014976A KR 1019910023619 A KR1019910023619 A KR 1019910023619A KR 910023619 A KR910023619 A KR 910023619A KR 930014976 A KR930014976 A KR 930014976A
- Authority
- KR
- South Korea
- Prior art keywords
- bit line
- polysilicon
- oxide film
- manufacturing
- memory device
- Prior art date
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- Semiconductor Memories (AREA)
Abstract
본 발명은 메모리 소자의 비트라인 제조방법에 관한 것으로 특히, 비트라인 제조 공정을 간단히 하여 워드라인과 비트라인간의 기생 캐패시턴스 용량을 감소시키는데 적당하도록 폴리실리콘 막을 이용한 비트라인 제조 방법에 관한 것이다. 이를 위하여 본 발명에서는, 메모리 소자의 비트라인 제조방법에 있어서, 실리콘 기판의 액티브 영역위에 워드라인을 형성하고, 피복성이 좋은 고온 산화막(HTO)을 데포지션한 후, 폴리실리콘을 데포지션하는 단계(a)와, 게이트 상부의 폴리실리콘을 포토 및 에치하여 정의한 후 평탄화용 산화막을 데포지션하는 단계(b)와, 포토 및 에치 공정을 통해서 평탄화용 산화막, 폴리실리콘 및 고온산화막을 제거하여 비트라인 콘택을 형성하는 단계(c)와, 비트라인 콘택에 도프드 폴리실리콘을 채운 후 에치백하고, 실리사이드 및 산화막을 차례로 데포지션한 다음, 포토 및 에치 공정을 통해서 비트라인을 형성하는 단계(d)을 포함하는 것을 특징으로 하는 메모리 소자의 비트라인 제조방법.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a bit line of a memory device, and more particularly, to a method for manufacturing a bit line using a polysilicon film, which is suitable for reducing the parasitic capacitance capacity between a word line and a bit line by simplifying the bit line manufacturing process. To this end, in the present invention, in the method of manufacturing a bit line of a memory device, a word line is formed on an active region of a silicon substrate, a high temperature oxide film (HTO) having a good coating property is deposited, and then polysilicon is deposited. (a) and defining the polysilicon on the gate by photo and etching, and then depositing the planarization oxide film (b), and removing the planarization oxide film, the polysilicon, and the high temperature oxide film through the photo and etching process. (C) forming a contact, filling the doped polysilicon into the bitline contact and then etching back, depositing the silicide and the oxide film in sequence, and then forming the bitline through a photo and etch process (d) Bit line manufacturing method of a memory device comprising a.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제2도는 본 발명의 메모리 소자의 비트라인 제조공정도,2 is a bit line manufacturing process diagram of a memory device of the present invention;
제3도는 본 발명의 비트라인 구조에 대한 레이아웃 및 단면도,3 is a layout and cross-sectional view of the bit line structure of the present invention;
종래의 셀 단면도와 본 발명의 셀 단면도.Conventional cell cross section and cell cross section of the present invention.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910023619A KR930014976A (en) | 1991-12-20 | 1991-12-20 | Bit line manufacturing method of memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910023619A KR930014976A (en) | 1991-12-20 | 1991-12-20 | Bit line manufacturing method of memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR930014976A true KR930014976A (en) | 1993-07-23 |
Family
ID=67356799
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910023619A KR930014976A (en) | 1991-12-20 | 1991-12-20 | Bit line manufacturing method of memory device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR930014976A (en) |
-
1991
- 1991-12-20 KR KR1019910023619A patent/KR930014976A/en not_active Application Discontinuation
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E601 | Decision to refuse application |