KR930014980A

KR930014980A - DRAM cell manufacturing method

Info

Publication number: KR930014980A
Application number: KR1019910023868A
Authority: KR
Inventors: 노재성; 정호영; 박공희
Original assignee: 문정환; 금성일렉트론 주식회사
Priority date: 1991-12-23
Filing date: 1991-12-23
Publication date: 1993-07-23
Also published as: KR100263470B1

Abstract

본 발명은 64메가급 이상의 디램 셀 제조에 적당하도록 한 비트라인 평탄화 공정에 관한 디램 셀 제조 방법에 관한 것으로 종래에는 비트라인과 워드라인 사이에 기생 커패시턴스가 발생하고 비트라인의 측벽 면적이 증가하여 비트라인과 트라인 사이의 기생 커패시턴스가 크게 되어 결국 센스 앰프의 동작을 어렵게 하였으나 본 발명에서는 비트 라인을 형성하기 전에 평탄화 공정을 실시하여 비트라인의 기생 커패시턴스를 줄이고 이러한 평탄화공정과 함께 비트라인 콘택과 노드 콘택을 용이하게 실시할 수 있도록 한 것이다.The present invention relates to a DRAM cell fabrication method related to a bit line planarization process suitable for DRAM cell fabrication of 64 megabytes or more. In the related art, a parasitic capacitance is generated between a bit line and a word line, and the sidewall area of the bit line is increased so that the bit line is increased. The parasitic capacitance between the line and the line becomes large, which makes it difficult to operate the sense amplifier. However, in the present invention, the parasitic capacitance of the bit line is reduced by performing the planarization process before forming the bit line, and the bit line contact and the node together with the planarization process. The contact can be easily performed.

Description

DRAM cell manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제4도는 본 발명의 일실시예를 나타낸 것으로 제1도의 A-A선으로 본 공정단면도,4 is a cross-sectional view of an embodiment of the present invention as viewed from the line A-A of FIG.

제5도는 제4도에서 제1도의 B-B선으로 본 공정단면도,5 is a cross-sectional view taken along line B-B of FIG. 4 to FIG.

제6도는 본 발명의 다른 실시예를 나타낸 디램 셀의 설계도,6 is a schematic diagram of a DRAM cell according to another embodiment of the present invention;

제7도는 제6도의 C-C선으로 본 공정단면도,7 is a cross-sectional view taken along line C-C of FIG.

제8도는 제6도의 D-D선으로 본 공정단면도.8 is a cross-sectional view taken along line D-D of FIG.

Claims

Forming a bit line contact and a node contact at the same time after forming a gate on the substrate and forming a CVD oxide film thereon; growing a selective polycrystalline silicon to fill the bit line contact and the node contact; Depositing an oxide film to planarize and etching the CVD oxide film to a predetermined thickness; and forming a storage node by forming a bit contact after forming a bit line by forming a bit line contact again, and forming a storage node. DRAM cell manufacturing method.

2. The method of claim 1 wherein the polycrystalline silicon is not filled over the field oxide film when forming bitline contacts and node contacts and growing and filling selective silicon in these contacts.

The method of claim 1, wherein about 500 GPa of polysilicon is left when the planarizing CVD oxide film is etched back.

2. The method of claim 1 wherein the bit line contacts and note contacts are formed on the selective polycrystalline silicon top surface.

Forming a gate contact on the substrate and forming a node contact to form a polycrystalline silicon for pads in the node contact, and planarizing the entire surface of the CVD oxide film to etch the CVD oxide film of the portion where the bit line is to be formed to a predetermined thickness. Forming a polycrystalline silicon sidewall on the etched portion, completing a bit line contact through etching an oxide film between the polycrystalline silicon sidewall, depositing planarizing polycrystalline silicon on the entire surface, and etching back to a predetermined thickness; A DRAM cell manufacturing method formed by sequentially forming a bit line and patterning a storage node.

※ Note: This is to be disclosed by the original application.