KR100263470B1 - Method for fabricateing dram cell - Google Patents

Abstract

PURPOSE: A method for fabricating a DRAM cell is provided to reduce a parasitic capacitance of a bit line by performing a planarization process before forming the bit line, and to make it easy to form a contact with the planarization process. CONSTITUTION: After forming a gate and a CVD oxide for gate side wall on a substrate, a contact etching is performed by defining a bit line contact together with a node contact. Then, the bit line contact and the node contact are filled with a polycrystalline silicon by growing the polycrystalline silicon selectively so that there is no polycrystalline silicon on a field oxide. Then, a planarization is achieved by filling between the gate on the field oxide with a CVD oxide. A bit line contact is formed by etching back the CVD oxide, and then a bit line polycrystalline silicon(17) and a tungsten silicide(18) and a CVD oxide(19) are formed in sequence. Then, a bit line is defined through a photo lithography process, and a CVD oxide for a bit line side wall is formed and is defined on the whole surface.

Description

DRAM cell manufacturing method

1 is a layout diagram of a conventional DRAM cell.

2 is a cross-sectional view taken along the line AA ′ of FIG. 1.

3 is a cross-sectional view taken along the line B-B 'of FIG.

4 is a cross-sectional view showing an embodiment of the present invention according to the line AA ′ of FIG. 1.

5 is a cross-sectional view taken along line BB ′ of FIG. 4 to FIG. 1.

6 is a layout diagram of a DRAM cell according to another embodiment of the present invention.

7 is a process cross-sectional view taken along the line CC ′ of FIG. 6.

8 is a cross-sectional view taken along line D-D 'of FIG.

* Explanation of symbols for main parts of the drawings

11,31: substrate 12,32: gate

13,15,33,35,40: CVD oxide film 14,17,21,34,37,38,42: polycrystalline silicon

39: tungsten silicide

The present invention relates to a method for manufacturing a DRAM cell, and more particularly, to a bit line planarization process suitable for manufacturing a DRAM cell of 64 mega or more.

The conventional DRAM cell manufacturing process is a CVD oxide film for the gate 2 and the gate sidewalls on the substrate 1, as shown in FIG. 2 and FIG. After (3) is formed, bit line contacts are formed, and polycrystalline silicon 4 is deposited for planarization.

After depositing the tungsten silicide 5 and the CVD oxide film 6 in sequence and defining the bit line by a photolithography process, the CVD oxide film 7 for forming the bit line sidewalls is formed and the node contact is formed. Polycrystalline silicon 8 for the storage node is deposited and patterned.

However, in the conventional DRAM cell fabrication method as described above, as shown in FIG. The large parasitic capacitance between word lines and the sidewall area of the bit line increase, which increases the parasitic capacitance ratio (C _b / C _s ) between the bit line and the bit line, which makes the operation of the sense amplifier difficult to operate. There is a flaw.

Disclosure of Invention The present invention has been made to solve the above-mentioned drawbacks. The method of manufacturing a DRAM cell which reduces the parasitic capacitance of the bit line by performing a planarization process before forming the bit line, and can easily perform a contact with such a planarization process. The purpose is to provide.

Hereinafter, with reference to the accompanying drawings, an embodiment of the present invention for achieving the above object will be described in detail.

First, FIG. 4 and FIG. 5 show an embodiment of the present invention along the lines A-A 'and B-B' of FIG. 1, and the gate 12 on the substrate 11 as in (A) first. And the CVD oxide film 13 for the gate sidewall is formed, and the contact etching is performed by defining the bit line contacts and the node contacts together.

Next, as shown in FIG. 4B, the polycrystalline silicon 14 is selectively grown to fill the bit line contact and the node contact at the same time.

At this time, as shown in FIG. 5B, only the bit line contact portion is filled with the polycrystalline silicon 14 and is not filled over the field oxide layer 16. FIG.

Thereafter, the CVD oxide film 15 is filled between the gates 12 on the field oxide film 16 to planarize.

As shown in (C), the CVD oxide film 15 is etched back to an appropriate thickness, leaving only about 500 GPa. Then, as shown in (D), a bit line contact is formed, and the polycrystalline silicon 17 for the bit line and tungsten silicide ( 18) and the CVD oxide film 19 are formed in turn.

Next, as shown in (E), a bit line is defined through a photolithography process, a CVD oxide film 20 for bit line sidewalls is formed, and then defined on the entire surface as shown in (F).

Next, the cross-sectional process along the line D-D 'of FIG. 6 will be described with reference to FIGS. 7 and 8.

First, as in (A), the gate 32 and the CVD oxide film 33 for the gate sidewalls are formed on the substrate 31, the node contacts are defined, and the polycrystalline silicon 34 of about 1000 mW is deposited on the entire surface. Deposit.

Then, as shown in (B), only the polycrystalline silicon of the node contact portion is etched away, the CVD oxide film 35 is formed to be surface planarized, and then a mask operation is performed to form the bit line contact using the photoresist 36. do.

Next, as in (C), the photoresist 36 having the bit line contact portion removed is etched to a predetermined thickness of the CVD oxide film 35, and then the photoresist 36 is removed, and the polycrystalline silicon 37 ) To form sidewalls of the polycrystalline silicon 37 in the grooves of the CVD oxide film 35 as shown.

In this state, as shown in (D), the bit line contacts are formed between the sidewalls of the polycrystalline silicon 37 by etching back, and the polycrystalline silicon 38 for planarization is deposited on the entire surface including the bit line contact buoys. After etch back, lower to the desired height.

Subsequently, the tungsten silicide 39 and the CVD oxide film 40 are etched on the polycrystalline silicon 38 as shown in (E) to form node contacts, and the polycrystalline silicon 42 for storage nodes is deposited and patterned as shown in (F). .

As described above, according to the present invention, in the case of the embodiment shown in FIGS. 4 and 5, first, the polycrystalline silicon 14 is selectively grown before the bit line is formed and then flattened with the CVD oxide film 15. The polycrystalline silicon 14 is filled only in the contact portion, so that the parasitic capacitance between the bit line and the word line can be reduced, and the bit line contact and the node contact can be easily formed.

6 to 8, pad polysilicon may be formed in the node contact region to protect the sidewall oxide layer of the gate when forming the node contact, and the polycrystalline silicon in the CVD oxide layer 35 when forming the bit line contact. By adjusting and using the sidewall of (37), not only can an overlag margin between the gate sidewall and the bitline contact be secured, but also the parasitic capacitance of the bitline can be improved by planarizing the CVD oxide film 35 before forming the bitline. There is an effect that can be minimized.

Claims (4)

Defining a substrate as a field region and an active region, forming a gate electrode to be used as a word line on the field region and the active region, and on the active region at a portion where a bit line and a storage node electrode are to be formed. Forming a polysilicon layer insulated from the gate electrode only, forming an insulating layer on the entire surface including the polysilicon layer, and then planarizing the layer, and removing a predetermined portion of the insulating layer to expose the polysilicon layer. Forming a bit line contact, forming a bit line electrically connected to the exposed polysilicon layer, and forming an insulating layer on the entire surface including the bit line, wherein the polysilicon layer has a predetermined portion. Patterning the semiconductor substrate to be exposed to form a storage node contact, and forming the storage node contact through the storage node contact DRAM cell manufacturing method, characterized by yirueojim including a step of forming a storage node electrode connected to the silicon layer. The method of claim 1, wherein the insulating layer is planarized by an etch back process and leaves about 500 GPa from polycrystalline silicon during etch back. The method of claim 1, wherein bit line contacts and node contacts are formed on the polycrystalline silicon top surface. Defining a substrate as a field region and an active region, forming a gate electrode used as a word line on the field region and the active region, forming a planarization insulating film on the entire surface of the substrate, and forming a bit line Removing the planarization insulating layer at the portion to be formed, forming a polycrystalline silicon sidewall at the etched portion, forming the bit line contact by removing the planarization insulating layer using the sidewall as a mask, and forming the bit line through the contact. Forming a bit line connected to the substrate, removing a flat insulating layer of a region where the storage node is to be formed, forming a pad polysilicon layer, and a storage node electrode electrically connected to the pad polysilicon layer. A DRAM cell manufacturing method, which is performed by sequentially performing a step of forming a film.