KR940009615B1 - Manufacturing method of semiconductor memory device - Google Patents

Abstract

The method for fabricating a semiconductor memory device comprises the steps of: forming an insulating layer on a semiconductor substrate and forming a contact hole in the insulating layer; growing epitaxial layer in the contact hole by the same height as that of the insulating layer; forming gate electrodes of MISFETs on the epitaxial layer; forming a trench in the insulating layer placed on both sides of the gate electrodes; forming an impurity region on the sidewall and bottom of the trench and forming source and drain regions on the epitaxial layer placed between the gate electrodes to form MISFETs; depositing conductive material to form a storage node; and forming a dielectric layer and a plate electrode.

Description

Semiconductor Memory Manufacturing Method

1 is a partial schematic cross-sectional view of a semiconductor memory device according to the prior art.

2A to 2H are manufacturing process diagrams of a semiconductor memory device according to the present invention.

3 to 5 are some schematic cross-sectional views showing respective modifications of the semiconductor memory device of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a method of manufacturing a semiconductor memory device suitable for high integration in a DRAM (dynamic RAM) having a trench structure capacitor and for improving the required capacitor capacity.

In DRAM, a semiconductor memory device, information is stored depending on whether or not there is a charge accumulated in the capacity. However, in the realization of DRAM according to the recent high integration trend, the cell area is divided into one transistor and one transistor after 16K bit DRAM. While only one capacitor is used, it is required to maintain a constant level of cell accumulation capacity. In terms of the capacitor formation, the storage capacitor of the memory cell has been developed in the form of a planar, stacked, or trench in terms of its structure, but among these, a so-called fin structure, which is an improved form of a stacked capacitor structure, has been developed. Although proposed, this technique has a problem that the step is high because the manufacturing process used to secure the required effective area is complicated even if the level of charge accumulation level is increased, and a film is formed by stacking on the silicon substrate.

From this point of view, the interest of semiconductor memory devices having a trench capacitor structure capable of high integration and required capacity is increasing, and the scope of research and development is widening.

A cross-sectional view of the semiconductor device shown in FIG. 1 shows a memory cell portion of a DRAM having a trench structure as a capacitor.

The storage of information is done in the capacitor C of the trench structure and the transfer of information is done via the active element T of the MISFET. These two devices constitute one cell, and the drawing shows two cells formed on the active region between the field oxide films 1 for device isolation. The MISFET (T) comprises a source / drain on the gate (G) and the semiconductor substrate (S), the source / drain region of which is connected to the charge accumulation electrode portion (5) of the trench and the other region is a contact region ( It is connected to the bit line 2 through B).

Inside the trench 6 formed in the semiconductor substrate, a dielectric such as an oxide-nitride-oxide (ONO) layer 3 is formed and a plate electrode layer 4 is formed thereon to form a capacitor. The problem is as follows.

First, as semiconductor devices are highly integrated at, for example, 64M class, the area occupied by the cells becomes narrow, and the contact area becomes narrow in proportion to the area in the drawing, which increases the probability of misalignment and affects the MISFETs located on the left and right sides, and yields. This has a problem of deterioration. This entails the limitation of the etching process for the formation of a narrow contact region, which makes it difficult to realize a satisfactory device.

In addition, in the capacitor capacity, as shown in the figure, the capacitance is maintained by using the trench size and the surface area using the step formed thereon, but the reduction of the device due to the high integration is accompanied by a decrease in the surface area. There is a problem that is difficult to maintain. That is, in the conventional structure, since it is structural, merolicel formation is difficult and it is a structure which has room for improvement even from the viewpoint of capacity maintenance.

Accordingly, an object of the present invention is to provide a DRAM having a trench structure capacitor and a method of manufacturing the same, which solve the problems described above, are not only reliable and advantageous in terms of yield, but also have no reduction in capacity due to high integration.

The semiconductor device manufacturing process of the present invention comprises the steps of forming an opening for forming an element by forming an insulating layer having a predetermined height on the semiconductor substrate; Growing a single crystal semiconductor layer, such as a substrate, to an insulating layer height within a defined opening; Forming a gate electrode for a pair of MISFETs on the semiconductor layer grown in the opening, and forming a trench at a depth of a substrate or more for the gate electrodes and the interlayer insulating regions on both sides; Forming an MISFET by forming an impurity layer on the trench sidewalls and the bottom and forming a source / drain region by ion implantation on the semiconductor layer formed between the gate electrodes, and covering the trench and the film quality around the trench. The conductive material is deposited to form a charge accumulation electrode portion, and a dielectric and plate electrode layer are formed thereon to form a capacitor to fabricate a DRAM cell having a capacitor having a trench structure.

Hereinafter, this invention is demonstrated with reference to attached drawing 2 (a)-(h) and FIG. 3 which show a manufacturing process procedure.

The semiconductor memory device of this invention is formed on another semiconductor layer grown on a substrate.

To this end, first, an insulating layer 13 having a predetermined height is deposited on the semiconductor substrate 11 as shown in FIG. 2A. The insulating layer is grown to an oxide film by a wet oxidation method or a chemical vapor deposition method, and the height thereof is about 0.5∽2 μm in this embodiment, but the comprehensive concept of thickness setting is possible to form two elements of trench and MISFET compatible therewith. It is to be formed at the minimum vertical height or higher.

2B is a step of partially etching the substrate to expose the insulating layer formed as described above to form the opening 15.

This opening is defined to be sized to form at least one or more memory cells. However, in the present invention, a pair of memory cells are formed with openings having a minimum size formed by a design rule according to high integration.

The semiconductor layer as described below is formed as the opening provided in this way. That is, as shown in FIG. 2C, a single crystal semiconductor layer 17 is formed by a so-called selective epitaxial growth (SEG) technique, for example, by low pressure chemical vapor deposition (LPCVD). As mentioned above, this grown single crystal semiconductor layer 17 is continuously grown to the height of the already formed insulating layer and a memory cell is formed in this region.

Depending on the conductivity type of the substrate, impurities may be included during epitaxial growth to form semiconductor layers having the same conductivity type and the same concentration as the substrate.

The memory cell is composed of a capacitor and a MISFET. A pair of memory cells are simultaneously formed on the formed semiconductor layer 17. First, an MISFET as an active element for signal transmission is formed as follows.

In order to form the respective gate electrodes for the pair of MISFETs as shown in the 2d diagram, a thin film gate insulating layer 18 is formed on the single crystal semiconductor layer 17, and the conductive layer 19 for the gate electrode is formed over the entire surface. ) And an insulating layer is formed to form the interlayer insulating layer 21 for the conductive layer.

The gate insulating layer 18 may be thinly formed by a thermal oxidation process with respect to the semiconductor layer 17. The conductive layer 19 for the gate electrode is deposited by, for example, a polysilicon layer, and the insulating layer is deposited by a high temperature oxide film (HTO film) thereon. At this time, the HTO film 21 is formed in this embodiment with a thickness of 500∽2,000∽.

And as mentioned, the formation position of a pair of gate electrode is set by the patterned photoresist film 23 on the HTO film 21. In FIG. 2D, the photoresist film is exposed and developed to form four divided films. The photoresist film on the semiconductor layer defines a gate electrode, and the photoresist film on the insulating layer 21 is patterned to form word lines.

Therefore, the HTO film 21 and the polysilicon layer 19 are continuously etched using the patterned photoresist film 23 as a mask.

After etching to form a pattern for the gate electrode and the word line, the photoresist film 23 is removed, and the HTO film is formed to a thickness of about 500∽2,000∽ over the entire surface of the substrate as shown in FIG. This insulating layer is for forming an insulating layer on the sidewalls in a similar thickness to the insulating layer on the gate electrode in the previous step. That is, after the HTO film 25 is deposited as shown in FIG. 2e, the HTO film is etched by a dry etching method such as RIE to form sidewall oxide films or spacers S formed on both sidewalls of the gate electrode and the word line. (FIG. 2f).

The thickness of this HTO is also related to the n ⁺ junction depth formed on the sidewalls. At this time, during the dry etching process, the gate insulating layer 18 of the thin layer is simultaneously etched simultaneously with the formation of the spacer so that the single crystal semiconductor layer 17 is partially exposed.

As described above, following the formation of the gate electrode, a trench for the capacitor is formed before completing the MISFET. This trench is formed in a region provided by the single crystal semiconductor layer 17 exposed between the insulating layer 13 and each gate electrode.

In general, the trench is formed by a dry etching method. In this case, the photoresist layer 27 is spin-coated on the entire surface of the substrate to expose and develop the semiconductor layer between the two gate electrodes and the exposed semiconductor layer during the trench formation. Afterwards, a photoresist layer is patterned on the inter-gate region.

Therefore, the exposed portion of the single crystal semiconductor layer 17 is limited to only the region for trench formation, and then the spacer S, the insulating layer 13, and the photoresist layer 27, which are HTO films, are dry-etched as in the second g layer. Using the etching mask, that is, by adjusting the selectivity of the SiO ₂ and Si layers, the single crystal silicon semiconductor layer 17 is etched, thereby forming a trench.

The depth of the trench is related to the capacitance of the capacitor. Alternatively, the width of the semiconductor layer 17 may be narrowed, but the area of the semiconductor layer 17 may be narrow. Therefore, the semiconductor layer 17 may be formed as deep as possible.

As described with respect to the height of the insulating layer 13 during the initial process, this is related not only to the height for device formation but also to the depth of trench formation.

By removing the photoresist film 27 and performing a thermal oxidation process on the exposed silicon layer, a thin insulating layer 28 is formed on the trench inner peripheral surface and the gate electrode region. A source / drain region is formed by an ion implantation process to complete the MISFET. The thermal oxide layer 28 is utilized to alleviate the impact of silicon during ion implantation. Ion implantation in the trench sidewalls is possible by appropriately adjusting the ion implantation angle, and furthermore, the ion implantation by the angle adjustment has the advantage of forming a shallow junction.

Thus, the pair of MISFETs is completed by forming the source / drain regions 29 by the gate electrode and the ion implantation.

Subsequently, the thin thermal oxide layer 28 is removed by a wet or dry etching method to expose the single crystal silicon semiconductor layer 17 and the semiconductor substrate 11. Therefore, the source / drain regions formed between the gate electrodes may be connected to the conductive lines for signal transmission, and the source / drain regions of the MISFETs formed on the inner circumferential surface of the trench may be directly connected to the electrodes of the subsequently formed capacitor.

The charge accumulation electrode 31 of the capacitor constituting the DRAM cell is formed by applying a conductive material over the formed trench and the film quality step around the trench inlet. As shown in FIG. 2h, a conductive material for the charge storage electrode is formed over the trench sidewalls and the bottom portion and the gate electrode and the wordline portion. As the conductive material, a polysilicon layer may be used, which is then formed along the electrode to form the ONO film 22 as a dielectric, and also by depositing the conductive material, i.e., polysilicon, to form the plate electrode 33 of the capacitor. The capacitor C constituting the above is completed.

In the conventional process, it is designed to consider the preliminary region considering the misalignment tolerance for the contact region of the source / drain region between the gate electrodes, which is an obstacle to high integration, but the contact region is not formed by photo etching as in the present invention and is in progress. Because it is formed in, it does not affect high integration.

This process advantage allows the capacitor capacity to be increased, since the trench depth can be sufficiently taken into account in terms of reducing the capacitor capacity due to high integration.

3 to 5 show modifications of the present invention, respectively.

FIG. 3 illustrates a structure in which a trench sidewall of an insulating layer is formed and a charge accumulation electrode of a capacitor and a source / drain region of a MISFET are contacted at the bottom thereof.

To form this, in the step of FIG. The impurity region is exposed and the inter-gate electrode region is also exposed to obtain the above-mentioned structure.

A third embodiment of this invention is shown in FIG. This structure is related to the depth of the trench and shows that the trench depth is formed beyond the epi silicon substrate and has a form with an increased capacity. 35 is a borophosphosilicate glass (BPSG) film as a protective film.

5 is another modification of the present invention, in which the trench sidewalls form insulating sidewalls as shown in the third diagram. The same method can be applied, and the depth of the trench is increased, so that even when ion implantation is performed by angle control when forming an impurity layer due to ion implantation in the semiconductor layer, a region having a low concentration is formed, but impurities during polysilicon deposition for charge storage electrodes By using doped polysilicon containing the concentration distribution by diffusion, good transistor formation is possible.

According to the present invention, there is no advantage in forming the contact portion during the process and the misalignment problem by the process such as the semiconductor spacer and the gate spacer which are selectively epitaxially grown in the opening, so that the design is increased and the capacity is increased due to the increase in the area where the capacitor electrode is formed. This increases the effect.

Claims (6)

Forming an opening for forming an element by forming an insulating layer having a predetermined height on the semiconductor substrate; Growing a single crystal semiconductor layer, such as a substrate, to an insulating layer height within a defined opening; Forming a gate electrode for a pair of MISFETs on a semiconductor grown in the opening, and forming a trench at a depth of a substrate or higher for the gate electrodes and the interlayer insulating regions on both sides; Forming an MISFET by forming an impurity layer on the trench sidewalls and the bottom and forming a source / drain region by ion implantation on the semiconductor layer between the gate electrodes, and over the steps of the trench and the surrounding film quality. And depositing a conductive material to form a charge accumulation electrode portion, and forming a dielectric and an electrode layer thereon to form a capacitor. The method of manufacturing a semiconductor memory device according to claim 1, wherein the height of the insulating layer formed on the semiconductor substrate is set within the range based on the depth of the trench to be formed. 2. The method of claim 1, further comprising selectively forming an insulating layer on the formed trench sidewalls after forming the MISFET. The trench of claim 1, wherein the trench formed at a predetermined depth after the gate electrode is formed on the semiconductor layer formed in the opening is formed at both sides of the trench by using a contact region between the semiconductor layer and the insulating layer supporting the opening as one side wall of the trench. A semiconductor memory device manufacturing method characterized by the above-mentioned. The method of claim 1, wherein a thermal oxide layer is formed on the exposed silicon region after the trench is formed to form a source / drain region for the MISFET by ion implantation, and the thermal oxide layer is etched to form a region between gate electrodes. A method of manufacturing a semiconductor memory device, the method comprising: The method of manufacturing a semiconductor memory device according to claim 1, wherein a field oxide film and a gate insulating film are formed as a mask when forming the trench structure.