CN112563205A

CN112563205A - Method for forming semiconductor device

Info

Publication number: CN112563205A
Application number: CN202011026866.1A
Authority: CN
Inventors: 陈稚轩; 陈瑞麟; 林祐宽
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2019-09-26
Filing date: 2020-09-25
Publication date: 2021-03-26

Abstract

A method of forming a semiconductor device includes providing a structure including a substrate, a first fin and a second fin, a first gate structure joining the first fin, and a second gate structure joining the second fin; depositing a dielectric layer on the first gate structure and the second gate structure; etching the dielectric layer to form a first gate contact opening exposing the first gate structure and a second gate contact opening exposing the second gate structure, wherein a first length of the first gate contact opening is greater than a second length of the second gate contact opening; and filling a conductive material into the first gate contact opening and the second gate contact opening to form a first gate contact to join the first gate structure and a second gate contact to join the second gate structure.

Description

Method for forming semiconductor device

Technical Field

Embodiments of the present invention generally relate to semiconductor devices, and more particularly, to different gate contacts for n-type and p-type field effect transistor regions of memory devices, such as sram cells.

Background

The semiconductor integrated circuit industry has experienced exponential growth. Technological advances in integrated circuit materials and design have resulted in each generation of integrated circuits having smaller and more complex circuits than the previous generation. In the evolution of integrated circuits, the functional density (e.g., the number of interconnect devices per unit area) generally increases as the geometries (e.g., the smallest features or lines that can be created by the fabrication process) shrink. The reduction in size generally facilitates increased throughput and reduced associated costs. The shrinking dimensions also increase the complexity of processing and fabricating integrated circuits.

In some integrated circuit designs, as technology nodes shrink, an advanced approach is to replace the polysilicon gate with a metal gate to improve device performance with reduced feature sizes. One of the processes for forming the metal gate may be referred to as a replacement gate or a gate post-process, which finally forms the metal gate to reduce the number of subsequent processes. In the gate post-processing process, a plurality of metal layers such as a work function metal layer and a metal filling layer are sequentially deposited in the gate trench to replace a dummy gate in the original gate trench. However, the processes for implementing these integrated circuit fabrication challenges, particularly for integrated circuit structures that are scaled down in size in advanced process nodes. One of the challenges is the difficulty in depositing metal layers into high aspect ratio gate trenches due to the shrinking gate width in memory devices such as sram devices. One of the subjects of the embodiments of the present invention is to solve this problem.

Disclosure of Invention

An exemplary embodiment of the present invention relates to a method of forming a semiconductor device, including providing a structure including a substrate having a first region and a second region, an isolation structure on the substrate, a first fin extending from the first region of the substrate through the isolation structure, a second fin extending from the second region of the substrate through the isolation structure, a first gate structure engaging the first fin, and a second gate structure engaging the second fin; depositing a dielectric layer on the first gate structure and the second gate structure; etching the dielectric layer to form a first gate contact opening exposing the first gate structure and a second gate contact opening exposing the second gate structure, wherein a first length of the first gate contact opening is greater than a second length of the second gate contact opening; and filling a conductive material into the first gate contact opening and the second gate contact opening to form a first gate contact to join the first gate structure and a second gate contact to join the second gate structure.

An exemplary embodiment of the present invention relates to a method of forming a semiconductor device, including providing a structure including a substrate, a fin protruding from the substrate, an isolation structure surrounding the fin, and a gate structure engaging the fin; forming a dielectric layer on the gate structure; etching the dielectric layer to form an opening exposing the gate structure, wherein the opening is rectangular in top view; etching the gate structure through the opening to extend the opening below the upper surface of the fin; and filling the opening with a conductive material to form a gate contact landing on the gate structure.

An exemplary embodiment of the present invention relates to a semiconductor device, including a substrate having a first region of a first configuration and a second region of a second configuration, the first configuration being opposite to the second configuration; a first fin protruding from the substrate in the first region; a first gate structure joining the first fin in the first region; a first gate contact landing on the first gate structure in the first region; a second fin protruding from the substrate in the second region; a second gate structure joining the second fin in the second region; and a second gate contact landing on the second gate structure in the second region, wherein a lower surface of the first gate contact is lower than a lower surface of the second gate contact.

Drawings

FIG. 1 is a simplified block diagram of an integrated circuit with embedded memory macrocodes in various embodiments of the invention.

FIG. 2 is a circuit diagram of a bit cell of an SRAM that can be implemented as a memory cell of a memory macro code according to various embodiments of the present invention.

FIG. 3 is a cross-sectional view of an interconnect layer of an SRAM bit cell.

Figure 4 is a perspective view of a finfet in some embodiments.

FIG. 5 is a plan view of an SRAM bitcell that may be implemented in a memory cell of a memory macrocode, in various embodiments of the invention.

FIG. 6 is a plan view of a 2 × 2 memory array formed by the SRAM bit cell arrangement of FIG. 5.

Fig. 7 is a flow chart of a method for forming a semiconductor device in accordance with an embodiment of the present invention.

Fig. 8-18 are cross-sectional views of semiconductor structures fabricated by the method of fig. 7 in some embodiments.

Description of reference numerals:

A-A: cutting line

BL, BLB: bit line

BLN, BLNB: bit line node

C1, C2, C3, C4: bit cell

CD 1: a first common drain

CD 2: a second common drain

D1, D2, h: distance between two adjacent plates

H fin height

L, L1, L2: length of

M1, M2, M3: metal layer

PD-1, PD-2: pull-down transistor

PG-1, PG-2: pass-gate transistor

PU-1, PU-2: pull-up transistor

SN, SNB: storage node

SW1, SW2, SW3, SW 4: side wall

Via _0, Via _1, Via _ 2: via layer

VDDN1, VDDN2, VSSN1, VSSN 2: voltage node

V_DD,V_SS: supply voltage

W: width of

Wg: width of grid

WL: word line

100,600: semiconductor device with a plurality of semiconductor chips

102: memory macrocode

104: circuit area

104A, 104B: memory area

106: memory unit

108,108A,108B, 108C: with zones

110: controller

112: dummy unit of edge

114,418: dielectric layer

200,400: SRAM bit cell

210,220: reverser

300: fin-shaped field effect transistor

302,420,420A,420A ', 420B, 420B', 420C,420C ', 420D, 420D', 420E,420E ', 420F, 420F': fin

304,430A,430B,430C, 430D: grid structure

306: spacer

308: drain region

310: source region

312,402: substrate

314,404: isolation structure

316: gate dielectric layer

318: grid electrode

406: virtual grid structure

408: interfacial layer

410,471A, 471B: gate layer

412,413,488: hard mask layer

414: p-type field effect transistor region

415: groove

416,416A, 416B: n-type field effect transistor region

460A,460B,460D, 460L: gate contact

460C,460E,460F,460G,460I,460J, 460K: source/drain contact

460H, and (2): device layer contact

470A, 470B: dielectric layer with high dielectric constant

472A, 472B: work function layer

474A, 474B: first work function layer

475A, 475B: second work function layer

476A, 476B: metal filling layer

482: etch stop layer

484: interlayer dielectric layer

490,492: opening of the container

494: conductive layer

700: method of producing a composite material

702,704,706,708,710,712,714,716,718,720: step (ii) of

Detailed Description

The following detailed description may be read with reference to the drawings to facilitate understanding of various aspects of the invention. It is noted that the various structures are for illustrative purposes only and are not drawn to scale as is normal in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of presentation.

The different embodiments or examples provided below may implement different configurations of embodiments of the invention. The particular arrangements and examples shown are meant to simplify the present disclosure and not to limit the invention. For example, the formation of a first element on a second element is described as including direct contact between the two elements, or the separation of additional elements other than direct contact between the two elements.

Moreover, various examples of the invention may be repeated using the same reference numerals for brevity, but elements having the same reference numerals in the various embodiments and/or arrangements do not necessarily have the same correspondence. Furthermore, spatially relative terms such as "below," "lower," "underside," "above," "upper," or the like may be used for ease of description to refer to a relationship of one element to another element in the figures. Spatially relative terms may be extended to elements used in other orientations than the orientation illustrated. Further, when a value or range of values is described as "about", "approximately", or the like, it includes +/-10% of the stated value, unless otherwise specified. For example, the term "about 5 nm" includes a size range of 4.5nm to 5.5 nm.

Embodiments of the present invention generally relate to semiconductor devices, and more particularly, to different gate contacts for n-type and p-type field effect transistor regions of memory devices, such as sram cells. A gate contact connects the metal gate of the transistor to an overlying layer, such as a via layer. The gate contact is typically formed by forming an opening in the gate and filling the opening with a conductive material, and the formation process may be damascene or dual damascene. The shape of the opening for the gate contact is typically circular or square and is uniform throughout the circuit. In an embodiment of the invention, the gate contact in the n-type field effect transistor region of the sram cell has an elongated shape in the top view (compared to a square gate contact in the p-type field effect transistor region), and the depth to which the gate contact in the n-type field effect transistor region extends to the underlying gate is greater (compared to the gate contact in the p-type field effect transistor region). In forming the gate contact, the deeper and elongated opening in the gate electrode that extends into the n-type transistor region will additionally oxidize the aluminum-containing conductive layer (e.g., metal fill layer) of the gate electrode. The additional oxidation may increase the threshold voltage of the n-type transistor, which may reduce the thickness of one or more metal layers (e.g., titanium nitride layers) in the gate electrode that compensate for the threshold voltage variation. As the aspect ratio of the gate trench increases with the increase of the number of nodes to be formed, the thinner metal layer can improve the gap-filling capability of the metal layer in the gate post-processing.

Fig. 1 shows a semiconductor device 100 having a memory macro 102. The semiconductor device 100 may be a microprocessor, an ASIC, a field programmable gate array, or a digital signal processor. Furthermore, the semiconductor device 100 may be part of an integrated circuit chip, a system on a chip, or a portion thereof, which may include a variety of passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field effect transistors, n-type field effect transistors, metal oxide semiconductor field effect transistors, complementary metal oxide semiconductor transistors, bipolar junction transistors, laterally diffused metal oxide semiconductor transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. The actual function of the semiconductor device 100 is not limited to the above-described subject matter. In the illustrated embodiment, the memory macro 102 is an SRAM macro, such as a single ended SRAM macro, a double ended SRAM macro, or other types of SRAM macros. However, the memory macro code 102 of the embodiments of the invention may be another type of memory, such as a dynamic random access memory, a non-volatile random access memory, a flash memory, or other suitable memory. Fig. 1 has been simplified to clarify the drawing in order to facilitate understanding of the inventive concepts of the embodiments of the present invention. Additional structures may be added to the memory macro-code 102, and other embodiments of the memory macro-code 102 may replace, adjust, or omit some of the structures described below.

In the embodiment, the memory macro 102 includes one or more circuit regions 104, such as memory regions 104A and 104B. The circuitry region 104 includes all of the memory cells 106 of the memory macro-code 102. The circuit region 104 is also referred to as a memory cell region. Memory cells 106 are typically implemented in an array in the circuit region 104. Each memory cell 106 is configured to store data, such as a sram cell. The memory cell 106 may be implemented in a variety of p-type metal oxide semiconductor transistors or n-type metal oxide semiconductor transistors, such as planar transistors, finfet transistors, all-around gate nanosheet transistors, all-around gate nanowire transistors, or other kinds of transistors. In the illustrated embodiment, memory cell 106 includes a variety of p-type and n-type finfets. In the embodiment, memory macro code 102 also includes one or more stripes 108, such as

stripes

108A,108B, and 108C, whose length direction is along the x-direction.

Stripes

108A and 108C are located at the edges of memory macro-code 102, and stripe 108 is located between memory areas 104A and 104B. Each stripe 108 contains no memory cells and is used to implement a well pick-up structure. The well pickup structure is typically configured to electrically couple a voltage to either the n-type well of the memory cell 106 or the p-type well of the memory cell 106.

In addition, the memory macro 102 may include various contact structures (or contacts), vias, and metal lines connecting the source, drain, and gate (or ends) of the transistors to form an integrated circuit.

As shown in fig. 1, the memory cells 106 are arranged in first to nth rows extending along a first direction (e.g., y-direction) and in first to mth columns extending along a second direction (e.g., x-direction), wherein N and M are positive integers. The first to nth columns each include a pair of bit lines extending along a first direction, such as bit line BL and complementary bit line BLB (also referred to as bit lines bars), which facilitate reading and/or writing individual memory cells 106 row by row in true and complementary fashion. The first row through the Mth row each include a word line WL (not shown) that facilitates accessing the individual memory cells 106 row-by-row. Each memory cell 106 is electrically connected to a respective bit line BL, a respective bit line BLB, and a respective word line WL, which are electrically connected to the controller 110. The controller 110 is configured to generate one or more signals to select at least one word line WL and at least one pair of bit lines (BL and BLB) to access at least one memory cell 106 for a read operation and/or a write operation. The controller 110 includes any circuitry suitable for reading the memory cells 106 or writing the memory cells 106, including but not limited to row decoding circuitry, column decoding circuitry, row selection circuitry, column selection circuitry, read/select circuitry (such as configured to read data of memory cells 106 corresponding to a selected bitline pair (i.e., a selected row)), other suitable circuitry, or a combination thereof. In some embodiments, the controller 110 includes at least one sense amplifier (not shown) configured to detect and/or amplify the differential voltage of a selected bit line pair. In some embodiments, the sense amplifier is configured to lock or store the data value of the differential voltage.

The periphery of the memory macro 102 is configured as dummy cells, such as the edge dummy cells 112, to ensure consistent performance of the memory cells 106. The dummy cells are arranged to be physically and/or structurally similar to memory cells 106, but do not store data. For example, the dummy cell may include a p-well, a fin structure (including one or more fins), a gate structure, a source/drain structure, and/or a contact structure. In the illustrated embodiment, the first through M columns of memory cells 106 begin with the edge dummy cells 112 and end with the edge dummy cells 112 such that the first through M columns of memory cells 106 are not between the two edge dummy cells 112.

FIG. 2 is a circuit diagram of an SRAM bit cell 200, which may be implemented in a memory cell of an SRAM array, in various embodiments of the present invention. In some embodiments, sram bitcell 200 may be implemented in one or more memory cells 106 of memory macrocode 102 (fig. 1). Fig. 2 has been simplified to clarify the drawing in order to facilitate understanding of the inventive concepts of the embodiments of the present invention. Additional structures may be added to sram bit cell 200, and other embodiments of sram bit cell 200 may replace, adjust, or omit some of the structures described below.

Sram bit cell 200 includes six transistors: pass gate transistors PG-1 and PG-2, pull-up transistors PU-1 and PU-2, and pull-down transistors PD-1 and PD-2. Sram bit cell 200 can therefore be viewed as a 6T sram bit cell. The 6T sram bit cell is used for illustration of the structure and is not used to limit the embodiments or related applications. Non-limiting embodiments may be applied to 8T SRAM bit cells, 10T SRAM bit cells, or content addressable memory bit cells.

In operation, pass gate transistors PG-1 and PG-2 provide access to the memory portion of SRAM bit cell 200, which includes a pair of cross-coupled inverters, such as

inverters

210 and 220. Inverter 210 includes a pull-up transistor PU-1 and a pull-down transistor PD-1, and inverter 220 includes a pull-up transistor PU-2 and a pull-down transistor PD-2. In some embodiments, pull-up transistors PU-1 and PU-2 are configured as p-type fin field effect transistors, while pull-down transistors PD-1 and PD-2 are configured as n-type fin field effect transistors. In some embodiments, pass gate transistors PG-1 and PG-2 are also configured as n-type fin field effect transistors.

The gate of pull-up transistor PU-1 is clamped to the source (electrically coupled to the power voltage V)_DD) And a first common drain CD1, and a gate of the pull-down transistor PD-1 is sandwiched between the source (electrically coupled to the power voltage V)_SS) And the first common drain CD 1. The gate of pull-up transistor PU-2 is clamped to the source (electrically coupled to the power voltage V)_DD) And a second common drain CD2, and a gate of the pull-down transistor PD-2 is sandwiched between the source (electrically coupled to the power voltage V)_SS) And a second common drain CD 2. In some embodiments, the first common drain CD1 is a storage node SN that stores data in real form. The second common drain CD2 is a storage node SNB, which stores data in a complementary form. The gate of pull-up transistor PU-1 and the gate of pull-down transistor PD-1 may be coupled to the second common drain, and the gate of pull-up transistor PU-2 and the gate of pull-down transistor PD-2 may be coupled to the first common drain. The gate of pass-gate transistor PG-1 is sandwiched between the source (electrically coupled to the complementary bit line BL) and the drain, which may be electrically coupled to the first common drain CD 1. The gate of pass-gate transistor PG-2 is sandwiched between the source (electrically coupled to the complementary bit line BLB) and the drain, which may be electrically coupled to the second common drain CD 2. The gates of pass gate transistors PG-1 and PG-2 are electrically coupled to word line WL. In some embodiments, pass gate transistors PG-1 and PG-2 may provide access to storage nodes SN and SNB during read operations and/or write operations. For example, pass gate transistors PG-1 and PG-2 couple storage nodes SN and SNB to bit lines BL and BLB, respectively, in response to voltages applied to the gates of pass gate transistors PG-1 and PG-2 by word line WL.

In reading from SRAM bitcell 200, a positive voltage may be applied to the word line and pass gate transistors PG-1 and PG-2 may couple bitline BL and BLB to and receive data from storage nodes SN and SNB. Unlike dynamic memory or DRAM cells, SRAM bitcells do not lose their memory state when read, and therefore do not require a write back operation after read. The bit lines Bl and BLB form a complementary pair of data lines. As known to those skilled in the art, the pairs of data lines may be coupled to differential sense amplifiers (not shown) and may sense and amplify differential voltages read from the sram cells. This may amplify the sense signal (e.g., the voltage of the logic layer) which may then output a signal, such as a read signal, to other logic circuits in the device.

After the transistors are formed, the sram bit cell 200 is formed in a semiconductor device, and the transistors may be interconnected to form a circuit. The connectors may be formed by using horizontal conductors formed of metal layers, which may be separated from the substrate and the gate by dielectric layers. In addition, the inter-layer dielectric layer and the inter-metal dielectric layer can separate and electrically isolate the metal layers from each other. For example, the dielectric layers may be low dielectric constant or high dielectric constant materials. The connections between the metal layers are required to couple device nodes (e.g., data storage nodes or bit line nodes) to the upper conductors, and may run vertically through the dielectric layer. An example of a linker is shown in figure 3.

FIG. 3 shows a cross-sectional view of an SRAM bit cell, wherein layers are formed on a semiconductor substrate or wafer. It is noted that fig. 3 shows various layers of interconnect structures and transistors, and that they may not correspond to the actual cross-sectional view of sram bit cell 200. The interconnect structure includes source/drain and gate contact layers, Via layers Via _0, Via _1, and Via _2, and metal layers M1, M2, and M3. Each layer includes one or more dielectric layers and conductive structures formed therein. Conductive structures of the same layer may have upper surfaces that are substantially flush with each other and lower surfaces that are substantially flush with each other, and may be formed simultaneously. Vertical conductive structures in the source/drain and gate contact layers may connect the gates of transistors (such as the exemplary transistors shown in fig. 2, e.g., pass gate transistor PG-1 and pull-up transistor PU-2) to an upper layer (such as Via layer Via _0), which may be considered a gate contact. Vertical conductive structures in the source/drain and gate contact layers may connect source/drain regions of the transistors to an upper layer (e.g., Via layer Via _0), which may be considered source/drain contacts. The gate contact and the source/drain contacts may be comprised of a variety of conductors including, but not limited to, metal nitrides, copper, tungsten, aluminum copper, titanium nitride, titanium tungsten, titanium, tantalum nitride, tantalum, platinum, or combinations thereof.

Advanced semiconductor devices employ more and more finfets. The fin field effect transistor has a three-dimensional gate structure. By forming a gate including a dielectric layer and an electrode layer on a vertical fin, the vertical height of the fin may increase the width W of the transistor gate (which is proportional to the transistor performance) without a corresponding increase in the surface area required for the device. On the other hand, the packaging of finfet devices for a given W/L measurement is more closely configured than the packaging of existing planar mos devices (with corresponding W/L measurements).

Fig. 4 is a perspective view of a finfet 300 that may be used as any transistor of sram bit cell 200 (fig. 2), including pull-up transistor PU-1, pull-up transistor PU-2, pull-down transistor PD-1, pull-down transistor PD-2, pass gate transistor PG-1, and pass gate transistor PG-2. In some embodiments, finfet 300 includes a semiconductor fin 302, a gate structure 304, spacers 306, a drain region 308, and a source region 310. Semiconductor fin 302 extends over semiconductor substrate 312. Semiconductor fin 302 represents

semiconductor fins

420A, 420B, 420C, 420D, 420E, and 420F in the layout of sram bit cell 400 in fig. 5, described below. In some embodiments, semiconductor substrate 312 and semiconductor fin 302 are of the same material composition. For example, the substrate is a silicon substrate. In some embodiments, isolation structures 314 formed on both sides of semiconductor fin 302 may surround semiconductor fin 302 of finfet 300. Isolation structure 314 may electrically isolate an active region (not shown) of finfet 300 from other active regions. In some embodiments, the isolation structure 314 is shallow trench isolation, field oxide, or another suitable electrically insulating structure.

As some examples shown in figure 3, gate structure 304 includes a gate dielectric layer 316 and a gate 318 on gate dielectric layer 316 and may be located on sidewalls and an upper surface of semiconductor fin 302. A portion of the semiconductor fin 302 overlapping the gate structure 304 may serve as a channel region of the finfet 300. In some embodiments, spacers 306 of finfet 300 are located on sidewalls and an upper surface of semiconductor fin 302. In addition, spacers 306 may be formed on both sides of the gate structure 304. In some embodiments, the composition of the spacers 306 is silicon nitride, silicon oxynitride, silicon carbide, another suitable material, or a combination thereof.

In some embodiments, portions of semiconductor fin 302 not covered by gate structure 304 and spacers 306 may serve as drain region 308 and source region 310. In some embodiments, drain regions 308 and source regions 310 of p-type fin field effect transistors, such as pull-up transistor PU-1 and pull-up transistor PU-2, may be formed by implanting portions of semiconductor fin 302 not covered by gate structure 304 and spacers 306 with a p-type impurity, such as boron, indium, or the like. In some embodiments, the drain region 308 and the source region 310 of the n-type fin field effect transistors, such as pass gate transistor PG-1, pass gate transistor PG-2, pull-down transistor PD-1, and pull-down transistor PD-2, may be formed by implanting the gate structure 304 and the portion of the semiconductor fin 302 not covered by the spacer 306 with n-type impurities, such as phosphorus, arsenic, antimony, or the like.

In some embodiments, drain region 308 and source region 310 may be formed by etching the portions of semiconductor fin 302 not covered by gate structure 304 and spacers 306 to form recesses, and growing epitaxial regions in the recesses. The epitaxial region may be composed of silicon, germanium, silicon phosphide, silicon carbide, silicon carbon phosphide, silicon germanium, silicon arsenide, indium gallium arsenide, indium antimonide, gallium arsenide, gallium antimonide, indium aluminum phosphide, indium phosphide, carbon, or combinations thereof. In summary, the composition of drain region 308 and source region 310 in some exemplary embodiments may be silicon germanium, while the composition of the remaining semiconductor fins 302 may be silicon. In some embodiments, when epitaxially growing the source and drain

regions

310 and 308 of p-type finfet 300, such as pull-up transistor PU-1 and pull-up transistor PU-2 in fig. 2, p-type impurities may be in-situ doped into the source and drain

regions

310 and 308. When epitaxially growing the n-type finfet 300, such as the source region 310 and the drain region 308 of pass gate transistor PG-1, pass gate transistor PG-2, pull-down transistor PD-1, and pull-down transistor PD-2 in fig. 2, n-type impurities may be in-situ doped into the source region 310 and the drain region 308.

In some embodiments, pass gate transistors PG-1 and PG-2, pull-up transistors PU-1 and PU-2, and pull-down transistors PD-1 and PD-2 of SRAM bit cell 200 in FIG. 2 may be planar metal oxide semiconductor devices.

FIG. 5 is a layout of an SRAM bitcell 400, which may be implemented as a memory cell of an SRAM array, in some embodiments of the invention. In some embodiments, sram bitcell 400 is implemented in one or more memory cells 106 of memory macrocode 102 of fig. 1, or as sram bitcell 200 of fig. 2. Fig. 4 has been simplified to clarify the drawing in order to facilitate understanding of the inventive concepts of the embodiments of the present invention. Additional structures may be added to sram bit cell 400 and other embodiments of sram bit cell 400 may replace, adjust, or omit some of these structures.

In fig. 5, sram bit cell 400 includes six transistors: pass gate transistors PG-1 and PG-2, pull-up transistors PU-1 and PU-2, and pull-down transistors PD-1 and PD-2. Sram bit cell 400 can therefore be considered a 6T sram bit cell. Sram bit cell 400 includes a p-type field effect transistor region 414 providing an n-type well between n-type field effect transistor regions 416A and 416B (collectively referred to as n-type field effect transistor regions 416) each providing a p-type well. Pull-up transistors PU-1 and PU-2 are located on p-type field effect transistor region 414, pull-down transistor PD-1 and pass gate transistor PG-1 are located on n-type field effect transistor region 416A, and pull-down transistor PD-2 and pass gate transistor PG-2 are located on n-type field effect transistor region 416B. In some embodiments, pull-up transistors PU-1 and PU-2 are configured as p-type fin field effect transistors, while pull-down transistors PD-1 and PD-2 and pass-gate transistors PG-1 and PG-2 are configured as n-type fin field effect transistors. In some embodiments, each transistor may be similar to the finfet 300 of fig. 4. In the illustrated embodiment, pull-down transistor PD-1 and pass-gate transistor PG-1 are multi-fin finfets (e.g., including

fins

420A and 420B), pull-up transistor PU-1 is a single-fin finfets (e.g., including fin 420C), pull-up transistor PU-2 is a single-fin finfets (e.g., including fin 420D), and pull-down transistor PD-2 and pass-gate transistor PG-2 are multi-fin finfets (e.g., including

fins

420E and 420F). Gate structure 430A is located on

fins

420A and 420B, gate structure 430C is located on fins 420A-420D, gate structure 430B is located on fins 420C-420F, and gate structure 430D is located on

fins

420E and 420F. The gate of pass gate transistor PG-1 is formed by gate structure 430A, the gate of pull-down transistor PD-1 is formed by gate structure 430C, the gate of pull-up transistor PU-2 is formed by gate structure 430B, the gate of pull-down transistor PD-2 is formed by gate structure 430B, and the gate of pass gate transistor PG-2 is formed by gate structure 430D.

Source/drain contact 460K electrically connects the drain region of pull-down transistor PD-1 (formed by

fins

420A and 420B, which may comprise an n-type epitaxial source/drain structure) and the drain region of pull-up transistor PU-1 (formed by fin 420C, which may comprise a p-type epitaxial source/drain region), such that the common drain of pull-down transistor PD-1 and pull-up transistor PU-1 forms storage node SN. Gate contact 460B electrically connects the gate of pull-up transistor PU-2 (formed by gate structure 430B) and the gate of pull-down transistor PD-2 (formed by gate structure 430B) to storage node SN. Source/drain contact 460C electrically connects the drain region of pull-down transistor PD-2 (formed by

fins

420E and 420F, which comprise an n-type epitaxial source/drain structure) and the drain region of pull-up transistor PU-2 (formed by fin 420D, which comprises a p-type epitaxial source/drain structure), such that the common drain of pull-down transistor PD-2 and pull-up transistor PU-2 forms storage node SNB. The gate contact 460D is electrically connected to the upper pullThe gate of transistor PU-1 (formed by gate structure 430C) and the gate of pull-down transistor PD-1 (also formed by gate structure 430C) to storage node SNB. Source/drain contact 460E electrically connects upper pull-up transistor PU-1 (formed by fin 420C, which may include a p-type epitaxial source/drain structure) to supply voltage V_DDVDDN1, and source/drain contact 460F electrically connects pull-up transistor PU-2 (formed by fin 420D, which may include a p-type epitaxial source/drain structure) to supply voltage V_DDVDDN 2. Source/drain contact 460G electrically connects pull-down transistor PD-1 (formed by

fins

420A and 420B, which may comprise an n-type epitaxial source/drain structure) to supply voltage V_SSAnd device layer contact 460H electrically connects pull-down transistor PD-2 (formed by

fins

420E and 420F, which may comprise an n-type epitaxial source/drain structure) to supply voltage V_SS Voltage node VSSN 2. Source/drain contact 460I electrically connects pass gate transistor PG-1 (formed by

fins

420A and 420B, which may include n-type epitaxial source/drain structures) to a bit line (generally referred to as bit line node BLN), and source/drain contact 460J electrically connects pass gate transistor PG-2 (formed by

fins

420E and 420F, which may include n-type epitaxial source/drain structures) to a complementary bit line (generally referred to as bit line node BLNB). Gate contact 460A electrically connects the gate of pass gate transistor PG-1 (formed by gate structure 430A) to a word line WL (commonly referred to as a word line node), while gate contact 460L electrically connects the gate of pass gate transistor PG-2 (formed by gate structure 430D) to a word line.

Of the

gate contacts

460A,460B,460D, and 460L, the

gate contacts

460B and 460D are located on the p-type field effect transistor region 414 providing the n-type well, and the

gate contacts

460A and 460L are located on the n-type field effect transistor regions 416A and 416B providing the p-type well. The width W of the gate contact is measured in the pitch direction (e.g., Y direction) of the gate. The length L of the gate contact is measured in the direction of the length of the gate (e.g., the X direction). A distance between the gate contact and an adjacent fin (e.g., distance D1 from an edge of gate contact 460A to an opposing edge of fin 420A, or distance D2 from an edge of gate contact 460B to an opposing edge of fin 420D) is measured in a direction along the length of the gate (e.g., the X direction). The width of the gate structures 430A-430D is denoted as gate width Wg. In the illustrated embodiment, the

gate contacts

460B and 460D are each square with a width W that is approximately the same as the length L (W ≈ L ≈ Wg). The

gate contacts

460A and 460L are each rectangular with a width W that is substantially equal to the gate width Wg and a length L that is about 2 to about 3 times the width W. In other words, the gate contact for an n-type transistor on a p-type well has a larger length to width ratio than the gate contact for a p-type transistor on an n-type well. As shown in subsequent cross-sectional views, the gate contact on the p-type well extends deeper into the underlying gate than the gate contact on the n-type well. The elongated shape of

gate contacts

460A and 460L may also reduce the distance D1 between the gate contacts and the respective adjacent fins. In some embodiments, distance D2 between gate contact 460B and fin 420D is about 1.1 to about 2 times gate width Wg, while distance D1 between gate contact 460A and fin 420A is about 0.4 to about 0.8 times gate width Wg. The advantages of an elongated and deepened gate contact over a p-type well for an n-type transistor will be more apparent in the following description of the invention.

The semiconductor device 600 shown in fig. 6 may contain 2 × 2 sram bit cells C1, C2, C3, and C4. In one embodiment, each SRAM bitcell in the array can employ the layout of SRAM bitcell 400 shown in FIG. 5. It is noted that other SRAM bit cell layouts may be used. The semiconductor device 600 may include the memory macro 102 or be the device shown in fig. 1. Fig. 6 has been simplified to clarify the drawing in order to facilitate understanding of the inventive concepts of the embodiments of the present invention. For example, FIG. 5 omits the source/drain contacts in SRAM bit cell 400. In addition, the reference numerals in fig. 5 may be repeated in fig. 6 to facilitate understanding, such as fins 420A-420F, gate structures 430A-430D, and

gate contacts

460A,460B,460D, and 406L.

An example of a 2x2 array may include p-type field effect transistor region 414 and n-type field effect transistor region 416. In this embodiment, the n-type field effect transistor region 416 provides a p-type well to form an n-type fin field effect transistor device (including pass gate transistor PG-1 and pull down transistor PD-1), while the p-type field effect transistor region 414 provides an n-type well to form a p-type fin field effect transistor device (including pull up transistors PU-1 and PU-2).

An example of a 2x2 array may include p-type field effect transistor regions 414 and n-type field effect transistor regions 416 arranged alternately along the x-direction. In other words, each p-type field effect transistor region 414 is adjacent to an n-type fin field effect transistor region 416, and the n-type field effect transistor region 416 is adjacent to another p-type field effect transistor region 414, and this pattern is repeated. For simplicity of reference, the rows in this example are in the Y direction. Thus, bitcells C1 and C2 are in the first column and bitcells C3 and C4 are in the second column. As shown, adjacent cells in the array are mirror images along the boundary between adjacent cells. Some active regions in an SRAM bit cell may extend across multiple SRAM bit cells in the same column. In FIG. 6, the active regions (e.g.,

fins

420A and 420B) for pass gate transistor PG-1 and pull-down transistor PD-1 in bit cell C1 extend through bit cell C2 to serve as the active regions for pass gate transistor PG-1 and pull-down transistor PD-1. The active region for pull-up transistor PU-1 in bit cell C1 (e.g., fin 420) may extend through bit cell C2 to serve as the active region for pull-up transistor PU-1. Similarly, the active regions for pass gate transistor PG-1 and pull down transistor PD-1 in bit cell C3 (e.g.,

fins

420A and 420B) extend through bit cell C4 as the active regions for pass gate transistor PG-1 and pull down transistor PD-1. The arrangement of the active regions (labeled as fins 420A 'through 420F') extending through bit cells C3 and C4 may be similar to the arrangement of their corresponding fins 420A through 420F.

When the bitcells have the configuration of FIG. 6, the active regions of the entire bitcell array can have uniform separation and extension. For example, the space in the x-direction may be uniform between active regions. In addition, the active region may extend longitudinally across multiple bitcells without the isolation region interrupting the active region. This arrangement improves the uniformity of the array layout, thereby avoiding photolithography problems in forming the active region, particularly in forming fins for finfet active regions and small technology nodes.

Fig. 7 illustrates a flow diagram of a method 700 for forming the semiconductor device 600 of fig. 6 in some embodiments. Method 700 is provided by way of example only and is not intended to limit embodiments of the present invention to those portions of the subject application not actually recited in the related application. Additional steps may be provided before, during, and after the method 700, and additional embodiments of the method may replace, omit, or swap some of the steps described. The method 700 will be described with reference to fig. 6 and 8-18, which show various cross-sectional views of the semiconductor device 600 during the fabrication steps of the method 700. Specifically, fig. 8-18 are cross-sectional views of semiconductor device 600 taken along section line a-a of fig. 6 (cut through n-type field effect transistor region 416 and p-type field effect transistor region 414 along the length of

gate structures

430A and 430B).

The semiconductor device 600 is used for illustrative purposes and is not intended to limit embodiments of the present invention to any number of devices, any number of regions, or any arrangement of structures or regions. Furthermore, the semiconductor device 600 shown in fig. 6 and 8-18 may be an intermediate device or portion thereof fabricated during processing of an integrated circuit, which may include static random access memory and/or logic circuitry, passive components (e.g., resistors, capacitors, or inductors), and active components (e.g., p-type field effect transistors, n-type field effect transistors, multi-gate field effect transistors such as finfets, mosfets, cmos transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, or combinations thereof).

Step 702 of method 700 shown in fig. 7 and 8 provides semiconductor device 600 having substrate 402, fin 420 (including

fins

420A, 420B, 420C, 420D, 420A ', and 420B') protruding from substrate 402, and isolation structure 404 located over substrate 402 and between fin 420. Each fin 420 includes two source/drain regions and a channel region sandwiched between the two source/drain regions. The device also includes dummy gate structure 406 to engage the channel region of fin 420. The dummy gate structure 406 is a placeholder for a high-k dielectric layer and a metal gate formed in a subsequent process. The dummy gate structure 406 may also be considered a dummy gate stack.

In this embodiment, the substrate 402 is a silicon substrate. In other embodiments, the substrate 402 comprises other semiconductor elements such as germanium; a semiconductor compound such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide; or a semiconductor alloy such as silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. In embodiments, the substrate 402 may comprise a silicon-on-insulator substrate, may have stress and/or strain to enhance performance, may comprise epitaxial regions, doped regions, and/or other suitable structures and layers.

The substrate 402 includes two regions, such as an n-type field effect transistor region 416 providing a p-type well for forming an n-type fin field effect transistor device and a p-type field effect transistor region 414 providing an n-type well for forming a p-type fin field effect transistor device, with the boundary therebetween as shown in dashed lines in fig. 8. Each of n-type field effect transistor region 416 and p-type field effect transistor region 414 includes a plurality of fins 420 separated by isolation structures, such as

fins

420A, 420B, 420A ', and 420B' in n-type field effect transistor 416 and

fins

420C and 420D in p-type field effect transistor region 414. It should be understood that embodiments of the present invention are not limited to any particular number of fins and regions, or any particular device arrangement. For example, although the semiconductor device 600 in the drawings is a finfet device, embodiments of the present invention may also be used to fabricate planar fet devices or fully-wrapped fet devices.

The length direction of fins 420 is along the Y-direction and is separated from each other in the X-direction, and the X-direction is perpendicular to the Y-direction. Each fin 420 may be designed for forming an n-type finfet or a p-type finfet, depending on the respective area. Fins 420 may be patterned by any suitable method. For example, fin 420 may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combined with photolithography and self-alignment processes can produce pitches that are smaller than the pitch of patterns obtained using a single direct photolithography process. For example, one embodiment forms a sacrificial layer on a substrate and patterns the sacrificial layer using a photolithography process. Spacers are formed along the patterned sacrificial layer sides using a self-aligned process. The sacrificial layer is then removed and the remaining spacers or cores may then be used as a masking unit to pattern fin 420. For example, the mask unit may be used to etch recesses in substrate 402 to retain fins 420 on substrate 402. The etching process may include dry etching, wet etching, reactive ion etching, and/or other suitable processes.

The isolation structure 404 may comprise silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass, a low-k dielectric material, and/or other suitable insulating materials. The isolation structure 404 may be a shallow trench isolation structure. In one embodiment, isolation structure 404 is formed by etching a trench into substrate 402 (e.g., as part of the process used to form fin 420), filling the trench with an insulating material, and performing a chemical mechanical planarization process on substrate 402 containing the insulating material. Other types of isolation structures are also suitable, such as field oxide or local silicon oxide.

The length direction of the dummy gate structure 406 is along the X-direction. Dummy gate structure 406 and fin 420 are bonded to their respective channel regions. The dummy gate structure 406 is a multi-layer structure. For example, the dummy gate structure 406 may include an interfacial layer 408, a gate layer 410 on the interfacial layer, and two hard mask layers 412 and 413.

The interfacial layer 408 may comprise a dielectric material such as silicon oxide or silicon oxynitride, and may be formed by chemical oxidation, thermal oxidation, atomic layer deposition, chemical vapor deposition, and/or other suitable methods. The gate layer 410 may comprise polysilicon and may be formed by a suitable deposition process such as low pressure chemical vapor deposition or plasma assisted chemical vapor deposition. Each of the hard mask layers 412 and 413 may comprise one or more layers of dielectric material, such as silicon oxide and/or silicon nitride, and may be formed by chemical vapor deposition or other suitable methods. The patterning of the various layers in the dummy gate structure 406 may be performed by photolithography and etching.

At step 704 of method 700 shown in fig. 7 and 9-11, an isolation structure is formed to separate dummy gate structure 406 into two portions, one portion overlying n-type field effect transistor region 416 and the other portion overlying p-type field effect transistor region 414. Step 704 may remove a portion of the dummy gate structure 406 and the top of the isolation structure 404 to form a trench 415, as shown in fig. 9. Step 704 may include one or more etching processes that are selective to the material of the dummy gate structures 406 and the isolation structures 404. The etching process may include dry etching, wet etching, reactive ion etching, or other suitable etching methods. Step 704 may be followed by filling the trenches 415 with one or more dielectric materials to form a dielectric layer 418, as shown in fig. 10. In this embodiment, other portions of the dielectric layer 418 (near the sidewalls SW1 and SW2) may comprise silicon nitride and no oxide. In some embodiments, the dielectric layer 114 may include some oxide on its interior portions. In other embodiments, the dielectric layer 114 may comprise a uniform silicon nitride layer without oxide. The dielectric layer 418 can be deposited by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable methods. In this embodiment, the deposition method of the dielectric layer 418 may employ atomic layer deposition to ensure that it completely fills the trench 415.

One or more chemical mechanical planarization processes are also performed in step 704 to remove the excess dielectric layer 418 (the portion outside the trench 415) and the hard mask layers 412 and 413. In one embodiment, the hard mask layer 412 may serve as a chemical mechanical planarization stop layer when the chemical mechanical planarization process removes the hard mask layer. In one embodiment, the hard mask layer 412 may serve as a CMP stop layer when the chemical mechanical planarization process removes the hard mask layer 413. The final structure is shown in fig. 11. After step 704, the dielectric layer 418 may be considered an isolation structure. Isolation structures such as dielectric layer 418 divide dummy gate structure 406 into two parts, which are then replaced with two high-k dielectric layers and a metal gate.

At step 706 of method 700 shown in fig. 7 and 12, dummy gate structure 406 is removed to form a gate trench (not shown), and high-k dielectric and

metal gate structures

430A and 430B (see fig. 6) are deposited in the gate trench. The high-k dielectric layer and metal gate structure 430A engage the fins 420B', 420A, and 420B in the n-type field effect transistor region 416 to form an n-type transistor, such as pass gate transistor PG-1. The high-k dielectric layer and metal gate structure 430B engage

fins

420C and 420D in p-type field effect transistor 414 to form a p-type transistor, such as pull-up transistor PU-2.

The high-k dielectric and metal gate structure 430A includes a high-k dielectric layer 470A and a gate layer 471A. Similarly, the high-k metal gate structure 430B includes a high-k dielectric layer 470B and a gate layer 471B. Each high-

k dielectric layer

470A and 470B may further include an interfacial layer (e.g., silicon oxide or silicon oxynitride) between the respective high-k dielectric layer and fin 420. The interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition, chemical vapor deposition, and/or other suitable methods. The high-

k dielectric layers

470A and 470B may comprise one or more high-k dielectric materials (or one or more layers of high-k dielectric materials), such as hafnium silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, lanthanum oxide, titanium oxide, yttrium oxide, strontium titanate, or combinations thereof. The high-

k dielectric layers

470A and 470B may be deposited by chemical vapor deposition, atomic layer deposition, and/or other suitable methods.

The gate layer 471A may include one or more metal layers, such as the work function layer 472A and the metal fill layer 476A. Similarly, the gate layer 471B may include one or more metal layers, such as the work function layer 472B and the metal fill layer 476B. The work function layer determines the work function of the high-k dielectric layer and the metal gate, and may include at least one layer or multiple layers of different materials. The material of the work function layer is selected according to whether the corresponding transistor is an n-type fin transistor or a p-type transistor. For example, the work function layer 472A of the n-type field effect transistor may comprise a first work function layer 474A (e.g., a titanium nitride layer) and a second work function layer 475A (e.g., a titanium aluminum layer) on the first work function layer 474A. The work function layer 472B of the p-type fin field effect transistor may include a first work function layer 474B (e.g., a titanium nitride layer, a tantalum nitride layer, or a titanium nitride layer on a tantalum nitride layer) and a second work function layer 475B (e.g., a titanium aluminum layer) on the first work function layer 474B. The deposition methods for the

work function layers

472A and 472B may be atomic layer deposition, chemical vapor deposition, physical vapor deposition, and/or other suitable methods. In some embodiments, each

work function layer

472A and 472B comprises a titanium aluminum layer on a titanium nitride layer, but with different thicknesses in the n-type and p-type field effect transistor regions to produce different work functions. In one example, the titanium nitride layer (e.g., the first work function layer 474A) in the n-type field effect transistor region 416 is thinner than the titanium nitride layer (e.g., the second work function layer 475B) in the p-type field effect transistor region 414, e.g., at a thickness ratio of about 1:1.1 to about 1: 10. This ratio range ensures effective threshold voltage tuning and acceptable work function layer thicknesses. If the thickness ratio is greater than 1:1.1, the threshold voltage of the p-type transistor is too high. If the thickness ratio is less than 1:10, the titanium nitride layer in the p-type field effect transistor region 414 may be too thick to be deposited in the gate trench. In addition, the titanium aluminum layer (e.g., second work function layer 475A) in n-type field effect transistor region 416 is thicker than the titanium aluminum layer (e.g., second work function layer 475B) in p-type field effect transistor region 414, e.g., by a ratio of about 1.1:1 to about 10: 1. Likewise, this ratio range ensures effective threshold voltage tuning and acceptable work function layer thicknesses. If the thickness ratio is less than 1.1:1, the threshold voltage of the n-type transistor is too high. If the thickness ratio is greater than 10:1, the thickness of the titanium aluminum layer in the n-type field effect transistor region 416 may be too thick to be deposited in the gate trench.

In some embodiments, after depositing the

work function layers

472A and 472B, a barrier layer such as another titanium nitride layer may be formed. The

metal fill layers

476A and 476B may comprise aluminum, tungsten, cobalt, and/or other suitable materials. After the

metal fill layers

476A and 476B are formed, a planarization process, such as a chemical mechanical planarization process or a mechanical polishing process, may be performed to remove excess fill metal material on the isolation structures, such as the dielectric layer 418, and expose the isolation structures, such as the dielectric layer 418.

The threshold voltage of the transistor depends mainly on the material and thickness of the work function metal layer. For example, for an n-type transistor in which the work function layer comprises titanium nitride, the thinner the titanium nitride layer, the lower the threshold voltage. On the other hand, the thickness of the TiN layer is also determined for a given threshold voltage. A thin layer of titanium nitride is typically required to facilitate its deposition in high aspect ratio gate trenches. Sometimes the identified thickness is not thin enough and therefore the deposition step faces challenges. The opening for the gate contact of the n-type transistor may be intentionally elongated and deepened during the formation of the gate contact to increase the oxidation of the aluminum-containing second work function layer 475A, which may increase the threshold voltage (if not otherwise adversely affected). Therefore, in order to offset the increased threshold voltage, the thickness of the titanium nitride layer can be further reduced, so as to obtain a thinner titanium nitride layer. In summary, the thickness of the first work function layer 474A in the n-type transistor may be smaller than the thickness of the first work function layer 474B in the p-type transistor.

At step 708 of the method 700 shown in fig. 7 and 13, an etch stop layer 482 and an interlayer dielectric layer 484 are formed over the semiconductor device 600. The etch stop layer 482 may comprise silicon carbide, silicon oxynitride, silicon carbonitride, or the like. The interlayer dielectric 484 may comprise a material selected from phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorine-doped silicate glass, an oxide of tetraethoxysilane, or other non-porous, low-k dielectric material. The etch stop layer 482 may be formed by a deposition method such as chemical vapor deposition. The interlayer dielectric layer 484 may be formed by spin-on coating, flowable chemical vapor deposition, or the like, or by other deposition methods such as plasma-assisted chemical vapor deposition, low pressure chemical vapor deposition, or the like.

At step 710 of the method 700 shown in fig. 7 and 14, one or more hard mask layers are formed over the semiconductor device 600. In this example, the hard mask layer 488 is taken as an example. In one embodiment, hard mask layer 488 comprises silicon nitride. The hard mask layer 488 may be deposited by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable methods. The hard mask layer 488 is also patterned in step 710 to form a patterned hard mask. As shown in fig. 14, hard mask layer 488 is patterned (e.g., etched) to provide openings 490 in n-type field effect transistor region 416 and openings 492 in p-type field effect transistor region 414. In one example, step 710 may form a patterned photoresist on the hard mask layer 488 by coating, exposing, post-exposure baking, and developing. Step 710 may then use the patterned photoresist as an etch mask and etch the hard mask layer 488 to form

openings

490 and 492. The etching process may include wet etching, dry etching, reactive ion etching, or other suitable etching methods. The patterned photoresist may then be removed, and the removal process may be stripping the photoresist. It is noted that the sidewalls of the

openings

490 and 492 of the hard mask layer 488 can be vertical or approximately vertical.

In some embodiments, opening 490 is located laterally between

fins

420A and 420A', while opening 492 is located directly on fin 420C.

Openings

490 and 492 have widths in the direction of gate pitch (e.g., Y-direction) substantially equal to the widths of

gate structures

430A and 430C. The

openings

490 and 492 have lengths L1 and L2, respectively, in the direction of the gate pitch (Y direction). The length L2 of opening 492 is substantially equal to its width. The length L1 of the opening 490 is about 2 to about 3 times the width, which is also about 2 to about 3 times the length L2.

At step 712 of method 700 shown in fig. 7 and 15, an etch process is performed to extend

openings

490 and 492 down through the ild layer 484 and the etchstop layer 482 to form gate contact openings. The etching process may include wet etching, dry etching, reactive ion etching, or other suitable etching methods. In some embodiments, the etch of step 712 includes two steps. The first step is a main etch step that etches through the ild 484 and the etchstop 482 to expose the

metal fill layers

476A and 476B. After the main etching step, an over-etching step is performed. The overetch step may further extend the

gate contact openings

490 and 492 into the tops of the

metal fill layers

476A and 476B to achieve a larger contact area.

In step 714 of the method 700 of fig. 7 and 16, the high-k dielectric layer and the work function layer 472A of the metal gate structure 430A are etched through the opening 490 in the n-type field effect transistor region 416. A photoresist layer (not shown) may also be used to cover the p-type field effect transistor region 414 to limit etching through the opening 490 rather than the opening 492. Step 714 may further extend the opening 490 into the work function layer 472A. In the depicted embodiment, opening 490 extends below the upper surface of fin 420. In other embodiments, opening 490 extends below the upper surface of fin 420 by a distance H that is less than half of fin height H (from the upper surface of isolation structure 404). If the distance H is not less than half the fin height H, the metal fill 476A directly under the opening 490 may be too thin to adversely affect normal transistor operation.

The etching process may employ one or more etchants or a mixture of etchants that can etch multiple layers in the gate layer 471A. Step 714 may apply a dry etch process that employs a process gas mixture of sulfur hexafluoride and oxygen as a dry etchant. In some other embodiments, the etching process of step 714 is a wet etching process that employs an aqueous potassium hydroxide solution as a wet etchant. In these embodiments, the gaseous mixture of sulfur hexafluoride and oxygen and the potassium hydroxide solution contain some oxygen, which may together be considered an oxygen-containing etchant or an atomic oxygen-containing etchant. In addition, step 714 may also control the etching bias voltage in the dry etching, or alternatively control the etchant in the wet etching. For example, a higher etch bias voltage (along the Z direction) tends to produce more vertical sidewalls in the opening 490, and a lower etch bias voltage reduces ion bombardment of the etchant downward, resulting in sloped sidewalls. In the illustrated embodiment, sidewalls SW3 and SW4 are sloped to etch a portion of second work function layer 475A and expose second work function layer 475A on sidewalls SW3 and SW 4. In some embodiments, the etch bias applied in step 714 may be 50V to 100V. In addition, the etching process of step 714 of this embodiment has a pressure of 5mTorr to 20mTorr, an energy of 100W to 200W, and a temperature of 75 ℃ to 125 ℃. Various other values of etch bias, etch pressure, etch energy, and etch temperature are also possible.

In some embodiments illustrated in fig. 16, the oxygen-containing etchant employed in step 714 may react with aluminum atoms in the second work function layer 475A (e.g., a tiain layer) to form an alumina-containing compound (e.g., tiain) that is predominantly present on the outer portions of the sidewalls SW3 and SW4 proximate the opening 490, while the inner portion of the second work function layer 475A is substantially free of the alumina-containing compound. Once the outer portion is converted to an aluminum oxide-containing compound due to chemical reaction with the oxygen-containing etchant, it may act as an etch passivation layer to hinder the oxygen-containing etchant from etching the second work function layer 475A.

Since the opening 490 in the gate layer 471A is larger and deeper than a normal opening (e.g., opening 492), the aluminum-containing compound in the second work function layer 475A in the larger and deeper opening will be converted to an aluminum oxide-containing compound. This conversion may increase the threshold voltage of the n-type transistor, and thus the first work function layer 474A may be thinner when depositing the first work function layer 474A to compensate for the increased threshold voltage. In the gate post-process, the thinner first work function layer 474A is easier to deposit into the high aspect ratio gate trench with higher uniformity and saves more space for other conductive layers to be subsequently deposited thereon.

At step 716 of method 700 of fig. 7 and 17, one or more conductive materials are filled into

openings

490 and 492 to form conductive layer 494. Conductive layer 494 can comprise tungsten, copper, aluminum, other suitable conductive materials, or combinations thereof. The conductive layer 494 may be formed by a suitable deposition process such as chemical vapor deposition or physical vapor deposition. In other embodiments, the method of forming conductive layer 494 can be a single damascene process or a dual damascene process. In one embodiment, the conductive layer 494 also includes a pad layer (not shown). The liner layer may comprise tantalum nitride, titanium nitride, hafnium nitride, zirconium nitride, tungsten nitride, niobium nitride, molybdenum nitride, combinations thereof, and/or other suitable conductive materials. The liner layer may be formed by atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, and/or other suitable deposition processes.

At 718 of method 700, shown in fig. 7 and 18, one or more chemical mechanical planarization processes are performed to remove excess conductive layer 494 (portions outside of openings 490 and 492) and hard mask layer 488. After step 718, recessed conductive layer 494 becomes two parts: a gate contact 460A filling an opening 490 in the n-type field effect transistor region 416, and a gate contact 460B filling an opening 492 in the p-type field effect transistor region 414. Similar to the contents of

openings

492 and 490 described above,

gate contacts

460A and 460B have a width in the direction of the gate pitch (Y-direction) that is substantially the same as the width of

gate structures

430A and 430C. The

gate contacts

460A and 460B have lengths L1 and L2, respectively, in the gate length direction (X direction). The length L2 of the gate contact 460B is substantially equal to its width. The length L1 of the gate contact 460A is about 2 to about 3 times the width of the gate contact 460A and is also about 2 to about 3 times the length L2. This range ensures effective threshold voltage tuning and acceptable distances from adjacent fins. If length L1 is greater than 3 times the width (and length L2), gate contact 460A becomes too close to

fins

420A and 420A', which may interfere with normal transistor operation. If the length L1 is less than 2 times the width (and the length L2), the threshold voltage cannot be effectively adjusted, resulting in a meaningless reduction in the thickness of the first work function layer 474A. Due to the greater length L1, the ratio between the distance D1 between the gate contact 460A and the fin 420A and the width of the gate contact 460A may be less than 1:1, such as about 0.4:1 to about 0.8:1 in a specific example. In contrast, the ratio of the distance D2 between the gate contact 460B and the fin 460D to the width of the gate contact 460B is greater than 1:1, such as about 1.1:1 to about 2:1 in certain examples. The lower surface of gate contact 460A is a distance H less than half of fin height H below the upper surface of fin 420. In a specific example, the distance H is about 0.2 to about 0.4 times the fin height H. As discussed above, if the distance H is not less than half the fin height H, the metal fill 476A directly under the opening 490 may become too thin to adversely affect normal transistor operation. In some embodiments, the gate contact 460A physically contacts the metal fill layer 476A and the second work function layer 475A, while the gate contact 460B physically contacts the metal fill layer 476B.

As shown in step 720 of method 700 of fig. 7, additional steps are performed to complete the fabrication of semiconductor device 600. For example, via layers and metal layers may be formed on the gate contacts to form metal interconnects that connect various transistors, i.e., to form the completed integrated circuit.

Embodiments of the present invention provide many advantages to, but are not limited to, semiconductor devices and methods of forming the same. For example, embodiments of the present invention provide larger and deeper gate contacts for n-type transistors formed in p-type wells. The larger and deeper gate contacts allow one or more metal layers in the metal gate structure to be thinned and deposited more easily in high aspect ratio gate trenches. In addition, the embodiment of the invention can be easily integrated into the existing semiconductor manufacturing process.

In some embodiments, the above method further comprises: the first gate structure is etched through the first gate contact opening such that the first gate contact opening is deeper than the second gate contact opening.

In some embodiments, a lower surface of the first gate contact opening is lower than an upper surface of the first fin, and a lower surface of the second gate contact opening is higher than an upper surface of the second fin.

In some embodiments, a lower surface of the first gate contact is lower than an upper surface of the first fin by a distance less than half of a height of the first fin.

In some embodiments, the first width of the first gate contact opening is substantially equal to the second width of the second gate contact opening.

In some embodiments, the first length of the first gate contact opening is about 2 to 3 times the second length of the second gate contact opening.

In some embodiments, the first gate contact opening exposes the work function layer of the first gate structure.

In some embodiments, the work function layer of the first gate structure comprises titanium aluminum.

In some embodiments, the first region and the second region are of opposite morphology.

In some embodiments, the first region provides a p-type well for forming n-type transistors, and the second region provides an n-type well for forming p-type transistors.

In some embodiments, the method further includes forming an isolation structure between the first fin and the second fin, wherein the isolation structure is higher than the first fin and the second fin and is partially embedded in the isolation structure.

In some embodiments, the width of the rectangle is substantially equal to the width of the gate structure.

In some embodiments, the length of the rectangle is from about 2 times to about 3 times the width.

In some embodiments, the gate structure comprises an aluminum-containing oxide and the step of etching the gate structure comprises applying an oxygen-containing etchant to produce an aluminum oxide-containing compound.

In some embodiments, the gate structure and the fin form an n-type transistor of the memory cell, and the gate contact electrically couples the gate structure to a word line of the memory cell.

In some embodiments, a lower surface of the first gate contact is lower than an upper surface of the first fin.

In some embodiments, the upper surface of the first gate contact is rectangular, the upper surface of the second gate contact is square, and the area of the rectangle is larger than the area of the square.

In some embodiments, the first gate contact is laterally offset from the first fin and the second gate contact is directly on the second fin.

The features of the above-described embodiments are helpful to those skilled in the art in understanding the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced above. It should also be understood by those skilled in the art that these equivalents may be substituted and/or modified without departing from the spirit and scope of the present invention.

Claims

1. A method of forming a semiconductor device, comprising:

providing a structure comprising a substrate having a first region and a second region, an isolation structure on the substrate, a first fin extending from the first region of the substrate through the isolation structure, a second fin extending from the second region of the substrate through the isolation structure, a first gate structure engaging the first fin, and a second gate structure engaging the second fin;

depositing a dielectric layer on the first gate structure and the second gate structure;

etching the dielectric layer to form a first gate contact opening exposing the first gate structure and a second gate contact opening exposing the second gate structure, wherein a first length of the first gate contact opening is greater than a second length of the second gate contact opening; and

conductive material is filled into the first gate contact opening and the second gate contact opening to form a first gate contact to engage the first gate structure and a second gate contact to engage the second gate structure.