KR100263764B1 - Method of forming contact in semiconductor device - Google Patents

Method of forming contact in semiconductor device Download PDF

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KR100263764B1
KR100263764B1 KR1019920011259A KR920011259A KR100263764B1 KR 100263764 B1 KR100263764 B1 KR 100263764B1 KR 1019920011259 A KR1019920011259 A KR 1019920011259A KR 920011259 A KR920011259 A KR 920011259A KR 100263764 B1 KR100263764 B1 KR 100263764B1
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South Korea
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polysilicon
layer
insulating film
mask
type thin
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KR1019920011259A
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Korean (ko)
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KR940001285A (en
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이헌철
이호석
김일욱
박해성
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for manufacturing contacts in semiconductor devices is provided to reduce the thickness of an insulating layer by forming a storage node contact using an island type thin film polysilicon and poly etch back bit lines. CONSTITUTION: A method for manufacturing contacts in semiconductor devices forms a field oxide film(3) on a given portion of a silicon substrate(1). A polysilicon layer(5), an insulating film(7) and an island type thin film polysilicon layer(9) are formed on the entire surface. An insulating layer is formed on the island type thin film polysilicon layer(9) and the island type thin film polysilicon layer(9), the insulating film(7) and the polysilicon layer(5) are then sequentially etched to form word lines. A spacer is formed at the sidewall. After depositing the insulating film(7) from the top of the word line, a given portion of the insulating film(7) is etched using the island type thin film polysilicon layer(9) as a barrier to form a bit line contact. An insulating layer(19) is deposited on the bit line to form a planarized structure. Mask polysilicon is deposited on the insulating layer(19). The mask polysilicon and a given portion of the insulating film are etched. Polysilicon is again deposited on it and is then etched to form a spacer polysilicon(18). The underlying insulating film(19) is etched using the spacer polysilicon(18) and the mask polysilicon(21) to form a contact(23) for a storage node.

Description

반도체소자의 콘택제조방법Contact manufacturing method of semiconductor device

제1도는 실리콘기판 상부에 워드라인을 형성하는 단계를 나타내는 반도체소자의 단면도.1 is a cross-sectional view of a semiconductor device showing a step of forming a word line on a silicon substrate.

제2도는 산화막을 식각하여 비트라인 콘택을 형성하고, 그 상부에 폴리실리콘을 증착한 후 비트라인을 형성하는 단계를 나타내는 반도체소자의 단면도.FIG. 2 is a cross-sectional view of a semiconductor device illustrating etching a oxide film to form a bit line contact, depositing polysilicon thereon, and then forming a bit line.

제3도는 폴리실리콘 스페이서를 마스크로 하여 하부의 절연막을 식각하여 저장노드 콘택홀을 형성하는 단계를 나타내는 반도체소자의 단면도.3 is a cross-sectional view of a semiconductor device illustrating a step of forming a storage node contact hole by etching a lower insulating film using a polysilicon spacer as a mask.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘 기판 3 : 필드 산화막1: silicon substrate 3: field oxide film

5 : 폴리실리콘층 7 : 절연막5: polysilicon layer 7: insulating film

9 : 아일랜드형 박막 폴리실리콘 11 : 스페이스9: island type thin film polysilicon 11: space

12 : 절연막 13 : 플러그 폴리실리콘12 insulating film 13 plug polysilicon

15 : 비트라인 콘택 17 : 비트라인15: bit line contact 17: bit line

18 : 스페이서 폴리실리콘 19 : 절연층18 spacer polysilicon 19 insulating layer

21 : 마스크 폴리실리콘 23 : 저장노드 콘택21: mask polysilicon 23: storage node contact

본 발명은 반도체소자의 콘택을 형성하는 방법에 관한 것이며, 특히, 에치백(Etch Back)기술과, 폴리스페이서 기술을 조합하여 콘택을 형성하는 방법에 관한 것이다.The present invention relates to a method of forming a contact of a semiconductor device, and more particularly, to a method of forming a contact by combining an etch back technique and a polyphase technique.

종래의 반도체소자의 콘택을 형성하는 방법에 있어서는, 폴리실리콘 스페이서 자기정렬 콘택방식을 비트라인 및 저장노드 콘택에 모두 사용함으로써, 절연막의 평탄화가 2번 진행하게 되어, 저장노드 콘택식각시 절연층의 두께가 두꺼워져서 식각시 많은 어려움이 따른다.In the conventional method of forming a contact of a semiconductor device, by using the polysilicon spacer self-aligned contact method for both the bit line and the storage node contact, planarization of the insulating film proceeds twice, so that the insulating layer during the storage node contact etching is performed. The thicker thickness brings a lot of difficulties when etching.

따라서, 상술한 문제점을 해결하기 위해, 본 발명 콘택을 형성할 때, 아일랜드형 박막 폴리실리콘 및 PEB(Poly Etch Back) 비트라인을 이용하여 저장노드 콘택을 형성하므로, 절연층의 두께를 줄일 수 있는 구조를 제공하는 것을 본 발명의 목적으로 한다.Therefore, in order to solve the above-described problems, when forming the contacts of the present invention, since the storage node contacts are formed using island-type thin-film polysilicon and polyetch back (PEB) bit lines, the thickness of the insulating layer can be reduced. It is an object of the present invention to provide a structure.

상기 목적을 달성하기 위해, 본 발명은 실리콘기판을 제공하는 단계와, 상기 실리콘기판 소정부분에 필드 산화막을 형성하는 단계와, 전체구조 상부에 폴리실리콘층, 절연막, 아일랜드형 박막 폴리실리콘층을 형성하는 단계와, 상기 아일랜드형 박막 폴리실리콘 상부에 절연층을 형성하고 마스크공정후, 하부의 아일랜드형 박막 폴리실리콘층, 절연막 및 폴리실리콘을 순차적으로 식각하여, 워드라인을 형성하고, 측벽에 스페이서를 형성하는 단계와, 상기 워드라인 상부로부터 절연막을 증착한 후, 마스크 공정 후, 아일랜드형 박막 폴리실리콘을 베리어로 절연막의 소정부분을 식각하여, 비트라인 콘택을 형성하는 단계와, 상기 비트라인 콘택내에 폴리실리콘을 충진시키고, 그 상부에 비트라인을 형성하는 단계와, 상기 비트라인 상부에 절연층을 증착시켜 평탄화된 구조를 형성하는 단계와, 상기 절연층 상부에 마스크 폴리실리콘을 증착하고, 마스크공정을 이용하여 상기 마스크 폴리실리콘 및 절연막 소정부분을 식각하고, 그 상부에 다시 폴리실리콘을 증착한 후, 식각하여 스페이서 폴리실리콘을 형성하는 단계와, 상기 스페이서 폴리실리콘 및 마스크 폴리실리콘을 이용하여 하부의 절연막을 식각하여, 저장노드용 콘택을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a step of providing a silicon substrate, forming a field oxide film on a predetermined portion of the silicon substrate, and forming a polysilicon layer, an insulating film, an island type thin film polysilicon layer on the entire structure And forming an insulating layer on the island-type thin film polysilicon, and after etching, the island-type thin film polysilicon layer, the insulating film, and polysilicon are sequentially etched to form a word line, and spacers are formed on the sidewalls. Forming a bit line contact by forming an insulating film from an upper portion of the word line, and etching a predetermined portion of the insulating film using an island-type thin-film polysilicon as a barrier after the mask process; and forming a bit line contact in the bit line contact. Filling polysilicon, forming a bitline thereon, and increasing an insulating layer on top of the bitline. Forming a planarized structure, depositing mask polysilicon on the insulating layer, etching a predetermined portion of the mask polysilicon and the insulating layer using a mask process, and depositing polysilicon on the upper part of the mask polysilicon Etching to form a spacer polysilicon, and etching a lower insulating layer using the spacer polysilicon and the mask polysilicon to form a contact for a storage node.

이하, 첨부된 도면으로 본 발명을 더욱 상세하게 설명하기로 한다.Hereinafter, the present invention will be described in detail with the accompanying drawings.

제1도는 실리콘기판(1)상에 워드라인을 형성하는 단계를 나타내는 반도체소자의 단면도로서, 실리콘기판(1) 소정부분에 필드 산화막(3)을 형성하고 실리콘기판(1) 및 필드 산화막(3)상에 폴리실리콘층(5)과 절연막(7)과 아일랜드형 폴리실리콘층(9)을 순차적으로 증착한 후 소정부분을 식각하여 워드라인을 형성한다. 그후, 워드라인 측벽에 스페이서(11)를 형성한다.1 is a cross-sectional view of a semiconductor device showing a step of forming a word line on a silicon substrate 1, wherein a field oxide film 3 is formed on a predetermined portion of the silicon substrate 1, and the silicon substrate 1 and the field oxide film 3 are formed. ), The polysilicon layer 5, the insulating film 7, and the island-type polysilicon layer 9 are sequentially deposited, and then a predetermined portion is etched to form a word line. Thereafter, spacers 11 are formed on the word line sidewalls.

제2도는 제1도의 공정후, 전체구조 상부로부터 절연막(12)을 형성하고, 절연막(11) 상부에 비트라인(17)을 형성하는 단계를 나타내는 반도체소자의 단면도로서, 절연막(12)의 소정부분을 식각하여, 비트라인 콘택(15)을 형성할 때, 워드라인의 최상부에 존재하는 얇은 아일랜드형 폴리실리콘(9)이 베리어로 되어 안정된 콘택(15)을 형성할 수 있다.FIG. 2 is a cross-sectional view of a semiconductor device showing a step of forming an insulating film 12 from above the entire structure and forming a bit line 17 over the insulating film 11 after the process of FIG. When the portion is etched to form the bit line contact 15, the thin island polysilicon 9 present at the top of the word line can be a barrier to form a stable contact 15.

그후, 상기 콘택(15) 상부로부터 플러그 폴리실리콘(13)을 증착하고 브랭킷(Blanket) 식각을 하여, 폴리실리콘(13)을 평탄화시킨다. 상기 평탄화된 폴리실리콘(13) 상부에 실리사이드를 증착하고 마스크 및 식각공정으로 비트라인(17)을 형성한다.Thereafter, the plug polysilicon 13 is deposited from the contact 15 and blanket etched to planarize the polysilicon 13. Silicide is deposited on the planarized polysilicon 13 and the bit line 17 is formed by a mask and an etching process.

제3도는 제2도의 공정후, 비트라인(17) 상부에 절연층(19) 및 마스크 폴리실리콘(21)을 증착하고, 폴리실리콘 스페이서(18)와 저장노드용 콘택(23)을 형성하는 단계를 나타내는 반도체소자의 단면도이며, 비트라인(17) 상부에 절연막(19)을 증착하여, 평탄화시키고, 그 상부에 마스크 폴리실리콘(21)을 증착시킨다. 그후, 마스크 폴리실리콘(21) 상부에 도시되지 않은 포토레지스트층을 코팅하고, 리소그래픽공정을 이용하여, 하부의 마스크 폴리실리콘(21) 및 절연막(19) 일부를 부분식각한 후, 다시 그 상부에 도시되지 않은 폴리실리콘을 증착하여, 블랭킷 식각으로 폴리실리콘 스페이서(18)를 형성한다. 그후, 폴리실리콘 스페이서(18) 및 마스크 폴리실리콘(21) 마스크로 하여 하부의 절연막(19)을 식각하고 저장노드용 콘택(23)을 형성한다. 이때, 하부의 평탄화된 절연막(19)이 식각될 때, 마스크 폴리실리콘(21)이 베리어로 작용하여, 상기 절연막(19)을 보호한다.3 shows depositing an insulating layer 19 and a mask polysilicon 21 on the bit line 17 after the process of FIG. 2, and forming a polysilicon spacer 18 and a contact for a storage node 23. A cross-sectional view of a semiconductor device, in which an insulating film 19 is deposited over the bit line 17 to planarize, and a mask polysilicon 21 is deposited over the bit line 17. Thereafter, a photoresist layer (not shown) is coated on the mask polysilicon 21, and part of the lower mask polysilicon 21 and the insulating film 19 are partially etched by using a lithographic process, and then again on the upper portion of the mask polysilicon 21. Polysilicon, not shown, is deposited to form polysilicon spacers 18 by blanket etching. Thereafter, the lower insulating film 19 is etched using the polysilicon spacers 18 and the mask polysilicon 21 mask to form the storage node contacts 23. At this time, when the lower planarized insulating film 19 is etched, the mask polysilicon 21 acts as a barrier to protect the insulating film 19.

이상에서 살펴본 바와같이, 본 발명은, 비트라인 콘택시에 아일랜드형 박막 폴리실리콘 및 PEB(Poly Etch Back) 비트라인 구조를 이용하여, 저장노드 콘택 식각시의 절연층 두께를 줄일 수 있는 효과가 있다.As described above, the present invention has an effect of reducing the thickness of the insulating layer during the etching of the storage node by using island type thin film polysilicon and a poly etch back (PEB) bit line structure during bit line contact. .

Claims (1)

반도체소자의 콘택을 형성하는 방법에 있어서, 실리콘기판(1)을 제공하는 단계와, 상기 실리콘기판(1) 소정부분에 필드 산화막(3)을 형성하는 단계와, 전체구조 상부에 폴리실리콘층(5), 절연막(7), 아일랜드형 박막 폴리실리콘층(9)을 형성하는 단계와, 상기 아일랜드형 박막 폴리실리콘(9) 상부에 절연층을 형성하고 마스크공정후, 하부의 아일랜드형 박막 폴리실리콘층(9), 절연막(7) 및 폴리실리콘(5)을 순차적으로 식각하여, 워드라인을 형성하고, 측벽에 스페이서(11)를 형성하는 단계와, 상기 워드라인 상부로부터 절연막(7)을 증착한 후, 마스크 공정 후, 아일랜드형 박막 폴리실리콘(9)을 베리어로 절연막(7)의 소정부분을 식각하여, 비트라인 콘택(15)을 형성하는 단계와, 상기 비트라인 콘택(15)내에 폴리실리콘을 충진시키고, 그 상부에 비트라인(17)을 형성하는 단계와, 상기 비트라인(17) 상부에 절연층(19)을 증착시켜 평탄화된 구조를 형성하는 단계와, 상기 절연층(19) 상부에 마스크 폴리실리콘을 증착하고, 마스크공정을 이용하여 상기 마스크 폴리실리콘 및 절연막 소정부분을 식각하고, 그 상부에 다시 폴리실리콘을 증착한 후, 식각하여 스페이서 폴리실리콘(18)을 형성하는 단계와, 상기 스페이서 폴리실리콘(18) 및 마스크 폴리실리콘(21)을 이용하여 하부의 절연막(19)을 식각하여, 저장노드용 콘택(23)을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 콘택 형성방법.A method of forming a contact of a semiconductor device, comprising: providing a silicon substrate 1, forming a field oxide film 3 on a predetermined portion of the silicon substrate 1, and forming a polysilicon layer on the entire structure ( 5) forming an insulating layer 7 and an island type thin film polysilicon layer 9, forming an insulating layer on the island type thin film polysilicon 9, and masking the island type thin film polysilicon Sequentially etching the layer 9, the insulating film 7 and the polysilicon 5 to form a word line, forming a spacer 11 on the sidewalls, and depositing the insulating film 7 from above the word line. After the mask process, a predetermined portion of the insulating film 7 is etched using the island-type thin-film polysilicon 9 as a barrier to form a bit line contact 15, and the poly within the bit line contact 15. Fill the silicon, and form the bit line 17 on top And depositing an insulating layer 19 on the bit line 17 to form a planarized structure, depositing mask polysilicon on the insulating layer 19, and using a mask process. Etching the mask polysilicon and a predetermined portion of the insulating film, depositing polysilicon on the upper portion of the mask polysilicon and the insulating layer, and then etching to form the spacer polysilicon 18; the spacer polysilicon 18 and the mask polysilicon 21; Etching the lower insulating film (19) to form a contact for the storage node (23).
KR1019920011259A 1992-06-26 1992-06-26 Method of forming contact in semiconductor device KR100263764B1 (en)

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KR940001285A KR940001285A (en) 1994-01-11
KR100263764B1 true KR100263764B1 (en) 2000-09-01

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