KR100340854B1 - Method for fabricating contact hole for forming capacitor of semiconductor device - Google Patents

Method for fabricating contact hole for forming capacitor of semiconductor device Download PDF

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Publication number
KR100340854B1
KR100340854B1 KR1019950019373A KR19950019373A KR100340854B1 KR 100340854 B1 KR100340854 B1 KR 100340854B1 KR 1019950019373 A KR1019950019373 A KR 1019950019373A KR 19950019373 A KR19950019373 A KR 19950019373A KR 100340854 B1 KR100340854 B1 KR 100340854B1
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forming
contact hole
capacitor
polysilicon
photoresist pattern
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KR1019950019373A
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Korean (ko)
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KR970003531A (en
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손진석
양예석
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주식회사 하이닉스반도체
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: A method for fabricating a contact hole for forming a capacitor of a semiconductor device is provided to increase a design margin by the width of a sidewall spacer by forming a sidewall spacer made of polysilicon on the sidewall of a portion where the contact hole for forming the capacitor is to be formed while using a process for forming the contact hole for fabricating a bitline and a process for forming the bitline. CONSTITUTION: The first interlayer dielectric(3) is deposited on a semiconductor substrate(1) having a filed oxide layer(2) and a MOS(Metal Oxide Semiconductor) transistor. A contact hole for forming the bitline and a temporary contact hole for forming the capacitor are formed. Polysilicon for the bitline is deposited and an ion implantation process is performed. A silicide layer and a nitride layer are sequentially deposited. The first photoresist pattern for forming the bitline is formed. The nitride layer, the silicide layer and the polysilicon for the bitline are etched to form the bitline by using the first photoresist pattern as an etch barrier while the sidewall spacer made of polysilicon is formed in a capacitor formation region. Residual photoresist is removed and the second interlayer dielectric(9) is formed. The second photoresist pattern for defining the contact hole for the capacitor is formed. The second interlayer dielectric is etched to form the contact hole for forming the capacitor by using the second photoresist pattern as an etch barrier. Residual photoresist is eliminated.

Description

반도체 소자의 캐패시터 형성을 위한 콘택홀 형성방법Contact hole formation method for capacitor formation of semiconductor device

본 발명은 일반적으로 반도체 소자 제조 방법에 관한 것으로서 특히 비트 라인을 형성하기 위한 콘택홀 형성 공정과 비트 라인을 제조하는 공정을 이용하여, 캐패시터을 형성하기 위한 콘택홀을 좀 더 용이하게 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a contact hole for forming a capacitor more easily using a contact hole forming process for forming a bit line and a process for manufacturing a bit line. will be.

반도체 소자가 고집적화되면서 셀 영역의 크기가 감소하여 콘택홀의 크기도 감소한다. 종래 캐패시터의 전하저장 전극을 형성하기 위한 콘택홀을 형성하는 방법으로는 콘택홀 형성시 식각 해야할 층간절연막이 두껍기 때문에 식각후 콘택홀의 상부 크기와 하부 크기의 차이가 크기에 정확한 콘택홀을 형성할 수 없다는 문제점을 가지고 있었다.As semiconductor devices are highly integrated, the size of the cell region is reduced, and the size of the contact hole is also reduced. As a method of forming a contact hole for forming a charge storage electrode of a conventional capacitor, since the interlayer insulating layer to be etched when forming the contact hole is thick, a contact hole can be formed with an accurate difference between the upper and lower portions of the contact hole after etching. Had the problem.

따라서, 전술한 바와 같은 문제점을 해결하기 위해 안출된 본 발명은 비트 라인을 형성하기 위한 콘택홑을 형성하는 공정과 비트 라인을 제조하는 공정을 이용하여 캐패시터를 형성하기 위한 콘택홀이 형성될 부분의 측벽에 폴리실리콘으로된 측벽 스페이서를 형성하므로써 측벽 스페이서의 폭 만큼의 디자인 여유도(Design Margin)을 증대시키고 좀 더 용이하게 캐패시터를 형성하기 위한 콘택홀을 형성하는 방법을 제공하는 것을 목적으로 한다.Accordingly, the present invention devised to solve the above-described problems is to provide a process for forming a single contact for forming a bit line and a portion for forming a contact hole for forming a capacitor using a process for manufacturing a bit line. An object of the present invention is to provide a method of forming a contact hole for increasing a design margin by the width of the sidewall spacer and forming a capacitor more easily by forming a sidewall spacer made of polysilicon on the sidewall.

본 발명의 캐패시터 형성을 위한 콘택홀 형성 방법은, 반도체 기판에 필드 산화막과 모스 트렌지스터가 형성된 구조상에 제 1 층간절연막을 증착하는 단계와, 비트 라인을 형성하기 위한 콘택홀과 캐패시터를 형성하기 위한 임시 콘택홀을 형성하는 단계와, 비트 라인용 폴리실리콘을 증착하고 이온주입을 실시한 후, 실리사이드막과 질화막을 차례로 증착하는 단계와, 비트 라인 형성을 위한 제 1 포토레지스트 패턴을 형성하고 상기 제 1 포토레지스트 패턴을 식각 배리어로 이용하여 상기 질화막, 상기 실리사이드막 및 상기 비트 라인용 폴리실리콘을 식각하여 비트 라인을 형성하고, 동시에 캐패시터가 형성될 영역에 폴리실리콘으로 이루어진 측벽 스페이서를 형성하는 단계와, 잔류 포토레지스트를 제거하고 제 2 층간절연막을 형성하는 단계 및 캐패시터를 형성하기 위한 콘택홀을 정의하는 제 2 포토레지스트 패턴을 형성한 후 상기 제 2 포토레지스트 패턴을 식각 베리어로 이용하여 상기 제2 층간절연막을 식각하여 캐패시터 형성을 위한 콘택홀을 형성하고 잔류 포토레지스트를 제거하는 단계를 포함하여 이루어진 것을 특징으로 한다.The method of forming a contact hole for forming a capacitor of the present invention comprises the steps of depositing a first interlayer insulating film on a structure in which a field oxide film and a MOS transistor are formed on a semiconductor substrate, and a temporary hole for forming a contact hole and a capacitor for forming a bit line. Forming a contact hole, depositing polysilicon for a bit line and performing ion implantation, depositing a silicide layer and a nitride layer in order, forming a first photoresist pattern for forming a bit line, and forming the first photo Forming a bit line by etching the nitride film, the silicide film and the polysilicon for the bit line using a resist pattern as an etching barrier, and simultaneously forming a sidewall spacer made of polysilicon in a region where the capacitor is to be formed; Removing the photoresist and forming a second interlayer dielectric film and caching After forming a second photoresist pattern defining a contact hole for forming a capacitor, the second interlayer insulating layer is etched using the second photoresist pattern as an etch barrier to form a contact hole for forming a capacitor and remaining. And removing the photoresist.

이제 본 발명의 캐패시터 형성을 위한 콘택홀 형성 방법의 실시예에 대하여 첨부도면을 참조하여 상세하게 살펴보게 된다. 먼저 제 1A도에 도시된 바와 같이 반도체 기판(1)에 필드 산화막(2)과 모스(MOS) 트렌지스터가 형성된 구조 상에 제 1 층간절연막(3)을 증착한다. 다음으로 제 1B도에 도시된 바와 같이 비트 라인(Bit Line)을 형성하기 위한 콘택홀과 캐패시터를 형성하기 위한 임시 콘택홀을 형성한다. 다음으로 제 1C도에 도시된 바와 같이 비트 라인용 폴리실리콘(4)을 증착하고 이온주입을 실시한 후, 실리사이드(siliside)막(5)과 질화막(6)을 차례로 증착한다. 다음으로 제 1D도에 도시된 바와 같이 비트 라인 형성을 위한 제 1 포토레지스트 패턴(7)을 형성하고 상기 제 1 포토레지스트 패턴(7)을 식각 배리어로 이용하여 상기 질화막(6), 상기 실리사이드막(5) 및 상기 비트 라인용 폴리실리콘(4)을 식각하여 비트 라인을 형성하고, 동시에 캐패시터가 형성될 영역에 폴리실리콘으로 이루어진 측벽 스페이서(8)를 형성한다. 다음으로 제 1E도에 도시된 바와 같이 잔류 포토레지스트를 제거하고 제 2 층간절연막(9)을 형성한다. 그리고 캐패시터를 형성하기 위한 콘택홀을 정의하는 제 2 포토레지스트 패턴을 형성한 후 상기 제 2 포토레지스트 패턴을 식각 배리어로 이용하여 상기 제 2 층간절연막(9)을 식각하여 캐패시터 형성을 위한 콘택홀을 형성하고 잔류 포토레지스트를 제거한다.An embodiment of a method for forming a contact hole for forming a capacitor of the present invention will now be described in detail with reference to the accompanying drawings. First, as shown in FIG. 1A, a first interlayer insulating film 3 is deposited on a structure in which a field oxide film 2 and a MOS transistor are formed on a semiconductor substrate 1. Next, as shown in FIG. 1B, a contact hole for forming a bit line and a temporary contact hole for forming a capacitor are formed. Next, as shown in FIG. 1C, the bit line polysilicon 4 is deposited and ion implanted, and then the silicide film 5 and the nitride film 6 are sequentially deposited. Next, as shown in FIG. 1D, a first photoresist pattern 7 for forming a bit line is formed, and the nitride film 6 and the silicide layer are formed using the first photoresist pattern 7 as an etch barrier. (5) and the bit line polysilicon 4 are etched to form bit lines, and at the same time, sidewall spacers 8 made of polysilicon are formed in the region where the capacitor is to be formed. Next, as shown in FIG. 1E, the residual photoresist is removed and the second interlayer insulating film 9 is formed. After forming a second photoresist pattern defining a contact hole for forming a capacitor, the second interlayer insulating layer 9 is etched using the second photoresist pattern as an etch barrier to form a contact hole for forming a capacitor. Form and remove residual photoresist.

반도체 소자 제조시, 전술한 바와 같은 본 발명에 따라 폴리실리콘으로 이루어진 측벽 스페이서를 형성하므로써 측벽 스페이서의 폭 만큼의 디자인여유도(Design Margin)을 증대시키고 좀 더 용이하게 캐패시터를 형성하기 위한 콘택홀을 형성할 수 있다.In manufacturing a semiconductor device, according to the present invention as described above, by forming a sidewall spacer made of polysilicon, a contact hole for increasing the design margin as much as the width of the sidewall spacer and forming a capacitor more easily is provided. Can be formed.

제 1A도 내지 제 1E도는 본 발명의 캐패시터 형성을 위한 콘택홀 형성 방법에 따른 공정도1A to 1E are process diagrams according to a contact hole forming method for forming a capacitor of the present invention.

※ 도면의 주요 부분에 대한 부호의 설명 ※※ Explanation of code about main part of drawing ※

1 : 반도체 기판 2 : 필드 산화막1: semiconductor substrate 2: field oxide film

3 : 제 1 층간절연막 4 : 비트 라인용 폴리실리콘3: first interlayer insulating film 4: polysilicon for bit line

5 : 실리사이드막 6 : 질화막5: silicide film 6: nitride film

7 : 제 1 포토레지스트 패턴7: first photoresist pattern

8 : 측벽스페이서 9 : 제 2 층간절연막8 side wall spacer 9 second interlayer insulating film

Claims (1)

캐패시터를 형성하기 위한 콘택홀을 형성하는 방법에 있어서,In the method of forming a contact hole for forming a capacitor, 반도체 기판에 필드 산화막과 모스 트렌지스터가 형성된 구조 상에 제 1 층간절연막을 증착하는 단계와,Depositing a first interlayer insulating film on a structure in which a field oxide film and a MOS transistor are formed on a semiconductor substrate; 비트 라인을 형성하기 위한 콘택홀과 캐패시터를 형성하기 위한 임시 콘택홀을 형성하는 단계와,Forming a contact hole for forming a bit line and a temporary contact hole for forming a capacitor; 비트 라인용 폴리실리콘을 증착하고 이온주입을 실시한 후, 실리사이드막과 질화막을 차례로 증착하는 단계와,Depositing polysilicon for bit lines and ion implantation, and then depositing a silicide film and a nitride film in sequence; 비트 라인 형성을 위한 제 1 포토레지스트 패턴을 형상하고 상기 제 1 포토레지스트 패턴을 식각 배리어로 이용하여 상기 질화막, 상기 실리사이드막 및 상기 비트 라인용 폴리실리콘을 식각하여 비트 라인을 형성하고, 동시에 캐패시터가 형성될 영역에 폴리실리콘으로 이루어진 측벽 스페이서를 형성하는 단계와;A bit line is formed by forming a first photoresist pattern for forming a bit line and etching the nitride film, the silicide layer, and the polysilicon for the bit line using the first photoresist pattern as an etch barrier. Forming sidewall spacers made of polysilicon in the region to be formed; 잔류 포토레지스트를 제거하고 제 2 층간절연막을 형성하는 단계 및,Removing residual photoresist and forming a second interlayer dielectric film; 캐패시터를 형성하기 위한 콘택홀을 정의하는 제 2 포토레지스트 패턴을 형성한 후 상기 제 2 포토레지스트 패턴을 식각 배리어로 이용하여 상기 제 2 층간절연막을 식각하여 캐패시터 형성을 위한 콘택홀을 형성하고 잔류 포토레지스트를 제거하는 단계를 포함하여 이루어진 캐패시터를 형성하기 위한 콘택홀 형성 방법.After forming a second photoresist pattern defining a contact hole for forming a capacitor, the second interlayer insulating layer is etched using the second photoresist pattern as an etch barrier to form a contact hole for forming a capacitor, and to form a residual photo. A method of forming a contact hole for forming a capacitor comprising the step of removing the resist.
KR1019950019373A 1995-06-30 1995-06-30 Method for fabricating contact hole for forming capacitor of semiconductor device KR100340854B1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04755A (en) * 1990-01-26 1992-01-06 Mitsubishi Electric Corp Semiconductor storage device and manufacture thereof
KR940010333A (en) * 1992-10-21 1994-05-26 김광호 Semiconductor memory device and manufacturing method thereof
JPH0738068A (en) * 1993-06-28 1995-02-07 Mitsubishi Electric Corp Semiconductor device and its manufacture

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04755A (en) * 1990-01-26 1992-01-06 Mitsubishi Electric Corp Semiconductor storage device and manufacture thereof
KR940010333A (en) * 1992-10-21 1994-05-26 김광호 Semiconductor memory device and manufacturing method thereof
JPH0738068A (en) * 1993-06-28 1995-02-07 Mitsubishi Electric Corp Semiconductor device and its manufacture

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