KR970003531A - Contact hole formation method for capacitor formation of semiconductor device - Google Patents

Contact hole formation method for capacitor formation of semiconductor device Download PDF

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Publication number
KR970003531A
KR970003531A KR1019950019373A KR19950019373A KR970003531A KR 970003531 A KR970003531 A KR 970003531A KR 1019950019373 A KR1019950019373 A KR 1019950019373A KR 19950019373 A KR19950019373 A KR 19950019373A KR 970003531 A KR970003531 A KR 970003531A
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KR
South Korea
Prior art keywords
forming
contact hole
capacitor
bit line
photoresist pattern
Prior art date
Application number
KR1019950019373A
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Korean (ko)
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KR100340854B1 (en
Inventor
손진석
양예석
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950019373A priority Critical patent/KR100340854B1/en
Publication of KR970003531A publication Critical patent/KR970003531A/en
Application granted granted Critical
Publication of KR100340854B1 publication Critical patent/KR100340854B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

반도체 소자 제조 방법Semiconductor device manufacturing method

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

종래 방법으로는 콘택홀 형성시 식각해야할 층간절연막이 두껍기 때문에 식각후 콘택홀의 상부 크기와 하부 크기의 차이가 크기에 정확한 콘택홀을 형성할 수 없다는 문제점을 해결하고자 함.In the conventional method, since the interlayer insulating layer to be etched when forming the contact hole is thick, the difference between the upper size and the lower size of the contact hole after etching is not sufficient to solve the problem of forming a contact hole.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

비트 라인을 형성하기 위한 콘택홀을 형성하는 공정과 비트 라인을 제조하는 공정을 이용하여 캐패시터를 형성하기 위한 콘택홀이 형성될 부분의 측벽에 폴리실리콘으로 된 측벽 스페이서를 형성하여 좀 더 용이하게 캐패시터를 형성하기 위한 콘택홀을 제조하고자 함.By using a process for forming a contact hole for forming a bit line and a process for manufacturing a bit line, a sidewall spacer made of polysilicon is formed on a sidewall of a portion where a contact hole for forming a capacitor is to be formed, thereby making the capacitor easier. To manufacture a contact hole to form a.

4. 발명의 중요한 용도4. Important uses of the invention

캐패시터를 형성하기 위한 콘택홀을 형성하는데 이용됨.Used to form contact holes for forming capacitors.

Description

반도체 소자의 캐패시터 형성을 위한 콘택홀 형성방법Contact hole formation method for capacitor formation of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 내지 제1E도는 본 발명의 캐패시터 형성을 위한 콘택홀 형성 방법에 따른 공정도.1A to 1E are process drawings according to the method for forming a contact hole for forming a capacitor of the present invention.

Claims (1)

캐패시터를 형성하기 위한 콘택홀을 형성하는 방법에 있어서, 반도체 기판에 필드 산화막과 모스 트렌지스터가 형성된 구조 상에 제1층간절연막을 증착하는 단계와, 비트 라인을 형성하기 위한 콘택홀과 캐패시터를 형성하기 위한 임시 콘택홀을 형성하는 단계와, 비트 라인용 폴리실리콘을 증착하고 이온주입을 실시한 후, 실리사이드막과 질화막을 차례로 증착하는 단계와, 비트 라인 형성을 위한 제1포토레지스트 패턴을 형성하고 상기 제1포토레지스트 패턴을 식각 배리어로 이용하여 상기 질화막,상기 실리사이드막 및 상기 비트 라인용 폴리실리콘을 식각하여 비트 라인을 형성하고, 동시에 캐패시터가 형성될 영역에 폴리실리콘으로 이루어진 측벽 스페이서를 형성하는 단계와, 잔류 포토레지스트를 제거하고 제2층간절연막을 형성하는 단계 및, 캐패시터를 형성하기 위한 콘택홀을 정의하는 제2포토레지스트 패턴을 형성한 후 상기 제2포토레지스트 패턴을 식각 배리어로 이용하여 상기 제2층간절연막을 식각하여 캐패시터 형성을 위한 콘택홀을 형성하고 잔류 포토레지스트를 제거하는 단계를 포함하여 이루어진 캐패시터를 형성하기 위한 콘택홀 형성 방법.A method of forming a contact hole for forming a capacitor, the method comprising: depositing a first interlayer insulating film on a structure in which a field oxide film and a MOS transistor are formed on a semiconductor substrate, and forming a contact hole and a capacitor for forming a bit line; Forming a temporary contact hole, depositing polysilicon for a bit line and performing ion implantation, and then depositing a silicide layer and a nitride layer, and forming a first photoresist pattern for forming a bit line. Forming a bit line by etching the nitride film, the silicide layer and the polysilicon for the bit line using an photoresist pattern as an etch barrier, and simultaneously forming a sidewall spacer made of polysilicon in a region where the capacitor is to be formed; Removing residual photoresist to form a second interlayer dielectric film; After forming a second photoresist pattern defining a contact hole for forming a capacitor, the second interlayer insulating layer is etched using the second photoresist pattern as an etch barrier to form a contact hole for forming a capacitor, and to form a residual photo. A method of forming a contact hole for forming a capacitor comprising the step of removing the resist. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950019373A 1995-06-30 1995-06-30 Method for fabricating contact hole for forming capacitor of semiconductor device KR100340854B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950019373A KR100340854B1 (en) 1995-06-30 1995-06-30 Method for fabricating contact hole for forming capacitor of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950019373A KR100340854B1 (en) 1995-06-30 1995-06-30 Method for fabricating contact hole for forming capacitor of semiconductor device

Publications (2)

Publication Number Publication Date
KR970003531A true KR970003531A (en) 1997-01-28
KR100340854B1 KR100340854B1 (en) 2002-10-31

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KR1019950019373A KR100340854B1 (en) 1995-06-30 1995-06-30 Method for fabricating contact hole for forming capacitor of semiconductor device

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Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2528731B2 (en) * 1990-01-26 1996-08-28 三菱電機株式会社 Semiconductor memory device and manufacturing method thereof
KR100278643B1 (en) * 1992-10-21 2001-02-01 윤종용 Semiconductor Memory Device Manufacturing Method
JPH0738068A (en) * 1993-06-28 1995-02-07 Mitsubishi Electric Corp Semiconductor device and its manufacture

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