KR970018745A - Capacitor Manufacturing Method of Semiconductor Device - Google Patents

Capacitor Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR970018745A
KR970018745A KR1019950029297A KR19950029297A KR970018745A KR 970018745 A KR970018745 A KR 970018745A KR 1019950029297 A KR1019950029297 A KR 1019950029297A KR 19950029297 A KR19950029297 A KR 19950029297A KR 970018745 A KR970018745 A KR 970018745A
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KR
South Korea
Prior art keywords
insulating film
film
forming
photoresist pattern
layer
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KR1019950029297A
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Korean (ko)
Inventor
심명섭
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김광호
삼성전자 주식회사
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Priority to KR1019950029297A priority Critical patent/KR970018745A/en
Publication of KR970018745A publication Critical patent/KR970018745A/en

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Abstract

단순한 공정으로 신뢰성 및 수율을 향상시킬 수 있는 반도체 장치의 제조방법에 관하여 개시한다. 본 발명은 트랜지스터가 형성된 반도체기판 상에 제1 절연막, 제2 절연막, 식각저지층 및 제3 절연막을 차례로 형성하는 단계와, 상기 제3 절연막 상에 제1 포토레지스트 패턴을 형성하는 단계와, 상기 제1 포토레지스트 패턴을 마스크로 상기 제3 절연막, 식각저지층, 제2 절연막 및 제1 절연막을 이방성 식각하여 소오스 또는 드레인을 노출하는 콘택홀을 형성하는 단계와, 상기 포토레지트 패턴을 이방성식각하여 폭이 확장된 제2 포토레지스트 패턴을 형성하는 단계와, 상기 제2 포토레지스트 패턴을 마스크로 상기 제3 절연막, 제1 질화막 및 제2 절연막의 일부를 이방성 식각하여 계단모양의 콘택홀을 형성하는 단계와, 상기 계단모양의 콘택홀이 형성된 기판의 전면에 제1 도전층을 형성하는 단계와, 상기 계단모양의 콘택홀을 매립하도록 제4 절연막을 형성하는 단계와, 상기 제4 절연막을 마스크로 하여 상기 제1 도전층을 이방성 식각하여 스토리지 노드를 형성하는 단계와, 상기 제4 절연막과 제3 절연막을 습식식각을 이용하여 제거하는 단계와, 상기 식각방지막을 습식식각을 이용하여 제거하는 단계와, 상기 결과물 전면에 유전체막 및 플레이트전극을 형성하여 커패시터를 형성하는 단계를 구비한다. 본 발명에 의하면, 스토리지 노드의 패턴형성을 자기정렬방식으로 하여 스토리지 노드 패턴에 의한 단락을 막을 수 있고, 식각방지막을 제거한 후 후속공정을 진행하여 공정을 단순화할 수 있고, 신뢰성 및 수율을 높일 수 있다.A manufacturing method of a semiconductor device capable of improving reliability and yield in a simple process is disclosed. The present invention provides a method of forming a first insulating film, a second insulating film, an etch stop layer, and a third insulating film on a semiconductor substrate on which a transistor is formed, and forming a first photoresist pattern on the third insulating film. Anisotropically etching the third insulating film, the etch stop layer, the second insulating film, and the first insulating film using a first photoresist pattern as a mask to form a contact hole exposing a source or a drain, and anisotropically etching the photoresist pattern. Forming a second photoresist pattern having a wider width, and anisotropically etching a part of the third insulating film, the first nitride film, and the second insulating film using the second photoresist pattern as a mask to form a stepped contact hole Forming a first conductive layer on an entire surface of the substrate on which the stepped contact holes are formed, and forming a fourth insulating layer to fill the stepped contact holes. Forming a storage node by anisotropically etching the first conductive layer using the fourth insulating layer as a mask, removing the fourth insulating layer and the third insulating layer by wet etching; Removing the etch stop layer by wet etching; and forming a dielectric film and a plate electrode on the entire surface of the resultant to form a capacitor. According to the present invention, the pattern formation of the storage node can be self-aligned to prevent short circuit due to the storage node pattern, and after the etch barrier is removed, a subsequent process can be performed to simplify the process and increase reliability and yield. have.

Description

반도체 장치의 커패시터 제조방법Capacitor Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2G도, 제3A도 내지 제3G도는 본 발명에 의한 반도체 장치의 커패시터 제조방법을 도시한 단면도이다.2A to 2G and 3A to 3G are sectional views showing the capacitor manufacturing method of the semiconductor device according to the present invention.

Claims (5)

트랜지스터가 형성된 반도체 기판 상에 제1 절연막, 제2 절연막, 식각저지층 및 제3 절연막을 차례로 형성하는 단계; 상기 제3 절연막 상에 제1 포토레지스트 패턴을 형성하는 단계; 상기 제1 포토레지스트 패턴을 마스크로 상기 제3 절연막, 식각저지층, 제2 절연막 및 제1 절연막을 이방성 식각하여 소오스 또는 드레인을 노출하는 콘택홀을 형성하는 단계; 상기 포토레지트 패턴을 이방성식각하여 폭이 확장된 제2 포토레지스트 패턴을 형성하는 단계; 상기 제2 포토레지스트 패턴을 마스크로 상기 제3 절연막, 제1 질화막 및 제2 절연막의 일부를 이방성 식각하여 계단모양의 콘택홀을 형성하는 단계; 상기 계단모양의 콘택홀이 형성된 기판의 전면에 제1 도전층을 형성하는 단계; 상기 계단모양의 콘택홀을 매립하도록 제4 절연막을 형성하는 단계; 상기 제4 절연막을 마스크로 하여 상기 제1 도전층을 이방성식각하여 스토리지 노드를 형성하는 단계; 상기 제4 절연막과 제3 절연막을 습식식각을 이용하여 제거하는 단계; 상기 식각방지막을 습식식각을 이용하여 제거하는 단계; 및 상기 결과물 전면에 유전체막 및 플레이트전극을 형성하여 커패시터를 형성하는 단계를 구비하여 이루어지는 것을 특징으로 하는 반도체 장치의 커패시터 제조방법.Sequentially forming a first insulating film, a second insulating film, an etch stop layer, and a third insulating film on the semiconductor substrate on which the transistor is formed; Forming a first photoresist pattern on the third insulating film; Anisotropically etching the third insulating film, the etch stop layer, the second insulating film, and the first insulating film using the first photoresist pattern as a mask to form a contact hole exposing a source or a drain; Anisotropically etching the photoresist pattern to form a second photoresist pattern having an expanded width; Anisotropically etching a portion of the third insulating film, the first nitride film, and the second insulating film using the second photoresist pattern as a mask to form a stepped contact hole; Forming a first conductive layer on an entire surface of the substrate on which the stepped contact holes are formed; Forming a fourth insulating film to fill the stepped contact hole; Forming a storage node by anisotropically etching the first conductive layer using the fourth insulating layer as a mask; Removing the fourth insulating film and the third insulating film by wet etching; Removing the etch stop layer by wet etching; And forming a capacitor by forming a dielectric film and a plate electrode on the entire surface of the resultant. 제1항에 있어서, 상기 제2 절연막은 평탄화가 용이한 BPSG막, 플라즈마 산화막 및 TEOS막 중에서 선택된 어느 하나인 것을 특징으로 하는 반도체 장치의 커패시터 제조방법.The method of claim 1, wherein the second insulating film is any one selected from a BPSG film, a plasma oxide film, and a TEOS film that is easily planarized. 제1항에 있어서, 상기 식각방지막은 상기 제2 절연막과 습식식각시 선택비가 큰 질화막인 것을 특징으로 하는 반도체 장치의 커패시터 제조방법.The method of claim 1, wherein the etch stop layer is a nitride layer having a large selectivity during wet etching with the second insulating layer. 제1항에 있어서, 상기 제4 절연막은 이동도가 큰 SOG막 또는 포토레지스트막인 것을 특징으로 하는 반도체 장치의 커패시터 제조방법.The method of claim 1, wherein the fourth insulating film is a SOG film or a photoresist film having high mobility. 제1항에 있어서, 상기 유전체막은 ONO막 또는 탄탈륨 산화막인 것을 특징으로 하는 반도체 장치의 커패시터 제조방법.The method of manufacturing a capacitor of a semiconductor device according to claim 1, wherein said dielectric film is an ONO film or a tantalum oxide film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950029297A 1995-09-07 1995-09-07 Capacitor Manufacturing Method of Semiconductor Device KR970018745A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8519393B2 (en) 2009-12-10 2013-08-27 Samsung Display Co., Ltd. Thin film transistor array panel and manufacturing method thereof
US8816475B2 (en) 2012-02-13 2014-08-26 SK Hynix Inc. Semiconductor devices including capacitors and methods of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8519393B2 (en) 2009-12-10 2013-08-27 Samsung Display Co., Ltd. Thin film transistor array panel and manufacturing method thereof
US8816475B2 (en) 2012-02-13 2014-08-26 SK Hynix Inc. Semiconductor devices including capacitors and methods of manufacturing the same

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