KR960026647A - Capacitor Manufacturing Method of Semiconductor Device - Google Patents

Capacitor Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR960026647A
KR960026647A KR1019940037495A KR19940037495A KR960026647A KR 960026647 A KR960026647 A KR 960026647A KR 1019940037495 A KR1019940037495 A KR 1019940037495A KR 19940037495 A KR19940037495 A KR 19940037495A KR 960026647 A KR960026647 A KR 960026647A
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South Korea
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conductive layer
forming
layer
mask
insulating
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KR1019940037495A
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Korean (ko)
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KR0146256B1 (en
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김석수
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김주용
현대전자산업 주식회사
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Priority to KR1019940037495A priority Critical patent/KR0146256B1/en
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Abstract

본 발명은 반도체소자의 캐패시터 제조방법에 관한 것으로, 반도체기판 상부에 하부절연층 및 제1절연막을 형성하고 그 상부에 상기 반도체기판에 콘택된 제1도전층을 형성한 다음, 상기 제1도전층 상부에 제2절연막과 제2도전층을 형성하고 콘택마스크보다 크게 형성된 마스크를 이용하여 상기 제2도전층과 일정두께의 제2절연막을 식각한 다음, 저장전극마스크를 이용한 식각공정으로 상기 제1절연막을 노출시키고 전체표면상부에 제3도전층을 형성한 다음, 이를 이방성식각하여 제3도전층 스페이서를 형성하고 상기 제2, 1절연막을 제거하여 표면적이 증가된 저장전극을 형성한 다음, 후공정에서 반도체소자의 고집적화에 충분한 정전용량을 갖는 캐패시터를 형성하여 반도체소자의 고집적화를 가능하게 하고 이에따른 반도체소자의 신뢰성을 향상시키는 기술이다.The present invention relates to a method for manufacturing a capacitor of a semiconductor device, wherein a lower insulating layer and a first insulating layer are formed on a semiconductor substrate, and a first conductive layer contacted to the semiconductor substrate is formed on the first conductive layer. The second insulating layer and the second conductive layer are formed on the upper portion, and the second conductive layer and the second insulating layer having a predetermined thickness are etched using a mask formed larger than the contact mask, and then the first process is etched using a storage electrode mask. After exposing the insulating film and forming a third conductive layer on the entire surface, and then anisotropically etching it to form a third conductive layer spacer, and removing the second and the first insulating film to form a storage electrode having an increased surface area, and then In the process, a capacitor having a capacitance sufficient for high integration of semiconductor devices is formed to enable high integration of semiconductor devices, thereby improving reliability of semiconductor devices. The key is technology.

Description

반도체소자의 캐패시터 제조방법Capacitor Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 내지 제1D도는 본 발명의 실시예에 따른 반도체소자의 캐패시터 제조공정을 도시한 단면도.1A to 1D are sectional views showing a capacitor manufacturing process of a semiconductor device according to an embodiment of the present invention.

Claims (7)

반도체기판 상부에 하부절연층 및 제1절연막을 순차적으로 형성하는 공정과, 콘택마스크를 이용한 식각공정으로 콘택홀을 형성하는 공정과, 상기 반도체기판에 접속되는 제1도전층을 형성하는 공정과, 상기 제1도전층 상부에 제2절연막과 제2도전층을 순차적으로 형성하는 공정과, 상기 제2도전층 상부에 제1감광막패턴을 형성하는 공정과, 상기 제1감광막패턴을 상기 제2도전층과 일정두께의 제2절연막을 식각하는 공정과, 상기 제1감광막패턴을 제거하는 공정과, 전체 표면상부에 제2감광막패턴을 제거하는 공정과, 상기 제2감광막패턴을 마스크로하여 상기 제1절연막을 노출시키는 공정과, 전체표면상부에 제3도전층을 형성하는 공정과, 제3도전층 스페이서를 형성하는 공정과, 상기 제2, 1절연막을 제거함으로써 표면적이 증가된 저장전극을 형성하는 반도체소자의 캐패시터 제조방법.Sequentially forming a lower insulating layer and a first insulating layer on the semiconductor substrate, forming a contact hole by an etching process using a contact mask, forming a first conductive layer connected to the semiconductor substrate, Sequentially forming a second insulating film and a second conductive layer on the first conductive layer, forming a first photosensitive film pattern on the second conductive layer, and forming the first photosensitive film pattern on the second conductive layer. Etching the layer and the second insulating film having a predetermined thickness, removing the first photoresist pattern, removing the second photoresist pattern on the entire surface, and using the second photoresist pattern as a mask. A process of exposing the first insulating film, a process of forming a third conductive layer over the entire surface, a process of forming a third conductive layer spacer, and forming a storage electrode having an increased surface area by removing the second and first insulating films; doing Method for manufacturing a capacitor of a semiconductor device. 제1항에 있어서, 상기 제1, 2, 3도전층은 단차피복비가 우수한 도전체로 형성되는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 1, wherein the first, second, and third conductive layers are formed of a conductor having excellent step coverage ratio. 제1항에 있어서, 상기 제1감광막패턴은 상기 콘택마스크보다 크고 상기 저장전극마스크보다 작게 형성되는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 1, wherein the first photoresist pattern is larger than the contact mask and smaller than the storage electrode mask. 제1항에 있어서, 상기 제2감광막패턴은 저장전극마스크를 이용한 식각공정으로 형성되는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 1, wherein the second photoresist pattern is formed by an etching process using a storage electrode mask. 제1항에 있어서, 상기 제2감광막패턴은 이용한 식각공정은 상기 제1절연막을 식각장벽으로하여 실시되는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 1, wherein the etching process using the second photoresist layer pattern is performed by using the first insulation layer as an etch barrier. 제1항에 있어서, 상기 제2, 1절연막 제거공정은 상기 제3, 2, 1도전층과의 식각선택비차이를 이용하는 습식방법으로 실시되는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 1, wherein the removing of the second and first insulating layers is performed by a wet method using an etching selectivity difference with the third, second and first conductive layers. 제6항에 있어서, 상기 습식방법은 HF 또는 BOE 용액이 이용되는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.7. The method of claim 6, wherein the wet method uses HF or BOE solution. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940037495A 1994-12-27 1994-12-27 Method for manufacturing capacitor of semiconductor device KR0146256B1 (en)

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KR1019940037495A KR0146256B1 (en) 1994-12-27 1994-12-27 Method for manufacturing capacitor of semiconductor device

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KR1019940037495A KR0146256B1 (en) 1994-12-27 1994-12-27 Method for manufacturing capacitor of semiconductor device

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KR960026647A true KR960026647A (en) 1996-07-22
KR0146256B1 KR0146256B1 (en) 1998-11-02

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