KR950025997A - Capacitor Manufacturing Method of Semiconductor Device - Google Patents

Capacitor Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR950025997A
KR950025997A KR1019940003763A KR19940003763A KR950025997A KR 950025997 A KR950025997 A KR 950025997A KR 1019940003763 A KR1019940003763 A KR 1019940003763A KR 19940003763 A KR19940003763 A KR 19940003763A KR 950025997 A KR950025997 A KR 950025997A
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South Korea
Prior art keywords
film
forming
oxide film
polysilicon
charge storage
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KR1019940003763A
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Korean (ko)
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KR0158906B1 (en
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박상훈
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김주용
현대전자산업 주식회사
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Priority to KR1019940003763A priority Critical patent/KR0158906B1/en
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 반도체 소자의 캐패시터 형성방법에 관한 것으로, 특히 스택 구조의 캐패시터를 제조할 때 전하저장 전극의 표면적을 증대시키기 위하여 비트라인을 일정높이 갖도록 형성하고, 비트라인의 상부에 까지 전하저장전극이 연장되도록 하면서, 돌출된 비트라인의 표면에 전이금속막에 의한 실리사이드의 형성으로 소자의 동작 속도를 개선함과 아울러 전하저장전극과 비트라인 사이에는 전이금속산화막을 형성함으로써 소자의 절연효과를 증대시킬수 있는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a capacitor of a semiconductor device. In particular, when manufacturing a capacitor having a stacked structure, the bit line is formed to have a certain height in order to increase the surface area of the charge storage electrode. While extending, the formation of silicide by the transition metal film on the surface of the protruding bit line improves the operation speed of the device and increases the insulation effect of the device by forming a transition metal oxide film between the charge storage electrode and the bit line. It is a skill.

Description

반도체소자의 캐패시터 제조방법Capacitor Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2D도는 본 발명에 의해 캐패시터를 형성하는 단계를 도시한 단면도.2A through 2D are cross-sectional views illustrating steps of forming a capacitor according to the present invention.

Claims (5)

반도체 소자의 캐패시터 제조방법에 있어서, 실리콘 기판상부에 게이트전극, 소오스/드레인영역이 구비된 트랜지스터를 형성하는 단계와, 상기 트랜지스터의 전체구조상부에 절연용 산화막, 질화막 및 평탄화용 산화막을 순차적으로 형성하는 단계와, 비트라인 콘택부위의 평탄화용 산화막, 질화막, 절연용 산화막을 제거하여 소오스/드레인 영역이 노출된 콘택홀을 형성하고, 전체구조 상부에 제1폴리실리콘막을 형성하는 단계와, 상기 제1폴리실리콘막을 상기 평탄화용 산화막이 노출되기 까지 식각하여 상기 콘택홀에만 제1폴리실리콘막을 남겨 일정 높이를 갖는 비트라인 패턴을 형성하는 단계와, 상기 평탄화용산화막을 제거하고 전이금솜막 및 질화막을 전체구조 상부에 형성한 후에, 고온 열처리하여 상기 비트라인의 표면부에 있는 전이금속막은 실리사이드로 형성되게 하고, 질화막의 표면의 전이금속막은 전이 금속산화막으로 형성되도록 하는 단계와, 전하저장전극 콘택영역의 질화막, 전이금속산화막, 질화막, 산화막을 순차적으로 식각하여 소오스/드레인 영역이 노출된 콘택홀을 형성하고, 전체구조 상부에 제2폴리실리콘막을 증착하는 단계와, 전하저장전극 마스크를 이용한 사진식각공정으로 상기 제2폴리실리콘막을 패턴으로 이루어진 전하저장전극을 형성하고 그 상부에 유전체막과 플레이트전극을 형성하여 표면적이 증대된 캐패시터를 형성하는 단계를 포함하는 반도체 소자의 캐패시터 제조방법.A method of manufacturing a capacitor of a semiconductor device, comprising: forming a transistor having a gate electrode and a source / drain region on a silicon substrate, and sequentially forming an insulating oxide film, a nitride film, and a planarizing oxide film over the entire structure of the transistor. Forming a contact hole exposing the source / drain regions by removing the planarizing oxide film, the nitride film, and the insulating oxide film of the bit line contact portion, and forming a first polysilicon film on the entire structure; Etching the polysilicon film until the planarization oxide film is exposed to form a bit line pattern having a predetermined height, leaving the first polysilicon film only in the contact hole; and removing the planarization oxide film and removing the transition gold film and nitride film. After forming on top of the whole structure, a high temperature heat treatment is followed by a transition metal film on the surface of the bit line. Silver silicide and a transition metal film on the surface of the nitride film are formed of a transition metal oxide film, and the source / drain regions are exposed by sequentially etching the nitride film, the transition metal oxide film, the nitride film, and the oxide film of the charge storage electrode contact region. Forming a contact hole, depositing a second polysilicon film on the entire structure, and forming a charge storage electrode formed by patterning the second polysilicon film by a photolithography process using a charge storage electrode mask, and forming a dielectric on the A method for manufacturing a capacitor of a semiconductor device comprising the step of forming a film and a plate electrode to form a capacitor having an increased surface area. 제1항에 있어서, 상기 전하저장전극 마스크를 이용한 사진식각공정으로 상기 제2폴리실리콘막패턴으로 이루어진 전하저장전극을 형성할 때 상기 비트라인 제2폴리실리콘막을 일정부분 식각하여 이웃하는 전하저장전극들과 상호 분리되도록 하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The charge storage electrode of claim 1, wherein the bit line second polysilicon layer is partially etched when the charge storage electrode including the second polysilicon layer pattern is formed by a photolithography process using the charge storage electrode mask. Capacitor manufacturing method of a semiconductor device characterized in that it is separated from each other. 제1항에 있어서, 상기 제1폴리실리콘막의 표면부에는 실리사이드가 형성되게 하고, 질화막의 표면에는 전이 금속산화막이 형성되도록 하는 고온 열처리는 800℃ 이상의 확산로에서 실시하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The semiconductor device according to claim 1, wherein the high temperature heat treatment is performed in a diffusion furnace of 800 ° C. or higher so that silicide is formed on the surface of the first polysilicon film and a transition metal oxide film is formed on the surface of the nitride film. Capacitor Manufacturing Method. 반도체 소자의 캐패시터 제조방법에 있어서, 실리콘 기판상부에 게이트전극, 소오스/드레인영역이 구비된 트랜지스터를 형성하는 단계와, 상기 트랜지스터의 전체구조상부에 절연용 산화막, 질화막 및 평탄화용 산화막을 순차적으로 형성하는 단계와, 비트라인 콘택부위의 평탄화용 산화막, 질화막, 절연용 산화막을 제거하여 소오스/드레인 영역이 노출된 콘택홀을 형성하고, 전체구조 상부에 제1폴리실리콘막을 형성하는 단계와, 상기 제1폴리실리콘막을 상기 평탄화용 산화막이 노출되기 까지 식각하여 상기 콘택홀에만 제1폴리실리콘막을 남겨 일정 높이를 갖는 비트라인 패턴을 형성하는 단계와, 상기 평탄화용 산화막을 제거하고 전이금속막 및 질화막을 전체구조 상부에 형성한후에, 고온 열처리하여 상기 비트라인의 표면부에 있는 전이금속막은 실리사이드로 형성되게하고, 질화막 표면의 전이금속막은 전이금속산화막으로 형성되도록 하는 단계와, 전하저장전극 콘택영역의 질화막, 전이금속산화막, 질화막, 산화막을 순차적으로 식각하여 소오스/드레인 영역이 노출된 콘택홀을 형성하고,전체구조 상부에 제2폴리실리콘막을 증착하는 단계와, 전하저장전극 마스크를 이용한 사진식각공정으로 상기제2폴리실리콘막패턴을 형성하고, 전체구조 상부에 CVD 산화막을 도포하고 상기 전하저장전극이 노출되도록한 CVD산화막 패턴을 형성하는 단계와, 전체구조 상부에 제3폴리실리콘막을 증착하고, 제3폴리실리콘막의요흠에 감광막을 채우는 단계와, 노출된 제3폴리실리콘막을 식각하여 제2폴리실리콘막과 전기적으로 접속되고,실린더형상의 전하저장전극을 형성하는 단계와, 남아있는 감광막을 제거하고, 전하저장전극의 표면에 유전체막과 플레이트전극을 형성하여 캐패시터의 표면적을 증대시키는 단계를 포함하는 반도체 소자의 캐패시터 제조방법.A method of manufacturing a capacitor of a semiconductor device, comprising: forming a transistor having a gate electrode and a source / drain region on a silicon substrate, and sequentially forming an insulating oxide film, a nitride film, and a planarizing oxide film over the entire structure of the transistor. Forming a contact hole exposing the source / drain regions by removing the planarizing oxide film, the nitride film, and the insulating oxide film of the bit line contact portion, and forming a first polysilicon film on the entire structure; Etching the polysilicon film until the planarization oxide film is exposed to form a bit line pattern having a predetermined height, leaving the first polysilicon film only in the contact hole; removing the planarization oxide film and removing the transition metal film and the nitride film. After forming on top of the whole structure, a high temperature heat treatment is followed by a transition metal film on the surface of the bit line. Silver silicide, and the transition metal film on the surface of the nitride film are formed of a transition metal oxide film, and the nitride film, the transition metal oxide film, the nitride film, and the oxide film of the charge storage electrode contact region are sequentially etched to expose the source / drain regions. Forming a contact hole, depositing a second polysilicon layer on the entire structure, forming the second polysilicon layer pattern by a photolithography process using a charge storage electrode mask, and applying a CVD oxide layer on the entire structure. Forming a CVD oxide film pattern for exposing the charge storage electrode, depositing a third polysilicon film on the entire structure, filling a photoresist film with the recesses of the third polysilicon film, and etching the exposed third polysilicon film Forming a cylinder-shaped charge storage electrode electrically connected to the second polysilicon film, and I, and the capacitor manufacturing method of the semiconductor device by forming a dielectric film and a plate electrode on the surface of the charge storage electrode comprising the step of increasing the surface area of the capacitor. 제4항에 있어서, 상기 전하저장전극 마스크를 이용한 사진식각공정으로 상기 제2폴리실리콘막을 형성할때상기 비트라인 상부에서 제2폴리실리콘막을 일정부분 식각하여 이웃하는 제2폴리실리콘막이 상호 분리되도록하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The method of claim 4, wherein when forming the second polysilicon layer by a photolithography process using the charge storage electrode mask, a portion of the second polysilicon layer is etched on the bit line to separate neighboring second polysilicon layers from each other. A method for manufacturing a capacitor of a semiconductor device, characterized in that. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940003763A 1994-02-28 1994-02-28 Manufacture of semiconductor memory device KR0158906B1 (en)

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KR1019940003763A KR0158906B1 (en) 1994-02-28 1994-02-28 Manufacture of semiconductor memory device

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KR950025997A true KR950025997A (en) 1995-09-18
KR0158906B1 KR0158906B1 (en) 1998-12-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030006423A (en) * 2001-07-12 2003-01-23 주식회사 포스코 Induction motor driver circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030006423A (en) * 2001-07-12 2003-01-23 주식회사 포스코 Induction motor driver circuit

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