TWI227915B - Method of forming a gate structure - Google Patents

Abstract

A substrate is provided. A gate oxide layer, a polysilicon layer, a silicate layer, and a cap layer are consecutively formed onto the substrate. Then, an etching process is performed to etch a portion of the cap layer, the silicate layer, and the polysilicon layer and stop on the polysilicon layer for forming a stacked gate. Thereafter, a portion of the silicate layer exposed on sidewalls of the stacked gate is removed to form a recess. A passivation layer is deposited to fill the recess. The remaining polysilicon layer and the gate oxide layer are removed.

Description

1227915 V. Description of the invention (1) '----- The technical field to which the invention belongs The present invention provides a method for making a gate electrode, especially a avoidable element line (w 0 rd 1 ine) and a bit line (bit 1 ine) short-circuited gate;

A dynamic random access memory (DR A Μ) is an aggregate of a plurality of memory units (me m r r y c e 1 1). Each memory cell is formed by stacking and connecting a metal oxide semiconductor (MOS) transistor and a Γ capacitor (capaci tor). The gate of the M0S transistor is the so-called word line, which is used to control the switching of the M0S transistor channel, and the drain or source of the M0S transistor is connected to a bit line for data writing or Erase. Please refer to Figure 1 and Figure 2. Figures 1 and 2 are schematic diagrams of the method for making gates in the conventional method. As shown in FIG. 1, a semiconductor substrate 10 is first provided, and the semiconductor substrate 10 includes at least one stacked gate electrode 12. The stacked gates 12 include a gate insulating layer 14, a polycrystalline stone layer 16, a petrified metal layer 18 and a cap layer 20 in order from bottom to top. Then, as shown in FIG. 2, a chemical vapor deposition process is performed.

Page 7 1227915 V. Description of the invention (2) A silicon nitride layer (not shown) is deposited on the conductive substrate 10, and then an anisotropic coining process is used to form a sidewall on the sidewall of the stacked gate 12 twenty two. After the sidewalls 22 are completed, an ion layout process is performed to form a drain and a source in the semiconductor substrate 10 (not shown). The conventional method of manufacturing DRAM includes the steps of forming bits to lines after the fabrication of stacked gate 12 is completed. Please refer to FIGS. 3 to 5, which are schematic diagrams of a conventional method for forming a bit line. As shown in FIG. 3, after the fabrication of the stacked gate 12 is completed, a barrier layer 24 is deposited on the semiconductor substrate 10 and the stacked gate 12, and then a borophosphosilicategiass (BPSG) layer is deposited. 26. A heat flow process is performed to planarize the borophosphosilicate glass layer 26, and finally a chemical mechanical polishing process is performed to remove the boron-filled silica glass layer 26 higher than the cap layer 20. The material and quality of the barrier layer 24 is silicon nitride, which is used to prevent the ions of the borophosphosilicate glass layer 26 from being doped into the semiconductor substrate 10 during the heat flow process. Next, as shown in FIG. 4, a dielectric layer 28, such as tetraethoxysilane (TE0S), is deposited on the stacked gates 12, and then a yellow light and etching are used to remove the divided dielectric layers 28, The borophosphosilicate glass layer 26 and the barrier layer 24 are formed to form a 22-hole 30 ° contact. Finally, as shown in FIG. 5, a bit line 32 is formed, and the drain hole or the semiconductor substrate 10 is contacted via the contact hole. Source (not shown in Figure 5 47) electrical connection ',

1227915 V. Description of the invention (3) From the above, it is known that the conventional method uses the side wall 2 2 to avoid bit lines and word lines (ie, the polycrystalline silicon layer 16 and the silicided metal layer 1 8 in the stacked gate 12). In the case of a short circuit, however, with the increase of the semiconductor element accumulation and the decrease of the line width, the formation of the contact hole 30 often destroys part of the sidewall 2 structure, as shown in Figure 4. In this case, the bit line 3 2 poles: the silicon silicide layer 18 contacts and a short circuit occurs, especially in the case of a semi-conductor process line width below 0.1 1 micron, the short circuit between the word line and the bit line is more problematic. serious. Invention: Therefore, the main object of the present invention is to provide a method for fabricating a gate electrode to solve the problems of the conventional techniques. To achieve the above object, the present invention discloses a method for fabricating a gate, which includes the following steps: First, a semiconductor substrate is provided, and a gate insulating layer, a polycrystalline silicon layer, and a silicided metal (si) are sequentially formed on the semiconductor substrate. 1 icate) layer and a cap 1 ayer layer. Next, a part of the cap layer, the silicided metal layer, and the polycrystalline silicon layer are engraved and stopped on the polycrystalline silicon layer to form a stacked gate structure. Then, a part of the silicided metal layer exposed on the side wall of the stacked gate is removed to form a gap on the side wall of the stacked gate. Finally, a protective layer is filled into the gap, and the polycrystalline silicon layer and the gate insulating layer remaining outside the sidewall of the stacked gate are removed.

1227915 V. Description of the invention (4) As can be seen from the above, the method for fabricating the gate disclosed in the present invention is to form a gap on the side wall of the stacked gate and fill a protective layer to avoid short circuit between the word line and the bit line. In addition, since the polycrystalline silicon layer under the side wall of the stacked gate has not been removed when the notch is formed, the gate insulating layer below the stacked gate structure will not be damaged by the etching solution when the notch is formed to affect the gate insulating layer. function. In order to make your reviewers understand the features and technical contents of the present invention more closely, please refer to the following detailed description and drawings of the present invention. However, the drawings are only for reference and auxiliary explanation, and are not intended to limit the present invention. Embodiments Please refer to Figs. 6 to 10, which are schematic diagrams of a method for manufacturing a gate electrode according to the present invention. First, as shown in FIG. 6, a semiconductor substrate 50 is provided, and a gate insulating layer 5 2 is sequentially formed thereon. A polycrystalline silicon layer 54, a petrified metal layer 56, a cap layer 58 and Nitric oxide stone layer 60. In a preferred embodiment of the present invention, the material of the polycrystalline silicon layer 54 is doped polycrystalline silicon with a thickness of about 800 Å, and the material of the silicide metal layer 56 is tungsten silicide (W six) with a thickness of about 800 A, and the material of the top cap layer 58 is silicon nitride, and its thickness is about 16 00 A, but it is not limited to this.

Page 10 1227915 V. Description of the invention (5) '~ — As shown in FIG. 7, a photoresist layer is coated on the silicon oxynitride layer 60 (ff' is not shown in the figure) and an exposure and development process is used to remove the part The photoresist layer (not shown in the figure) is used to form a photoresist pattern 6 2, and then the photoresist pattern 6 2 is used as a hard mask to etch the silicon oxynitride layer 6 2 that is not covered by the photoresist pattern 6 2 As shown in FIG. 8, the photoresist pattern 62 is first removed, and the remaining ^ oxide layer 60 is used as a hard mask to etch away the cap layer 5 8 which is not covered by the silicon oxynitride layer 60. , A silicided metal layer 56 and a portion of the polycrystalline silicon layer 54 and stop thereon to form a stacked gate structure 64. 7

As shown in FIG. 9, a coin engraving process is then performed. An APM (ammonium hydro gen peroxide mixture) solution is used as the wormhole fluid to etch away part of the petrified metal layer on the side wall of the gate structure β 4 of the stacked gate structure. Into a gap 66. In a preferred embodiment of the present invention, the ratio of the AρM solution is approximately NΗ40Η: Η20 2: Η20 = 1: 1: 50. Finally, as shown in FIG. 10, an etching process is performed to remove the non-silicon oxynitride. The polycrystalline stone layer 54 covered by the layer 60 and the gate insulating layer 52. Then, a silicon nitride layer 68 is deposited and fills the gap 66, and then another etching process is performed to remove the silicon nitride layer 68 outside the gap 66, thereby completing the fabrication of the stacked gate structure 64 of the present invention. It is worth noting that the remaining part of the polycrystalline silicon layer 54 when the notches 66 are formed is to prevent the APM solution from damaging the gate insulating layer 52 and affecting the function of the gate insulating layer 52. In addition, the nitrided layer 6 8 filled in the gap 6 6 is used as a protective layer to avoid short word line / bit line in subsequent processes.

1227915 V. Description of Invention (6) Road. As described in the conventional technology, after the fabrication of the stacked gate structure 64 of the present invention, a step of forming a bit line is required to form a complete memory cell. However, the method for forming a bit line in the present invention is the same as the conventional method, and details are not described herein again. In addition, this embodiment uses a silicon nitride oxide layer 60 as a hard cover.

To form the stacked gate structure 64 of the present invention. However, the method for forming the stacked gate structure 64 is not limited to this. The present invention can also use the cap layer 5 8 as a hard cover to form the stacked gate structure 64. Compared with the conventional technology, the method for manufacturing the gate electrode of the present invention forms a gap in the side wall of the stacked gate, and fills a protective layer in the gap to prevent the subsequent formation of a bit line. A word line / bit line short circuit occurs. The problem. In addition, in order to prevent the gate insulating layer from being broken when the gap is formed, the present invention retains a portion of the polycrystalline silicon layer on the outside of the side wall of the stacked gate during the formation of the gap. After the gap is formed, the remaining polycrystalline silicon layer is removed.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the patent of the present invention.

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Figures 1 and 2 are schematic diagrams of the conventional method for making gates. Figures 3 to 5 are schematic diagrams of the conventional method for forming bit lines. Figures 6 to 10 are the gates of the present invention. Schematic diagram of the pole method 〇 Symbol description 10 Half: shirt ΓΤ body base 12 stacked gate 14 pole insulation layer 16 polycrystalline silicon layer 18 silicided metal layer 20 cap layer 2 2 side wall 24 barrier layer 2 6 borophosphosilicate glass Under layer 28, 30 contact holes 32 bit lines 50 semiconductor substrate 5 2 gate insulating layer 54 polycrystalline silicon layer 56 shattered metal layer 5 8 top cap layer 60 silicon oxynitride layer 6 2 photoresist pattern 64 stacking electrode 66 missing a 6 8 silicon nitride layer

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Claims (1)

1227915 VI. Scope of patent application 1. A method for manufacturing a gate, comprising: providing a semiconductor substrate, and sequentially forming a gate insulating layer, a polycrystalline layer, and a petrochemical metal on the semiconductor substrate ( si 1 icate) layer and a cap layer; a portion of the cap layer, the petrified metal layer, and the polycrystalline chopped layer are engraved and stopped on the polycrystalline polycrystalline layer to form a stack A stacked gate structure, removing a part of the silicided metal layer exposed on the side wall of the stacked gate to form a gap in the side wall of the stacked gate; filling a protective layer in the gap; and The polycrystalline silicon layer and the gate insulating layer remaining outside the sidewalls of the stacked gate are removed. 2. The method for fabricating a gate as described in the first item of the patent application, wherein the method for forming the stacked gate structure includes: coating a photoresist layer on the top cover layer; using a photomask to perform an exposure and A developing process, removing a part of the photoresist layer to form a patterned photoresist pattern; and The patterned photoresist pattern is used as a hard mask to remove the cap layer, the silicided metal layer, and part of the polysilicon layer that are not covered by the patterned photoresist pattern. 3. The method for fabricating a gate as described in item 2 of the patent application, after removing the polycrystalline silicon layer and the gate insulation layer remaining outside the side wall of the stacked gate, further includes Page 14 1227915 VI. Scope of patent application There is a step of removing the patterned photoresist layer. 4. The method for fabricating a gate electrode according to item 1 of the patent application, wherein the method for forming the stacked gate structure comprises: forming a patterned silicon oxynitride layer on the cap layer; and using the patterned nitrogen The silicon oxide layer serves as a hard mask to remove the cap layer, the silicided metal f, and a portion of the polycrystalline silicon layer that are not covered by the patterned silicon oxynitride layer. 5. The system described in item 4 of the application patent: the method of i gate removes the polycrystalline silicon layer and the gate insulating layer remaining outside the side wall of the stacked gate, and further includes a method for removing the patterned oxynitride layer. step. 6. The method for fabricating a gate electrode according to item 1 of the patent application, wherein the silicided metal layer includes tungsten silicide. 7. The method for manufacturing a gate electrode as described in item 1 of the patent application, wherein the gap 4 is formed by removing part of the silicided metal layer with an APM (ammonium hydrogen peroxide mixture) solution. 8. The method for fabricating a gate electrode according to item 1 of the patent application, wherein the protective layer includes silicon nitride. 9. The method for making a gate as described in the first patent application, wherein Page 15 1227915 VI. The method for filling the protective layer in the scope of patent application includes: depositing a silicon nitride layer on the polycrystalline silicon layer and filling the gap; and performing an anisotropic (anis 〇tr 〇) pic) The silicon etch process removes the silicon nitride layer outside the gap. 1 0. A method for making a gate includes: providing a semiconductor substrate, and sequentially forming a gate insulating layer on the semiconductor substrate; a polycrystalline silicon layer; and a broken metal (s 1 1 1 cate) layer and a cap layer; forming a pattern mask layer on the cap layer, etching the cap layer and the silicidation which are not covered by the pattern mask layer A metal layer and a part of the polycrystalline silicon layer and stopping on the polycrystalline silicon layer to form a stacked gate structure; using an etching solution to remove a part of the silicided metal layer exposed on the side wall of the stacked gate to form a gap; A protective layer is deposited on the polycrystalline stone layer to fill the gap, and an anisotropic (anis 〇tr 〇pic) process is performed to remove the protective layer outside the gap; remove the mask that is not covered by the patterning The polycrystalline silicon layer and the gate insulating layer covered by the mask layer; and removing the patterned mask layer. 1227915 VI. Application scope of patent 1 2. The method for fabricating a gate electrode as described in item 10 of the patent application, wherein the method of forming the patterned masking layer includes: forming a silicon oxynitride layer on the top cover layer ; I: a photoresist layer on the silicon oxynitride layer; using a photomask to perform an exposure and development process, removing a portion of the photoresist layer to form a patterned photoresist pattern; facilitating the two patterned photoresist patterns As a hard mask, removing the silicon oxynitride layer not covered by the patterned photoresist pattern; and removing the patterned photoresist pattern. 1 3 · The method for fabricating a gate electrode as described in item 10 of the patent application, wherein the silicided metal layer includes osmium hafnium. 14. The method for fabricating a gate electrode as described in claim 10, wherein the etching solution is an APM (ammonium hydrogen peroxide mixture) solution. · 15 · The method for fabricating a gate electrode as described in item 10 of the patent application, wherein the protective layer includes nitride nitride. Page 17