KR950030338A - Capacitor Manufacturing Method of Semiconductor Device - Google Patents

Capacitor Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR950030338A
KR950030338A KR1019940008702A KR19940008702A KR950030338A KR 950030338 A KR950030338 A KR 950030338A KR 1019940008702 A KR1019940008702 A KR 1019940008702A KR 19940008702 A KR19940008702 A KR 19940008702A KR 950030338 A KR950030338 A KR 950030338A
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KR
South Korea
Prior art keywords
forming
film
storage electrode
charge storage
contact hole
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KR1019940008702A
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Korean (ko)
Inventor
김재갑
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김주용
현대전자산업 주식회사
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Priority to KR1019940008702A priority Critical patent/KR950030338A/en
Publication of KR950030338A publication Critical patent/KR950030338A/en

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • H10B12/02Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03Making the capacitor or connections thereto
    • H10B12/033Making the capacitor or connections thereto the capacitor extending over the transistor

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 반도체소자의 캐패시터 관한 것으로서, 필드산화막과 모스트랜지스터 및 비드라인이 형성되어 있는 반도체기판을 평탄화하는 층간절연막상에 식각선택비차가 있는 물질로 식각정벽층을 도포한 후, 소오스전극상의 식각장벽층과 층간절연막을 제거하여 전하보존전극 콘택홀을 형성하고, 상기 전하보존전극 콘택홀의 측벽에 절연스페이서를 형성하는데, 상기 절연스페이서 식각 공정시 식각장벽층을 이용하여 층간절연막 보다 낮게 형성한 후, 상기 전하보존전극 콘택홀을 메우는 제1도전층 패턴 및 상기 제1도전층 패턴과 연결되는 원동 형상의 제2도전층 패턴으로 구성되는 전하보존전극을 형성하였으므로, 전하보존전극 마스크의 정렬 여유도가 증가되어 고집적화에 유리하며, 절연스페이서가 손상되지 않아 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor of a semiconductor device, comprising: applying an etched wall layer with a material having an etching selectivity difference on an interlayer insulating film to planarize a semiconductor substrate on which a field oxide film, a MOS transistor, and a bead line are formed, and then etching the source electrode. After removing the barrier layer and the interlayer insulating layer, a charge storage electrode contact hole is formed, and an insulation spacer is formed on the sidewall of the charge storage electrode contact hole, which is formed lower than the interlayer insulating layer using an etch barrier layer during the etching process of the insulating spacer. And a charge storage electrode including a first conductive layer pattern filling the charge storage electrode contact hole and a second conductive layer pattern having a circular shape connected to the first conductive layer pattern, thus providing an alignment margin of the charge storage electrode mask. Is increased, which is advantageous for high integration, and the insulation spacer is not damaged, thus improving process yield and device operation. It can improve the castle.

Description

반도체소자의 캐패시터 제조방법Capacitor Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도 (A)-(D) 는 본 발명의 다른 실시예에 따른 반도체소자의 캐패시터 제조공정도.3A to 3D are diagrams illustrating a capacitor manufacturing process of a semiconductor device in accordance with another embodiment of the present invention.

Claims (7)

소자분리를 위한 필드산화막과 게이트산화막과 게이트전극 및 게이트전극 양측의 반도체기판에 소오스전극 및 드레인전극이 형성되어 있는 반도체기판의 전표면에 제1절연막을 형성하는 공정과, 상기 제1절연막상에 상기 드레인전극과 연결되는 비트라인을 형성하는 공정과, 상기 구조의 전표면에 제2절연막을 형성하는 공정고, 상기 제2절연막상에 제2절연막과 식각선택비차가 있는 물질로 식각장벽층을 형성하는 공정과, 상기 소오스 전극상의 식각장벽층에서 제1절연막까지 순차적으로 제거하여 상기 소오스전극을 노출시키는 전하보존전극 콘택홀을 형성하는 공정과, 상기 전하보존전극 콘택홀의 측벽에서 상기 제2절연막의 상측 표면 보다 낮은 절연스페이서를 형성하는 공정을 구비하는 반도체소자의 캐패시터 제조방법.Forming a first insulating film on the entire surface of the semiconductor substrate having source and drain electrodes formed on the semiconductor substrates on both sides of the field oxide film, the gate oxide film, the gate electrode and the gate electrode for device isolation; Forming a bit line connected to the drain electrode; forming a second insulating layer on the entire surface of the structure; and forming an etch barrier layer on the second insulating layer with a material having an etching selectivity difference with the second insulating layer. Forming a charge storage electrode contact hole exposing the source electrode by sequentially removing the etching barrier layer from the etch barrier layer on the source electrode to the first insulating layer; and forming a charge storage electrode contact hole on the sidewall of the charge storage electrode contact hole. A method for manufacturing a capacitor of a semiconductor device, comprising the step of forming an insulating spacer lower than an upper surface of the substrate. 제1항에 있어서, 상기 제1절연막을 산화막으로 형성하는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of manufacturing a capacitor of a semiconductor device according to claim 1, wherein said first insulating film is formed of an oxide film. 제1항에 있어서, 상기 제2절연막을 BPSG 단일막이나 USG/BPSG의 적측막으로 형성하는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of manufacturing a capacitor of a semiconductor device according to claim 1, wherein said second insulating film is formed of a BPSG single film or a red film of USG / BPSG. 제1항에 있어서, 상기 식각장벽층을 질화막이나 실리콘막으로 형성하는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 1, wherein the etching barrier layer is formed of a nitride film or a silicon film. 소자분리를 위한 필드산화막과 게이트산하막과 게이트전극 및 게이트전극 양측의 반도체기판에 소오스전극 및 드레인전극이 형성되어 있는 반도체기판상에 상기 소오스전극을 노출시키는 콘택홀이 형성되어 있는 제1절연막 패턴을 형성하는 공정과, 상기 콘택홀을 메우는 도전층 패턴으로된 접촉플러그를 형성하는 공정과, 상기 구조의 전표면에 평탕화를 위한 제2절연막을 형성하는 공정과, 상기 제2절연막상에 제2절연막과 식각선택비차가 있는 물질로 식각장벽층을 형성하는 공정과, 상기 접촉플러그를 노출시키기 위한 전하보존전극 콘택 마스크를 상기 제1절연막 패턴 상부의 식각장벽층상에 형성하는 공정과, 상기 전하보존전극 콘택 마스크에 의해 노출되어 있는 식각장벽층 및 제2절연막을 순차적으로 제거하여 상기 접촉플러그를 노출시키는 전하보존전극콘택홀을 형성하는 공정과, 상기 전하보존전극 콘택홀의 측벽에서 상기 제2절연막의 상측 표면 보다 낮은 절연 스페이서를 형성하는 공정과, 상기 구조의 전표면에 제1도전층을 형성하여 전하보존전극 콘택홀을 메우는 공정과, 상기 전하보존전극 콘택홀 상부의 제1도전층상에 회생막 패턴을 형성하고 회생막 패턴에 의해 노출되어 있는 제1도전층을 제거하여 제1도전층 패턴들을 고립시키는 공정과, 상기 회생막 패턴의 측벽에 원동형상의 제2도전층 패턴을 형성하여 상기 제1도전층 패턴과 연결시키는 공정과, 상기 회생막 패턴을 제거하는 공정을 구비하는 반도체소자의 캐패시터 제조방법.A first insulating film pattern having contact holes for exposing the source electrode on a semiconductor substrate having a source electrode and a drain electrode formed on the semiconductor substrates on both sides of the field oxide layer, the gate underlayer, and the gate electrode for device isolation. Forming a contact plug having a conductive layer pattern filling the contact hole, forming a second insulating film for leveling on the entire surface of the structure, and forming a second insulating film on the second insulating film. (2) forming an etch barrier layer with a material having an etching selectivity difference between the insulating layer, and forming a charge storage electrode contact mask on the etch barrier layer above the first insulating layer pattern to expose the contact plug; The etch barrier layer and the second insulating layer exposed by the storage electrode contact mask are sequentially removed to expose the contact plug. Forming a charge storage electrode contact hole, forming an insulating spacer lower than an upper surface of the second insulating film on the sidewall of the charge storage electrode contact hole, and forming a first conductive layer on the entire surface of the structure Filling the storage electrode contact hole, and forming a regenerative film pattern on the first conductive layer on the charge storage electrode contact hole, and removing the first conductive layer exposed by the regenerative film pattern to isolate the first conductive layer patterns. And forming a circular conductive second conductive layer pattern on the sidewall of the regenerative film pattern, connecting the first conductive layer pattern to the first conductive layer pattern, and removing the regenerative film pattern. Way. 제5항에 있어서, 상기 접촉플러그와 제1 및 제2도전층을 실리콘으로 형성하는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 5, wherein the contact plug and the first and second conductive layers are formed of silicon. 제5항에 있어서, 상기 회생막 패턴을 산화막으로 형성하는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of manufacturing a capacitor of a semiconductor device according to claim 5, wherein the regenerative film pattern is formed of an oxide film. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019940008702A 1994-04-25 1994-04-25 Capacitor Manufacturing Method of Semiconductor Device KR950030338A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100334393B1 (en) * 1999-06-30 2002-05-03 박종섭 Fabricating method for semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100334393B1 (en) * 1999-06-30 2002-05-03 박종섭 Fabricating method for semiconductor device

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