KR980005628A

KR980005628A - Method of forming a contact hole in a semiconductor device

Info

Publication number: KR980005628A
Application number: KR1019960025810A
Authority: KR
Inventors: 심대용
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1996-06-29
Filing date: 1996-06-29
Publication date: 1998-03-30

Abstract

본 발명은 반도체소자의 콘택홀 형성방법에 관한 것으로, 도전층 상부에 제1내부절연막, 제1평탄화층, 제2평탄화층 및 제2내부절연막을 순차적으로 형성하고 상기 제2내부절연막을 콘택홀보다 크게 건식식각한 다음, 상기 제2평탄화층, 제1평탄화층 및 제1내부절연막을 콘택마스크를 이용하여 건식식각함으로써 상기 도전층을 노출시키는 콘택홀을 형성하고 상기 콘택홀을 습식식각처리하여 상기 콘택홀의 측벽을 완만하게 형성하는 공정으로 상기 콘택홀의 단차피복비를 향상시킴으로써 후속공정을 용이하게 하여 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.A method for forming a contact hole in a semiconductor device, the method comprising: forming a first inner insulating film, a first planarizing layer, a second planarizing layer, and a second inner insulating film sequentially on the conductive layer, The second planarizing layer, the first planarizing layer, and the first inner insulating film are dry-etched using a contact mask to form contact holes exposing the conductive layers, and the contact holes are wet-etched A step of gently forming a sidewall of the contact hole improves a step coverage ratio of the contact hole, thereby facilitating a subsequent process, thereby improving the characteristics and reliability of the semiconductor device and enabling high integration of the semiconductor device.

Description

Method of forming a contact hole in a semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2a도는 내지 제2d도는 본 발명의 실시예에 따른 반도체소자의 바아콘택홀 형성방법을 도시한 단면도.FIGS. 2a to 2d are cross-sectional views illustrating a method of forming a bar contact hole in a semiconductor device according to an embodiment of the present invention;

Claims

A step of sequentially forming a first inner insulating film, a first planarization layer, a second planarization layer, and a second inner insulating film on the conductive layer; dry etching the second inner insulating film to a larger extent than the contact hole; Forming a contact hole exposing the conductive layer by dry-etching the planarizing layer, the first planarization layer, and the first inner insulating film using a contact mask; wet etching the contact hole to smooth the side wall of the contact hole And forming a contact hole in the semiconductor device.

The method according to claim 1, wherein the first planarization layer is formed of an organic SOG insulating film.

The method of claim 1 or 2, wherein the second planarization layer is formed of a BPSG insulation film.

The method according to claim 1 or 2, wherein the second planarization layer forms a BPSG insulation film.

※ Note: It is disclosed by the contents of the first application.