KR940010195A - Fine contact formation method for highly integrated devices - Google Patents

Fine contact formation method for highly integrated devices Download PDF

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Publication number
KR940010195A
KR940010195A KR1019920018285A KR920018285A KR940010195A KR 940010195 A KR940010195 A KR 940010195A KR 1019920018285 A KR1019920018285 A KR 1019920018285A KR 920018285 A KR920018285 A KR 920018285A KR 940010195 A KR940010195 A KR 940010195A
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South Korea
Prior art keywords
oxide film
film
etching
forming
highly integrated
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KR1019920018285A
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Korean (ko)
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KR950010852B1 (en
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김정
고요환
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김주용
현대전자산업 주식회사
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Priority to KR1019920018285A priority Critical patent/KR950010852B1/en
Priority to JP5249431A priority patent/JP2577864B2/en
Publication of KR940010195A publication Critical patent/KR940010195A/en
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Publication of KR950010852B1 publication Critical patent/KR950010852B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

본 발명은 DRAM, SRAM, ASIC 등의 고집적 소자의 집적도가 높아질수록 어려움을 겪고 있는 미세 콘택 형성에 관한 것으로, 비등방성 식각에 의해 잔류되는 링 모양의 패드 폴리실리콘막과 콘랙홀 상의 산화막 식각 폭만큼의 공정 여유도를 갖게함으로써 미세 콘택에서 발생되기 쉬운 워드선 및 비트선의 단락을 방지하고 또한 반도체 소자의 공정상의 여유를 확보할 수 있어 고집적 소자의 신뢰도를 증진 시키는 고집적 소자용 미세 콘택 형성방법에 관한 것이다.The present invention relates to the formation of fine contacts, which are becoming more difficult as the degree of integration of highly integrated devices such as DRAM, SRAM, and ASIC increases. The present invention relates to a ring-shaped pad polysilicon film remaining by anisotropic etching and an oxide film etching width on a contact hole. A method of forming a micro contact for a highly integrated device that improves reliability of a highly integrated device by preventing short circuits of word lines and bit lines that are likely to occur in fine contacts and securing a process margin of a semiconductor device by having a process margin of will be.

Description

고집적 소자용 미세 콘택 형성방법Fine contact formation method for highly integrated devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 미세 콘택 형성 방법을 이용한 DRAM 셀제조 공정도.1 is a DRAM cell manufacturing process using the fine contact forming method of the present invention.

Claims (5)

반도체 기판(1)에 소자 분리 절연막(2), 소오스 전극(6a), 드레인 전극(6b), 게이트 산화막(3), 워드선인 게이트 전극(4), 상기 게이트 전극(4)의 스페이서 산화막(5)을 갖는 MOSFET에 고집적 소자용 미세 콘택 형성방법에 있어서, MOSFET상에 제1산화막(7)을 전면에 도포하고 상기 제 1산화막(7)상에 질화막(8)을 적층한 다음에 감광막(9)으로 마스크 패턴하고 질화막(8)과 제1산화막(7)의 일부를 선택 식각하는 제1단계, 상기 제1단계후에 상기 감광막(9)을 제거 하고 폴리 실리콘막(10)을 증착하고 마스크 없이 상기 폴리실리콘막(10)을 비등방성 식각하여 패드 폴리실리콘막(10a)을 형성하는 제2단계, 상기 제2단계 후에 평탄화용 제3산화막(11)을 도포하고 비트선 형성을 위한 감광막(12) 마스크 패턴을 한 다음에 드레인 전극(6b) 상부에 위치한 제2산화막(11), 제1산화막(7)을 차례로 식각하여 비트선 콘택홀(16)을 형성하는 제3단계, 및 상기 제3단계 후에 비트선(13)을 형성하고 제3산화막(14)을 도포하여 전하 저장 콘택홀(17)형성을 위해 감광막(15)으로 마스크 패턴하여 제3산화막(14), 제2산화막(11), 제1산화막(7)을 차례로 식각하여 전하 저장 콘택홀(17)은 형성하는 제4단계로 구비되어지는 것을 특징으로 하는 고집적 소자용 미세 콘택 형성방법.A device isolation insulating film 2, a source electrode 6a, a drain electrode 6b, a gate oxide film 3, a gate electrode 4 as a word line, and a spacer oxide film 5 of the gate electrode 4 are formed on the semiconductor substrate 1. In the method of forming a fine contact for a highly integrated device in a MOSFET having a), the first oxide film 7 is applied to the entire surface of the MOSFET, and the nitride film 8 is laminated on the first oxide film 7, and then the photoresist film 9 Mask pattern and selective etching of the nitride film 8 and a portion of the first oxide film 7, after the first step, the photoresist film 9 is removed and the polysilicon film 10 is deposited without a mask. The second step of anisotropically etching the polysilicon film 10 to form the pad polysilicon film 10a, and after the second step, the third oxide film 11 for planarization is applied and the photoresist film 12 for forming bit lines After the mask pattern is formed, the second oxide film 11 and the first oxide film 7 positioned on the drain electrode 6b are removed. A third step of forming the bit line contact hole 16 by etching, and forming the bit line 13 after the third step and applying a third oxide layer 14 to form the charge storage contact hole 17. The photoresist film 15 is masked and the third oxide film 14, the second oxide film 11, and the first oxide film 7 are sequentially etched to form the charge storage contact hole 17. A fine contact forming method for a highly integrated device, characterized in that. 제1항에 있어서, 상기 제1단계의 감광막(9)마스크 패턴에 의한 식각 부위는 비트선 콘택 부분과 전하 저장전극 콘택 영역인 것을 특징으로 하는 고집적 소자용 미세 콘택 형성방법.The method of claim 1, wherein the etching portion of the photoresist layer (9) mask pattern of the first step is a bit line contact portion and a charge storage electrode contact region. 제1항에 있어서, 상기 제3단계의 잔류된 상기 패드 폴리 실리콘막(10a)은 제2산화막(11)을 식각한 후에 제1산화막(7)을 식각할때에 게이트 전극(4), 즉 워드선과 후에 형성된 비트선과의 단락을 막아 주는 식각 장애물질로 사용되는 것을 특징으로 하는 고집적 소자용 미세 콘택 형성방법.The method according to claim 1, wherein the pad polysilicon film (10a) remaining in the third step is the gate electrode (4), i.e., when etching the first oxide film (7) after etching the second oxide film (11). A method for forming a fine contact for an integrated device, characterized in that it is used as an etch barrier to prevent short circuit between the word line and the bit line formed later. 제1항에 있어서, 상기 제4단계의 감광막(15)마스크 패턴에 의한 식각 부위는 전하 저장 전극 콘택 영역인 것을 특징으로 하는 고집적 소자용 미세 콘택 형성방법.The method of claim 1, wherein the etching portion of the photoresist layer (15) mask pattern of the fourth step is a charge storage electrode contact region. 제1항에 있어서, 상기 제4단계의 제2산화막(11) 식각 후 제1산화막(7)을 식각할때에 게이트 전극(4), 즉 워드선과 후에 형성된 전하 보존 전극과의 단락을 막아 주는 식각 장애 물질은 상기 상기 제3단계의 잔류된 상기 패드 폴리실리콘막(10a)인 것을 특징으로 하는 고집적 소자용 미세 콘택 형성방법.The method of claim 1, wherein the first oxide film 7 is etched after the second oxide film 11 is etched in the fourth step, thereby preventing a short circuit between the gate electrode 4, that is, the word line and the charge storage electrode formed later. An etching barrier material is the pad polysilicon layer (10a) remaining in the third step of the method for forming a fine contact for the integrated device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920018285A 1992-10-06 1992-10-06 Fine contact patterning method of semiconductor device KR950010852B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019920018285A KR950010852B1 (en) 1992-10-06 1992-10-06 Fine contact patterning method of semiconductor device
JP5249431A JP2577864B2 (en) 1992-10-06 1993-10-05 Method for forming fine contact hole in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920018285A KR950010852B1 (en) 1992-10-06 1992-10-06 Fine contact patterning method of semiconductor device

Publications (2)

Publication Number Publication Date
KR940010195A true KR940010195A (en) 1994-05-24
KR950010852B1 KR950010852B1 (en) 1995-09-25

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