KR950014973A - Microcontact Formation Method of Semiconductor Device - Google Patents

Microcontact Formation Method of Semiconductor Device Download PDF

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Publication number
KR950014973A
KR950014973A KR1019930024238A KR930024238A KR950014973A KR 950014973 A KR950014973 A KR 950014973A KR 1019930024238 A KR1019930024238 A KR 1019930024238A KR 930024238 A KR930024238 A KR 930024238A KR 950014973 A KR950014973 A KR 950014973A
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KR
South Korea
Prior art keywords
forming
semiconductor device
planarization layer
mask
photoresist pattern
Prior art date
Application number
KR1019930024238A
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Korean (ko)
Inventor
김정
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019930024238A priority Critical patent/KR950014973A/en
Publication of KR950014973A publication Critical patent/KR950014973A/en

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Abstract

본 발명은 반도체소자의 미세콘택 형성방법에 관한 것으로, 특히 단차를 갖는 소자를 평탄화시켜 주면서 자기정렬적인 방식으로 미세콘택을 형성하는 방법으로 평탄화층 하부에 평탄화층과 차이가 큰 다결정실리콘층을 적층함으로써 평탄화층을 식각한 후에 자기정렬된 콘택트홀을 형성하며 미세콘택을 용이하게하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a micro contact of a semiconductor device, and in particular, a method of forming a micro contact in a self-aligned manner while flattening a device having a step, and stacking a polysilicon layer having a large difference from the planarization layer under the planarization layer The present invention relates to a technology for forming a self-aligned contact hole after etching the planarization layer and facilitating fine contact.

Description

반도체소자의 미세콘택 형성방법Microcontact Formation Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 내지 제2D도는 종래기술에 실시예에 의한 반도체소자의 미세콘택 형성공정을 도시한 단면도,1A to 2D are cross-sectional views showing a microcontact formation process of a semiconductor device according to an embodiment in the prior art;

제2A도 내지 제2F도는 본 발명의 실시예에 의해 반도체소자의 미세콘택 형성공정을 도시한 단면도.2A to 2F are sectional views showing a microcontact forming process of a semiconductor device according to an embodiment of the present invention.

Claims (2)

반도체소자의 미세콘택 형성방법에 있어서, 워드라인 상부 및 측벽에서 절연기능을 하는 워드라인 스페이서 산화막 및 워드라인 마스크 산화막이 구비된 MOSFET를 형성하는 공정과, 상기 상부구조 전체에 제1절연막, 다결정실리콘을 적층한 다음, 평탄화층을 적층하는 공정과, 상기 평탄화층의 상부에 비트라인 콘택 마스크용 감광막패턴을 형성하는 공정과, 상기 감광막패턴을 마스크로 하여 평탄화층과 제1다결정실리콘을 차례대로 이방성식각하여 비트라인 콘택홀을 형성하고, 감광막패턴을 제거하는 공정과, 상부구조 전체에 제2절연막을 증착한 다음, 마스크를 사용하지 않고 제2절연막을 차례대로 이방성 식각하여 비트라인 콘택홀을 형성하는 공정을 포함하는 반도체소자의 미세콘택 형성방법.A method for forming a micro contact of a semiconductor device, the method comprising: forming a MOSFET including a word line spacer oxide film and a word line mask oxide film having insulating functions on upper and sidewalls of a semiconductor device, and a first insulating film and polycrystalline silicon on the entire upper structure. And then forming a planarization layer; forming a bit line contact mask photoresist pattern on the planarization layer; and using the photoresist pattern as a mask, the planarization layer and the first polycrystalline silicon are sequentially anisotropic. Etching to form a bit line contact hole, removing a photoresist pattern, depositing a second insulating film over the entire upper structure, and then anisotropically etching the second insulating film without using a mask to form a bit line contact hole A fine contact forming method of a semiconductor device comprising the step of. 제1항에 있어서, 상기 워드라인 마스크 산화막 대신에 질화막을 사용하는 것을 특징으로하는 반도체소자의 미세패턴 형성방법.2. The method of claim 1, wherein a nitride film is used instead of the word line mask oxide film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930024238A 1993-11-15 1993-11-15 Microcontact Formation Method of Semiconductor Device KR950014973A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930024238A KR950014973A (en) 1993-11-15 1993-11-15 Microcontact Formation Method of Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930024238A KR950014973A (en) 1993-11-15 1993-11-15 Microcontact Formation Method of Semiconductor Device

Publications (1)

Publication Number Publication Date
KR950014973A true KR950014973A (en) 1995-06-16

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930024238A KR950014973A (en) 1993-11-15 1993-11-15 Microcontact Formation Method of Semiconductor Device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970022583A (en) * 1995-10-27 1997-05-30 알베르트 발도르프, 롤프 옴케 Boundless contact etching method and selective anisotropic etching method by sidewall spacer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970022583A (en) * 1995-10-27 1997-05-30 알베르트 발도르프, 롤프 옴케 Boundless contact etching method and selective anisotropic etching method by sidewall spacer

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