KR960043110A - Method of forming device isolation film in semiconductor device - Google Patents

Method of forming device isolation film in semiconductor device Download PDF

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KR960043110A
KR960043110A KR1019950014338A KR19950014338A KR960043110A KR 960043110 A KR960043110 A KR 960043110A KR 1019950014338 A KR1019950014338 A KR 1019950014338A KR 19950014338 A KR19950014338 A KR 19950014338A KR 960043110 A KR960043110 A KR 960043110A
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South Korea
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film
oxide film
forming
etching
high temperature
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KR1019950014338A
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Korean (ko)
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KR0176154B1 (en
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홍수진
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PSL방식에 의한 소자분리막 형성방법에 대해 기재되어 있다. 이는, 반도체 기판 상에 패드 산화막 및 산화 방지막을 적층하는 제1공정, 소자분리막이 형성될 영역의 산화방지막을 식각하여 개구부를 형성하는 제2공정, 개구부에 의해 노출된 패드 산화막을 등방성 식각하여 언더컷을 형성하는 제3공정, 등방성 식각에 의해 노출된 반도체 기판 표면에 버즈비크 제어산화막을 형성하는 제4공정, 제어산화막이 형성되어 있는 결과물 전면에 다결정실리콘막, 질화막 및 고온산화막을 순차적으로 적층하는 제5공정, 고온산화막 및 질화막을 이방성 식각하여 고온산화막 스페이서와 L형 질화막을 형성하는 제6공정, 다결정실리콘막을 이방성식각하여 고온 산화막 스페이서 하부에만 다결정실리콘막을 남김으로써 L형 다결정실리콘막을 형성하는 제7공정, 고온 산화막 스페이서를 제거하는 제8공정, 산화공정을 실시하여 소자분리막을 형성하는 제9공정을 포함하는 것을 특징으로 한다. 따라서, 미세 크기의 소자분리막을 형성할 수 있다.A device isolation film formation method by the PSL method is described. This is a first step of laminating a pad oxide film and an anti-oxidation film on a semiconductor substrate, a second step of forming an opening by etching an anti-oxidation film in a region where the device isolation film is to be formed, and an undercut by isotropically etching the pad oxide film exposed by the opening. A third process of forming a silicon oxide film, a fourth process of forming a Buzzbeek controlled oxide film on the surface of the semiconductor substrate exposed by isotropic etching, and sequentially stacking a polysilicon film, a nitride film, and a high temperature oxide film on the entire surface of the resultant The fifth step, anisotropically etch the high temperature oxide film and the nitride film to form the high temperature oxide film spacer and the L-type nitride film; 7th step, 8th step of removing high temperature oxide film spacer, oxidation step It characterized in that it comprises a ninth step of forming a separator character. Therefore, a device isolation film having a fine size can be formed.

Description

반도체 장치의 소자분리막 형성방법Method of forming device isolation film in semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2A도 내지 제2H도는 본 발명의 제1실시예에 의한 소자분리막 형성방법을 설명하기 위해 도시한 단면도들이다.2A through 2H are cross-sectional views illustrating a method of forming an isolation layer in accordance with a first embodiment of the present invention.

Claims (4)

반도체 기판 상에 패드 산화막 및 산화방지막을 적층하는 제1공정 ; 소자분리막이 형성될 영역의 상기 산화방지막을 식각하여 개구부를 형성하는 제2공정; 상기 개구부에 의해 노출된 패드 산화막을 등방성 식각하여 언더컷을 형성하는 제3공정 ; 상기 등방성 식각에 의해 노출된 반도체 기판 표면에 버즈비크 제어산화막을 형성하는 제4공정; 상기 제어산화막이 형성되어 있는 결과물 전면에 다결정실리콘막, 질화막 및 고온 산화막을 순차적으로 적층하는 제5공정; 상기 고온산화막 및 질화막을 이방성 식각하여 고온산화막 스페이서와 L형 질화막을 형성하는 제6공정; 상기 다결정실리콘막을 이방성식각하여 상기 고온산화막 스페이서 하부에만 다결정실리콘막을 남김으로써 L형 다결정실리콘막을 형성하는 제7공정; 상기 고온산화막 스페이서를 제거하는 제8공정; 산화공정을 실시하여 소자분리막을 형성하는 제9공정을 포함하는 것을 특징으로 하는 반도체 장치의 소자분리막 형성방법.A first step of laminating a pad oxide film and an antioxidant film on a semiconductor substrate; A second step of forming an opening by etching the antioxidant film in a region where the device isolation film is to be formed; A third step of isotropically etching the pad oxide film exposed by the opening to form an undercut; A fourth step of forming a Buzzbeek-controlled oxide film on the surface of the semiconductor substrate exposed by the isotropic etching; A fifth step of sequentially stacking a polysilicon film, a nitride film, and a high temperature oxide film on the entire surface of the resultant on which the control oxide film is formed; Anisotropically etching the high temperature oxide film and the nitride film to form a high temperature oxide film spacer and an L-type nitride film; An seventh step of forming an L-type polysilicon film by anisotropically etching the polysilicon film to leave a polysilicon film only below the high temperature oxide film spacer; An eighth step of removing the high temperature oxide film spacer; And a ninth step of forming an element isolation film by performing an oxidation process. 제1항에 있어서, 상기 제3공정 후, 상기 산화방지막을 식각마스크로 하여 노출된 반도체 기판을 식각함으로써 트렌치를 형성하는 공정을 더 포함하는 것을 특징으로 하는 반도체 장치의 소자분리막 형성방법.The method of claim 1, further comprising forming a trench by etching the exposed semiconductor substrate using the antioxidant film as an etch mask after the third process. 제1항에 있어서, 상기 제7공정 또는 제8공정 후, 노출된 반도체 기판을 식각함으로써 트렌치를 형성하는 공정을 더 포함하는 것을 특징으로 하는 반도체 장치의 소자분리막 형성방법.The device isolation film forming method of claim 1, further comprising forming a trench by etching the exposed semiconductor substrate after the seventh or eighth process. 제2항 또는 제3항에 있어서, 트렌치 형성을 위한 상기 식각 공정은 이방성 식각 또는 등방성 건식식각으로 진행되는 것을 특징으로 하는 반도체 장치의 소자분리막 형성방법.The method of claim 2, wherein the etching process for forming the trench is performed by anisotropic etching or isotropic dry etching. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950014338A 1995-05-31 1995-05-31 Isolation method of semiconductor device KR0176154B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100464939B1 (en) * 1997-06-26 2005-05-17 주식회사 하이닉스반도체 Method of forming device isolation film in semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100361763B1 (en) * 1995-12-22 2003-02-11 주식회사 하이닉스반도체 Method for manufacturing isolation layer of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100464939B1 (en) * 1997-06-26 2005-05-17 주식회사 하이닉스반도체 Method of forming device isolation film in semiconductor device

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