KR960015854A - Device Separation Method of Semiconductor Devices - Google Patents

Device Separation Method of Semiconductor Devices Download PDF

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Publication number
KR960015854A
KR960015854A KR1019940027917A KR19940027917A KR960015854A KR 960015854 A KR960015854 A KR 960015854A KR 1019940027917 A KR1019940027917 A KR 1019940027917A KR 19940027917 A KR19940027917 A KR 19940027917A KR 960015854 A KR960015854 A KR 960015854A
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KR
South Korea
Prior art keywords
forming
nitride film
semiconductor substrate
oxide film
trench
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KR1019940027917A
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Korean (ko)
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KR0166489B1 (en
Inventor
고요환
박찬광
노광명
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김주용
현대전자산업 주식회사
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Priority to KR1019940027917A priority Critical patent/KR0166489B1/en
Publication of KR960015854A publication Critical patent/KR960015854A/en
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Publication of KR0166489B1 publication Critical patent/KR0166489B1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H01L21/7621Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 반도체소자의 소자분리 방법에 관한 것으로서, 반도체기판에서 소자분리 영역으로 예정되어 있는 부분을 노출시키는 질화막 패턴을 형성하고 상기 질화막 패턴의 측벽에 질화막으로된 스페이서를 형성하며, 그에 의해 노출되는 반도체기판의 소정두께를 등방성 식각하여 언더컷이진 트랜치를 형성하어 부피팽창에 따른 스트레스를 감소시키며, 상기 트랜치의 측벽 부분에 질화막 패턴을 형성하여 산화막과 반도체기판의 경계 부분에 산소가 침투하는 것을 방지한 후, 열산화를 실시하여 소자분리 산화막을 형성함으로써, 반도체기판의 스트레스가 감소되어 격자결함에 따른 누실전류 증가를 방지하여 소자동작의 신뢰성을 향상시킬 수 있으며, 버즈빅의 크기가 감소되어 고자의 고집적화에 유리하고 공정수율을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a semiconductor device, comprising forming a nitride film pattern exposing a portion intended for a device isolation region on a semiconductor substrate, and forming a spacer of a nitride film on a sidewall of the nitride film pattern. Isotropic etching of a predetermined thickness of the semiconductor substrate forms an undercut trench to reduce stress due to volume expansion, and a nitride film pattern is formed on the sidewalls of the trench to prevent oxygen from penetrating the boundary between the oxide film and the semiconductor substrate. After the thermal oxidation is performed to form a device isolation oxide film, the stress of the semiconductor substrate is reduced to prevent leakage current increase due to lattice defects, thereby improving the reliability of the device operation. It is advantageous for high integration and improves process yield.

Description

반도체소자의 소자분리 방법Device Separation Method of Semiconductor Devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1A도 내지 제1E도는 본 발명의 일실시예에 따른 반도체소자의 소자분리 공정도,1A through 1E are device isolation process diagrams of a semiconductor device according to an embodiment of the present invention;

제2A도 내지 제2C도는 본 발명의 다른 실시예에 따른 반도체소자의 소자분리 공정도.2A to 2C are device isolation process diagrams of a semiconductor device according to another embodiment of the present invention.

Claims (4)

반도체기판상에 산화막을 형성하는 공정과, 상기 산화막상에 제1질화막을 형성하는 공정과, 상기 반도체기판에서 소자분리 영역으로 예정되어 있는 부분상의 제1질화막을 제거하여 산화막을 노출시키는 제1질화막패턴을 형성하는 공정과, 상기 제1질화막 패턴의 측벽에 질화막으로된 스페이서를 형성하는 공정과, 상기 스페이서에 의해 노출되어 있는 산화막을 제거하여 반도체기판을 노출시키는 공정과, 상기 노출되어 있는 반도체기판을 예정된 깊이로 제거하여 상기 산화막 페턴의 하부에 언더컷이 진 트랜치를 형성하는 공정과, 상기 트랜치에서 내부의 언더컷이 진 부분과 트랜치의 측벽에 제2질화막 패턴을 형성하는 공정과, 상기 제1 및 제2질화막패턴에 의해 노출되어 있는 트랜치 내부의 반도체기판을 열산화시켜 소자분리 산화막을 형성하는 공정을 구비하는 반도체소자의 소자분리 방법.A process of forming an oxide film on the semiconductor substrate, a process of forming a first nitride film on the oxide film, and a first nitride film exposing the oxide film by removing the first nitride film on a portion of the semiconductor substrate, which is intended to be an element isolation region. Forming a pattern, forming a spacer of a nitride film on a sidewall of the first nitride film pattern, removing an oxide film exposed by the spacer to expose a semiconductor substrate, and exposing the exposed semiconductor substrate. Removing the trench to a predetermined depth to form an undercut trench in the lower portion of the oxide pattern, forming a second nitride film pattern in the undercut portion and sidewalls of the trench in the trench; Forming a device isolation oxide film by thermally oxidizing the semiconductor substrate inside the trench exposed by the second nitride film pattern. A device isolation method for a semiconductor device comprising a step. 제1항에 있어서, 상기 스페이서를 질화막의 전면 도포 및 전면 이방성 식각방법으로 형성하는 것을 특징으로 하는 반도체소자의 소자분리 방법.The method of claim 1, wherein the spacers are formed by coating the entire surface of the nitride layer and etching the entire surface. 제1항에 있어서, 상기 트랜치 형성공정을 등방성 식각방법으로 형성하는 것을 특징으로 하는 반도체소자의 소자분리 방법.The method of claim 1, wherein the trench forming process is formed by an isotropic etching method. 반도체기판상에 산화막을 형성하는 공정과, 상기 산화막상에 제1질화막을 형성하는 공정과, 상기 반도체기판에서 소자분리 영역으로 예정되어 있는 부분상의 제1질화막과 산화막을 제거하여 반도체기판을 노출시키는 제1질화막 패턴과 산화막 패턴을 형성하는 공정과, 상기 제1질화막 패턴과 산화막 패턴이 측벽에 질화막으로된 스페이서를 형성하는 공정과, 상기 스페이서에 의해 노출되어 있는 반도체기관을 예정된 깊이로 제거하여 상기 산화막 패턴의 하부에 언더컷이 진 트랜치를 형성하는 공정과, 상기 질화막 스페이서에 의해 노출되어 있는 반도체기판을 열산화시켜 소자분리 산화막을 형성하는 공정을 구비하는 반도체소자의 소자분리 방법.Forming an oxide film on the semiconductor substrate, forming a first nitride film on the oxide film, and removing the first nitride film and the oxide film on a portion of the semiconductor substrate, which are intended as an isolation region, to expose the semiconductor substrate. Forming a first nitride film pattern and an oxide film pattern, forming a spacer including a nitride film on the sidewalls of the first nitride film pattern and an oxide film pattern, and removing the semiconductor engine exposed by the spacer to a predetermined depth. Forming a trench with an undercut under the oxide film pattern; and forming a device isolation oxide film by thermally oxidizing a semiconductor substrate exposed by the nitride film spacer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940027917A 1994-10-28 1994-10-28 Method of element isolation on a semiconductor device KR0166489B1 (en)

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Application Number Priority Date Filing Date Title
KR1019940027917A KR0166489B1 (en) 1994-10-28 1994-10-28 Method of element isolation on a semiconductor device

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Application Number Priority Date Filing Date Title
KR1019940027917A KR0166489B1 (en) 1994-10-28 1994-10-28 Method of element isolation on a semiconductor device

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Publication Number Publication Date
KR960015854A true KR960015854A (en) 1996-05-22
KR0166489B1 KR0166489B1 (en) 1999-02-01

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