KR930017137A - Device Separation Method of Semiconductor Device - Google Patents

Device Separation Method of Semiconductor Device Download PDF

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Publication number
KR930017137A
KR930017137A KR1019920000157A KR920000157A KR930017137A KR 930017137 A KR930017137 A KR 930017137A KR 1019920000157 A KR1019920000157 A KR 1019920000157A KR 920000157 A KR920000157 A KR 920000157A KR 930017137 A KR930017137 A KR 930017137A
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South Korea
Prior art keywords
insulating film
undercut
forming
film
polysilicon
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KR1019920000157A
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Korean (ko)
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KR950001301B1 (en
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김병렬
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김광호
삼성전자 주식회사
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Priority to KR1019920000157A priority Critical patent/KR950001301B1/en
Publication of KR930017137A publication Critical patent/KR930017137A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

반도체 기판상에 옥시나이트라이드막 및 질화막을 순차적으로 형성하는 단계, 질화막을 기판까지 또는 기판의 일부까지 식각한 후 옥시나이트라이드막의 언더 컷을 형성하는 단계 및 고온 습식산화법에 의하여 필드 산화막을 형성하는 단계로 이루어지는 반도체 장치의 소자분리방법에 관한 것. 옥시나이트라이드막의 언더 컷에 의하여 필드 산화막의 형상각도는 90°이상이 되어 게이트 산화막의 신뢰성을 향상시킬 수 있다는 장점이 있다.Sequentially forming an oxynitride film and a nitride film on the semiconductor substrate, etching the nitride film to a substrate or a part of the substrate, and then forming an undercut of the oxynitride film, and forming a field oxide film by a high temperature wet oxidation method. An element isolation method of a semiconductor device comprising a step. By the undercut of the oxynitride film, the shape angle of the field oxide film is 90 ° or more, which has the advantage of improving the reliability of the gate oxide film.

Description

반도체 장치의 소자분리방법Device Separation Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 2도 (가) 내지 (다)는 본 발명에 의한 소자분리방법을 나타내는 공정순서도, 제 3도 (가) 내지 (라)는 본 발명에 따른 소자분리방법의 일실시예를 나타내는 공정순서도이다.2 (a) to (c) is a process flow chart showing a device separation method according to the present invention, Figure 3 (a) to (d) is a process flow chart showing an embodiment of the device separation method according to the present invention. .

Claims (11)

반도체 기판상에 제1 절연막 및 제2 절연막을 순차적으로 형성하는 단계, 사진식각법으로 상기 제2 절연막의 소정부분을 표면으로부터 적어도 상기 제1 절연막까지 식각하여 개구부를 형성한 후 상기 제1 절연막의 언더 컷을 행사는 단계: 및 열산화법으로 필드 산화막을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 장치의 소자분리방법.Sequentially forming a first insulating film and a second insulating film on a semiconductor substrate, and etching a predetermined portion of the second insulating film from a surface to at least the first insulating film by a photolithography method to form an opening, and then Exerting an undercut; and forming a field oxide film by a thermal oxidation method. 제 1항에 있어서, 상기 제 1절연막이 옥시나이트라이박인 것을 특징으로 하는 반도체 장치의 소자분리방법.2. The method of claim 1 wherein the first insulating film is an oxynitride foil. 제 1항에 있어서, 상기 제2 절연막이 질화막인 것을 특징으로 하는 반도체장치의 소자분리방법.The method of claim 1, wherein the second insulating film is a nitride film. 제 1항에 있어서, 상기 개구부 형성시 상기 반도체 기판의 일부까지 식각하는 것을 특징으로 하는 반도체 장치의 소자분리방법.The method of claim 1, wherein a portion of the semiconductor substrate is etched when the opening is formed. 제 4항에 있어서, 상기 반도체 기판의 식각깊이가 0.05~0.2㎛의 범위로 이루어지는 것을 특징으로 하는 반도체 장치의 소자분리방법.The device isolation method of claim 4, wherein an etching depth of the semiconductor substrate is in a range of 0.05 μm to 0.2 μm. 제 1항에 있어서, 상기 제 1 절연막의 언더 컷이 습식식각하여 형성되는 것을 특징으로 하는 반도체장치의 소자분리방법.2. The method of claim 1, wherein the undercut of the first insulating film is formed by wet etching. 제1항 또는 제 6항에 있어서, 상기 제1절연막의 언더 컷이 0.1~0.2㎛의 깊이로 이루어지는 것을 특징으로 하는 반도체 장치의 소자분리방법.7. The device isolation method according to claim 1 or 6, wherein the undercut of the first insulating film has a depth of 0.1 to 0.2 mu m. 제 1항에 있어서, 상기 제 1절연막의 언더컷을 행한 후 폴리실리콘을 기판 전표면상에 형성한 다음 상기 개구부 측벽에 상기 폴리실리콘의 스페이서를 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체장치의 소자분리방법.The device of claim 1, further comprising forming polysilicon on the entire surface of the substrate after the undercut of the first insulating layer, and then forming a spacer of the polysilicon on the sidewall of the opening. Separation Method. 제 8항에 있어서, 상기 폴리실리콘의 스페이서가 비등방성식각법으로 형성되는 것을 특징으로 하는 반도체장치의 소자분리방법.9. The method of claim 8, wherein the spacer of polysilicon is formed by anisotropic etching. 제 8항에 있어서, 상기 폴리실리콘의 스페이서는 버즈비크의 성장을 억제하기 위하여 형성되는 것을 특징으로 하는 반도체 장치의 소자분리방법.9. The method of claim 8, wherein the spacer of polysilicon is formed to suppress the growth of the Burj beak. 제 1항에 있어서, 상기 제1절연막 및 제 2절연막의 두께가 각각 100~500Å, 1000~2000Å의 범위로 형성되는 것을 특징으로 하는 반도체장치의 소자분리방법.2. The method of claim 1, wherein the thicknesses of the first insulating film and the second insulating film are in a range of 100 to 500 mW and 1000 to 2000 mW, respectively. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920000157A 1992-01-08 1992-01-08 Semiconductor device isolation method KR950001301B1 (en)

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KR1019920000157A KR950001301B1 (en) 1992-01-08 1992-01-08 Semiconductor device isolation method

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KR1019920000157A KR950001301B1 (en) 1992-01-08 1992-01-08 Semiconductor device isolation method

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KR930017137A true KR930017137A (en) 1993-08-30
KR950001301B1 KR950001301B1 (en) 1995-02-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100446285B1 (en) * 1997-10-22 2004-11-16 삼성전자주식회사 Method for forming trench isolation region having round-shaped profile formed at upper corner of trench

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100446285B1 (en) * 1997-10-22 2004-11-16 삼성전자주식회사 Method for forming trench isolation region having round-shaped profile formed at upper corner of trench

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Publication number Publication date
KR950001301B1 (en) 1995-02-15

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