KR100446285B1 - Method for forming trench isolation region having round-shaped profile formed at upper corner of trench - Google Patents

Abstract

PURPOSE: A method for forming a trench isolation region is provided to prevent thinning effect of a gate oxide and concentration of electric field to an upper corner of a trench by forming the upper corner of the trench with a round shape. CONSTITUTION: A pad oxide layer pattern(30'), a nitride layer pattern(50'), and an oxide layer pattern are stacked on a semiconductor substrate(10). A trench is formed on the semiconductor substrate. A part of the pad oxide layer pattern and the oxide layer pattern are selectively etched to form a recess on the pad oxide layer pattern and remove the oxide layer pattern. A sidewall oxide layer is formed on the inside of the trench. The trench is buried and an insulating layer is formed on the semiconductor substrate.

Description

Method for forming trench isolation region with rounded top corner

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method of forming a trench isolation region capable of obtaining a rounded profile at an upper corner of a trench.

In general, LOCOS, which is widely used in the manufacture of semiconductor devices, is used to separate devices by oxidizing the surface of a semiconductor substrate between active regions, and is highly integrated with 256M dynamic random access memory (DRAM). In the semiconductor device, a punch-through current flows as the width of device isolation decreases.

In order to solve the problem of the punch-through current of the LOCOS method, a device isolation method using a trench has been proposed. The trench isolation method separates devices by forming trenches between active regions and filling trenches with insulating material.Effective isolation depth can be obtained even at the same device isolation width. have. In particular, STI (Shallow Trench Isolation) technology is becoming more important as it is combined with chemical mechanical polishing (CMP) technology.

A typical trench device isolation method is as follows. First, a pad oxide film, a silicon nitride film, and a high temperature oxide film (HTO) having a predetermined thickness are deposited on the semiconductor substrate, and then patterned to form a mask pattern. Then, the trench is formed in the semiconductor substrate using the pattern as a mask. Form. After the trench is etched, the inside of the trench is oxidized and the inside of the trench is filled with an insulating material, followed by chemical mechanical polishing (CMP) to expose the nitride film pattern. Subsequently, the device isolation film is completed by removing the nitride film pattern and the pad oxide film.

Hereinafter, with reference to the drawings, the problem of the above-described conventional method will be described. 1 is a cross-sectional view showing a step in which an oxide film is formed inside a trench by the conventional method. Referring to FIG. 1, a mask pattern including a pad oxide film pattern 3, a nitride film pattern 5, and a high temperature oxide film pattern 7 is formed on a semiconductor substrate 1, and a thin oxide film is formed inside the trench t. (9) is formed.

As can be seen from FIG. 1, the oxide film 9 is not easily formed in the upper corner u of the trench t, which is the boundary between the active area and the inactive area of the device, so that the oxide film is formed thinner. As a result, the trench upper corner u after the subsequent CMP process and the residual mask pattern 3 and 5 removal process has a sharp profile.

2 is a cross-sectional SEM photograph after the oxide film is formed inside the trench by the conventional method, and it can be seen that the upper corner of the trench has a sharp profile.

In this state, when the oxidation process for forming the gate oxide film is formed in the active region, gate oxide thinning occurs at the upper corner u of the trench, and an abnormal hump in the current-voltage (IV) curve is observed. A hump may occur or leakage current in an OFF state may increase, and a reverse narrow channel effect or a deterioration of a gate oxide layer may occur. Specifically, when the gate voltage is applied, the electric field is concentrated in the channel region adjacent to the u point, and thus is easily inverted even at a low gate voltage to increase the current flowing between the source and the drain. Therefore, an effect of lowering the threshold voltage of the transistor, that is, an inverse narrow channel effect occurs, thereby degrading device characteristics.

On the other hand, according to the conventional trench device isolation method, since the oxide film pattern 7 used as the etching mask remains on the nitride film pattern 5 after the trench is etched, the thickness of the oxide film pattern 7 is very unevenly in the wafer. In addition, the variation is severe for each wafer. Therefore, when the gap of the trench is filled in the subsequent process and the CMP process is performed, if the thickness of the pattern 7 is non-uniform, the height of the field oxide film cannot be adjusted after the CMP process, and in this case, there is a problem in that the electrical characteristics of the device are varied. have.

An object of the present invention is to provide a method for forming a trench isolation region in which an upper portion of a sidewall of the sidewall has a round shape.

1 is a cross-sectional view illustrating a problem of trench isolation according to the prior art.

2 is a cross-sectional SEM photograph when an oxide film is formed inside a trench by the prior art.

3 to 10 are cross-sectional views sequentially illustrating a method of forming a trench isolation region according to a first embodiment of the present invention.

11 to 15 are cross-sectional views sequentially illustrating a method of forming a trench isolation region according to a second embodiment of the present invention.

Fig. 16 is a cross-sectional SEM photograph when the pad oxide film pattern on the semiconductor substrate is recessed according to the present invention.

17 is a cross-sectional SEM photograph in the case where an oxide film is formed in the trench according to the present invention.

In order to achieve the above object, in the present invention, a trench is formed in a semiconductor substrate in which a pad oxide film pattern, a nitride film pattern, and an oxide film pattern are sequentially stacked, and then a predetermined portion of the pad oxide film pattern and the oxide film pattern are selectively etched to form a pad oxide film. A recess is formed in the pattern and the oxide film pattern is removed. A sidewall oxide film is formed in the trench. At this time, since the sidewall oxide film is formed inside the recess, the upper corner of the trench is rounded. Subsequently, the trench is filled with an insulating layer having a predetermined thickness on the substrate.

In the present invention, the step of selectively etching the pad oxide film and the oxide pattern, wet etching using an etchant that selectively etches only oxide, it is preferable to perform so that the pad oxide film pattern is recessed (50 to 300Å). Do.

In an embodiment of the present invention, a photoresist pattern is used as a trench etching mask instead of the oxide layer pattern. As such, even if there is no oxide layer on the nitride layer pattern, the pad oxide layer may be recessed after the trench etching to obtain a round profile of the upper corner of the trench.

According to the method of forming a trench device isolation region according to the present invention, by forming a recess in a pad oxide layer pattern, an oxide layer may be formed to a uniform thickness up to an upper corner when an oxide layer is formed in the trench. A round profile can be obtained at the top of the trench sidewalls. In addition, in the recess process of the pad oxide film pattern, the oxide film pattern remaining on the nitride film pattern is also removed to uniformize the height of the field oxide film in a subsequent process because the surface is uniform.

Hereinafter, a method of forming an isolation region according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

Example 1

3 to 10 are cross-sectional views illustrating a method of forming a trench device isolation region in a semiconductor device according to a first embodiment of the present invention.

Referring to FIG. 3, a pad oxide film 30 is first grown on a semiconductor substrate 10, and a silicon nitride film 50 is deposited thereon. Subsequently, an oxide film 70, for example, a high temperature oxide film HTO, is formed on the nitride film 50 to form a trench etching mask. A photoresist is applied on the oxide film 70 and then exposed and developed to form a photoresist pattern (not shown) on the semiconductor substrate 10.

The pad oxide layer 30 is formed to have a thickness of 50 to 300 Å, which serves as a buffer against stress that the semiconductor substrate 10 receives when the nitride layer 50 is deposited.

The nitride film 50 is formed to have a thickness of 1000 to 2000 microns, which is formed in a subsequent process, and after the insulating material is deposited on the entire surface of the semiconductor substrate to fill the insulating material in the trench, a chemical mechanical polishing (CMP) process is performed. It is intended to serve as an abrasive barrier layer when advancing.

The oxide layer 70 serves as a mask when etching the semiconductor substrate to form a trench, and the method of oxidizing the inside of the silicon nitride layer pattern with an oxidizing gas such as oxygen or water vapor at a high temperature, or There is a method of oxidizing the inside of the silicon nitride film pattern using plasma. In this case, the oxide film formed using the plasma has an advantage that the wet etch rate is superior to that of the high temperature oxide film and thus is completely removed during the partial etching process of the pad oxide film in a subsequent process.

Referring to FIG. 4, the oxide film 70, the nitride film 50, and the pad oxide film 30 are sequentially etched using the photoresist pattern (not shown) as an etch mask, so as to be used as a mask. After the nitride film pattern 50 'and the oxide film pattern 70' are formed, the photoresist pattern is removed.

Referring to FIG. 5, a trench t is formed by dry etching the semiconductor substrate 10 using the oxide layer pattern 70 ′, the nitride layer pattern 50 ′, and the pad oxide layer pattern 30 ′ as a mask. . The dry etching process uses a mixed gas of Cl ₂ and HBr.

Referring to FIG. 6, a portion of the pad oxide layer pattern 30 ′ of the trench upper corner u is selectively etched to recess the pad oxide layer pattern 30 ′ with respect to the nitride layer pattern 50 ′. )

As an etchant capable of selectively etching only the oxide film, a mixture solution of NH ₄ OH and HF or an HF solution may be used, and the mixing ratio may be adjusted according to the etching rate.

In addition, in the process of wet etching a predetermined amount of the pad oxide layer pattern 30 ′ with the etchant, the oxide layer pattern 70 ′ remaining on the nitride layer pattern 50 ′ is removed together, and thus the thickness of the field oxide layer is uniform. Done.

The oxide film pattern 70 'may be formed using a plasma chemical vapor deposition method. The plasma oxide film has a higher wet etching rate than the high temperature oxide film, and is thus completely removed during the etching process. As a result, the uniformity of the oxide film before the chemical mechanical polishing process can be obtained at the same level as that of the material filling the gap of the trench.

Referring to FIG. 7, the sidewall oxide film 90 is thinly formed in the trench t. This is to heal the damaged portion during the etching process for forming the trench region t. For example, the sidewall oxide layer 90 is formed in the trench by thermal oxidation. In this case, since the recess is formed in the pad oxide layer pattern 30 ′, the oxide layer may be formed even on the semiconductor substrate exposed by the recess. As a result, the thickness of the sidewall oxide layer 90 inside the trench may be formed in the upper corner of the trench. up to u), a round profile is formed at the top corner of the trench.

Referring to FIG. 8, the oxide film 110 is formed to fill the trench t by a chemical vapor deposition method and to have a predetermined thickness on the nitride film pattern 50 ′.

Referring to FIG. 9, planarization is performed using a chemical mechanical polishing (CMP) process until the nitride film pattern 50 ′ is exposed.

Referring to FIG. 10, the nitride film pattern 50 ′ is removed by wet etching using an etchant such as phosphoric acid, a sacrificial oxide film (not shown) is formed through a sacrificial oxidation process, and a buffer oxide film. The device isolation layer 110 ′ is obtained by removing the pad oxide layer pattern 30 ′ using an oxide film etchant such as an etched solution (BOE) or hydrofluoric acid (HF).

In the semiconductor device manufactured by the trench isolation method of the present invention as described above, the upper corner u of the trench t, which is a boundary between the active region and the inactive region, has a round shape.

FIG. 16 is a cross-sectional SEM photograph when the trench is formed in accordance with the method of the present invention as shown in FIG. 6 and then the pad oxide layer pattern is recessed with NH ₄ OH solution or HF solution for 1 minute. From this, it can be seen that the pad oxide film pattern in the upper portion of the trench is recessed by about 150 Å.

FIG. 17 is a SEM photograph after the sidewall oxide film is formed in the trench of the wafer where the pad oxide pattern is recessed according to the method of the present invention as shown in FIG. 7. It can be seen that the upper corner of the trench is formed in a round shape.

Example 2

The second embodiment differs from the first embodiment in that a photoresist film is applied instead of an oxide film after nitride film deposition.

11 to 15 are cross-sectional views illustrating a method of forming a trench isolation region in a semiconductor device according to a second embodiment of the present invention.

Referring to FIG. 11, a pad oxide film 300 is first grown on a semiconductor substrate 100, and a nitride film 500 is deposited thereon. Next, the photoresist 1300 is coated on the nitride film 500.

The pad oxide layer 300 is formed to have a thickness of 50 to 300 占 이는, which serves as a buffer against stress that the semiconductor substrate 100 receives when the nitride layer 500 is deposited.

The nitride film 500 is formed to have a thickness of 1000 to 2000 microns, which is formed in a subsequent process, and after the insulating material is deposited on the entire surface of the semiconductor substrate to fill the trench with a trench, a chemical mechanical polishing (CMP) process is performed. It is intended to serve as an abrasive barrier layer when advancing.

The photoresist 1300 is formed to a thickness of 5000 to 15000 Å, which serves as a mask when forming a pattern of the nitride film 500 and the pad oxide film 300 and when etching a semiconductor substrate to form a trench.

Referring to FIG. 12, the photoresist is exposed and developed to form a photoresist pattern 1300 ′, and the pad oxide film 300 and the nitride film 500 are etched to expose the semiconductor substrate 100 using the photoresist pattern as a mask pattern. The pad oxide film pattern 300 'and the nitride film pattern 500' are thus formed.

Referring to FIG. 13, a trench t is formed by dry etching a semiconductor substrate using the photoresist pattern 1300 ′ as an etching mask. The dry etching process may use a mixed gas of Cl ₂ and HBr.

Referring to FIG. 14, the photoresist pattern 1300 ′ is removed. The photoresist pattern 1300 ′ may be removed after the recess forming step, or may be removed after the CMP process.

Referring to FIG. 15, a portion of the pad oxide layer pattern 300 ′ of the upper portion of the trench t may be selectively etched to recess the pad oxide layer pattern 300 ′ with respect to the nitride layer pattern 500 ′. recess).

An etchant capable of selectively etching only the pad oxide layer may be a mixed solution of NH ₄ OH and HF or an HF solution.

Subsequently, the same process as in Example 1 was carried out to obtain a device isolation film as shown in FIG.

As described above, according to the exemplary embodiments of the present invention, after the trench is etched, a recess is formed in the pad oxide layer pattern, and then an oxide layer is formed in the trench to round the upper corner of the trench. As a result, the gate oxide thinning and the concentration of the electric field in the upper corners of the trench do not appear.

In addition, in the process of forming a recess in the pad oxide layer pattern after etching the trench, the trench etch mask pattern remaining on the upper portion of the nitride layer may be completely removed to uniformize the height of the field oxide layer in a subsequent process.

In the above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention. Do.

Claims (16)

Forming a trench in a semiconductor substrate in which a pad oxide film pattern, a nitride film pattern, and an oxide film pattern are sequentially stacked; Selectively etching a predetermined portion of the pad oxide layer pattern and the oxide layer pattern to form a recess in the pad oxide layer pattern and to remove the oxide layer pattern; Forming a sidewall oxide film in the trench; And And filling the trench and forming an insulating layer having a predetermined thickness on the semiconductor substrate. The method of claim 1, wherein the forming of the trench comprises: Stacking a pad oxide film, a nitride film, and an oxide film on the semiconductor substrate in sequence, and then patterning the same to expose a predetermined region of the semiconductor substrate; And And etching the exposed semiconductor substrate to a predetermined depth. The method of claim 2, wherein the oxide layer comprises a high temperature oxide layer (HTO). The method of claim 2, wherein the oxide film is a plasma oxide film. The method of claim 1, wherein the selective etching is wet etching using a mixed solution of NH ₄ OH and HF or an HF solution as an etchant. The method of claim 1, wherein the selective etching is performed to etch the pad oxide layer pattern 50 to 300 산화. The method of claim 1, wherein the sidewall oxide layer has a constant thickness. The method of claim 1, wherein the sidewall oxide layer is formed by thermal oxidation. Forming a trench in a semiconductor substrate in which a pad oxide film pattern, a nitride film pattern, and a photoresist pattern are sequentially stacked; Forming a recess in the pad oxide layer pattern; Forming a sidewall oxide film in the trench; And And filling the trench and forming an insulating layer having a predetermined thickness on the substrate. The method of claim 9, wherein the forming of the trench comprises: Stacking a pad oxide film, a nitride film, and a photoresist film on the semiconductor substrate in sequence, and then patterning the same to expose a predetermined region of the semiconductor substrate; And And etching the exposed semiconductor substrate by dry etching. The method of claim 9, wherein the recess is formed by wet etching using a mixed solution of NH ₄ OH and HF or an HF solution as an etchant. 10. The method of claim 9, wherein the length of the recess is 50 to 300 micrometers. 10. The method of claim 9, further comprising removing the photoresist pattern after forming the trench. 10. The method of claim 9, further comprising removing the photoresist pattern after forming the recess. The method of claim 9, wherein the sidewall oxide layer has a constant thickness. 10. The method of claim 9, wherein the sidewall oxide film is formed by thermal oxidation.

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