KR970003823A - Device Separating Method of Semiconductor Device - Google Patents

Device Separating Method of Semiconductor Device Download PDF

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Publication number
KR970003823A
KR970003823A KR1019950019155A KR19950019155A KR970003823A KR 970003823 A KR970003823 A KR 970003823A KR 1019950019155 A KR1019950019155 A KR 1019950019155A KR 19950019155 A KR19950019155 A KR 19950019155A KR 970003823 A KR970003823 A KR 970003823A
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KR
South Korea
Prior art keywords
oxide film
film
forming
field oxide
anisotropic etching
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KR1019950019155A
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Korean (ko)
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KR0167675B1 (en
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장희현
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김주용
현대전자산업 주식회사
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Priority to KR1019950019155A priority Critical patent/KR0167675B1/en
Publication of KR970003823A publication Critical patent/KR970003823A/en
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Publication of KR0167675B1 publication Critical patent/KR0167675B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

본 발명은 소자분리막의 기판 상부로의 돌출을 방지하여 평탄도를 증대시키는 반도체 소자의 소자분리막 형성방법에 관한것으로, 반도체 소자 제조공정중 활성영역간의 전기적 격리를 위한 소자분리막 형성방법에 있어서, 실리콘기판에 완충산화막, 질화막을 형성한 후 필드산화막이 형성될 영역의 상기 질화막을 제거하는 제1단계; 열산화 공정을 통해 제1필드산화막을 형성하는 제2단계; 상기 제1필드산화막을 제거한 후 제2필드산화막을 형성하는 제3단계; 및 상기 질화막, 완충산화막을 제거하는 제4단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention relates to a method for forming a device isolation film of a semiconductor device to increase the flatness by preventing the device isolation film from protruding to the upper portion of the substrate, in the method of forming a device isolation film for electrical isolation between active regions during the semiconductor device manufacturing process Forming a buffer oxide film and a nitride film on a substrate, and then removing the nitride film in a region where a field oxide film is to be formed; A second step of forming a first field oxide film through a thermal oxidation process; A third step of forming a second field oxide film after removing the first field oxide film; And a fourth step of removing the nitride film and the buffer oxide film.

Description

반도체 소자의 소자분리막 형성방법Device Separating Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2D도는 본 발명의 일실시예에 따른 필드산화막 형성과정을 나타내는 단면도.2A through 2D are cross-sectional views illustrating a process of forming a field oxide film according to an embodiment of the present invention.

Claims (6)

반도체 소자 제조공정중 활성영역간의 전기적 격리를 위한 소자분리막 형성방법에 있어서, 실리콘기판에완충산화막, 질화막을 형성한 후 필드산화막이 형성될 영역의 상기 질화막을 제거하는 제1단계; 열산화공정을 통해 제1필드산화막을 형성하는 제2단계; 상기 제1필드산화막을 제거한 후 제2필드산화막을 형성하는 제3단계; 및 상기 질화막, 완충산화막을 제거하는 제4단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.A method of forming a device isolation film for electrical isolation between active regions in a semiconductor device manufacturing process, comprising: forming a buffer oxide film and a nitride film on a silicon substrate, and then removing the nitride film in a region where a field oxide film is to be formed; A second step of forming a first field oxide film through a thermal oxidation process; A third step of forming a second field oxide film after removing the first field oxide film; And a fourth step of removing the nitride film and the buffer oxide film. 제1항에 있어서, 상기 완충산화막 및 질화막은 1대 5내지 50의 두께비로 형성되는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.The method of claim 1, wherein the buffer oxide film and the nitride film are formed in a thickness ratio of 1 to 5 to 50. 제2항에 있어서, 상기 제1단계 후 노출된 실리콘기판에 채널스톱 불순물을 이온주입하는 제5단계를 더 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.3. The method of claim 2, further comprising a fifth step of ion implanting channel stop impurities into the exposed silicon substrate after the first step. 제1항 또는 제3항에 있어서, 상기 제1필드산화막의 제거는 비등방성식각 또는 비등방성식각 및 등방성식각의 병행 중 어느 하나에 의해 이루어지는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.The method of claim 1 or 3, wherein the first field oxide film is removed by any one of anisotropic etching, anisotropic etching, and anisotropic etching. 반도체 소자 제조공정중 활성영역간의 전기적 격리를 위한 소자분리막 형성방법에 있어서, 실리콘기판에완충산화막, 폴리실리콘막, 질화막을 형성한 후 필드산화막이 형성될 영역의 상기 질화막, 폴리실리콘막을 제거하는 단계; 열산화공정을 통해 제1필드산화막을 형성하는 단계; 상기 제1필드산화막을 제거한 후 제2필드산화막을 형성하는 단계;상기 질화막, 폴리실리콘막, 완충산화막을 제거하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.A method of forming a device isolation film for electrical isolation between active regions in a semiconductor device manufacturing process, the method comprising: removing a nitride film and a polysilicon film in a region where a field oxide film is to be formed after forming a buffer oxide film, a polysilicon film, and a nitride film on a silicon substrate; ; Forming a first field oxide film through a thermal oxidation process; Forming a second field oxide film after removing the first field oxide film; and removing the nitride film, the polysilicon film, and the buffer oxide film. 제5항에 있어서, 상기 제1필드산화막의 제거는 비등방성식각 또는 비등방성식각 및 등방성식각 의 병행중 어느 하나에 의해 이루어지는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.6. The method of claim 5, wherein the first field oxide film is removed by anisotropic etching, or anisotropic etching and anisotropic etching. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950019155A 1995-06-30 1995-06-30 Method of manufacturing a semiconductor device provided with an isolation region KR0167675B1 (en)

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Application Number Priority Date Filing Date Title
KR1019950019155A KR0167675B1 (en) 1995-06-30 1995-06-30 Method of manufacturing a semiconductor device provided with an isolation region

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KR970003823A true KR970003823A (en) 1997-01-29
KR0167675B1 KR0167675B1 (en) 1999-02-01

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