KR970053492A - Semiconductor Device Separation Method - Google Patents

Semiconductor Device Separation Method Download PDF

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KR970053492A
KR970053492A KR1019950069586A KR19950069586A KR970053492A KR 970053492 A KR970053492 A KR 970053492A KR 1019950069586 A KR1019950069586 A KR 1019950069586A KR 19950069586 A KR19950069586 A KR 19950069586A KR 970053492 A KR970053492 A KR 970053492A
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South Korea
Prior art keywords
oxide film
silicon substrate
trench
forming
region
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KR1019950069586A
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Korean (ko)
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KR100204416B1 (en
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박상훈
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김주용
현대전자산업 주식회사
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Priority to KR1019950069586A priority Critical patent/KR100204416B1/en
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Publication of KR100204416B1 publication Critical patent/KR100204416B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 반도체 소자 분리방법에 관한 것으로, 영역 분리가 요구되는 실리콘 기판상에 패드 산화막과 질화막을 형성하는 단계; 상기 질화막과 패드 산화막을 선택적으로 식각하여 소자 분리 영역을 구축한 후 이 소자 분리 영역의 실리콘 기판에 소정 깊이의 트렌치를 형성하고 이 트렌치의 내부에 이온을 주입하여 채널 스톱 영역을 형성하는 단계; 상기 질화막을 산화 방지층으로 열산화법을 이용하여 트렌치 내부에 열산화막을 형성하는 단계; 산화 방지층으로 사용된 질화막을 제거한 후 전체 구조의 상부에 테오스 산화막을 증착하는 단계; 상기 테오스 산화막과 패드 산화막을 실리콘 기판과 동일 평면이 되도록 연마하여 필드 산화막을 형성하는 단계; 상기 필드 산화막과 실리콘 기판의 저농도 채널 스톱 영역을 포함하지 않는 소정의 감광막 패턴을 형성한 후 이 감광막 패턴을 이온 저지층으로 소자 분리 영역 양측의 실리콘 기판상에 저농도 채널 스톱용 불순물과 동일한 조건으로 이온을 주입하고 고농도 채널 스톱 영역을 형성하는 단계; 및 이온 저지층으로 사용된 감광막 패턴을 제거하는 단계로 구성한 것이다. 이와 같은 본 발명에 의한 반도체 소자 분리방법은 질화막을 사용하지 않는 트렌치 형태의 필드 산화막을 형성하여 소자를 분리하는 방법으로써, 질화막을 사용하지 않음으로 인한 파티클의 오염을 줄일 수 있고, 또한 활성 영역을 충분히 확보할 수 있으므로 반도체 소자의 집적도 및 전기적 특성을 개선시킬 수 있다.The present invention relates to a method for separating semiconductor devices, comprising: forming a pad oxide film and a nitride film on a silicon substrate requiring region separation; Selectively etching the nitride film and the pad oxide film to form an isolation region, forming a trench having a predetermined depth in the silicon substrate of the isolation region, and implanting ions into the trench to form a channel stop region; Forming a thermal oxide film inside the trench using a thermal oxidation method as the oxidation prevention layer; Removing the nitride film used as the anti-oxidation layer and depositing a theos oxide film on top of the entire structure; Polishing the theos oxide film and the pad oxide film to be coplanar with a silicon substrate to form a field oxide film; After forming a predetermined photoresist pattern that does not include the low concentration channel stop region of the field oxide film and the silicon substrate, the photoresist pattern is used as an ion blocking layer on the silicon substrate on both sides of the device isolation region under the same conditions as the impurities for the low concentration channel stop. Implanting and forming a high concentration channel stop region; And removing the photosensitive film pattern used as the ion blocking layer. The semiconductor device isolation method according to the present invention forms a trench type field oxide film that does not use a nitride film, and separates the devices. Thus, contamination of particles due to the absence of a nitride film can be reduced, and an active region can be reduced. Since it can ensure enough, the integration degree and electrical characteristics of a semiconductor element can be improved.

Description

반도체 소자 분리방법Semiconductor Device Separation Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 (a)(b)(c)(d)(e)(f)는 본 발명의 반도체 소자 분리방법에 대한 공정도.3 is a process diagram for the semiconductor device isolation method of the present invention (a) (b) (c) (d) (e) (f).

Claims (6)

영역 분리가 요구되는 실리콘 기판상에 패트 산화막과 질화막을 형성하는 단계; 상기 질화막과 패드 산화막을 선택적으로 식각하여 소자 분리 영역을 구축한 후 이 소자 분리 영역의 실리콘 기판에 소정 깊이의 트렌치를 형성하고 이 트렌치의 내부에 이온을 주입하여 채널 스톱 영역을 형성하는 단계; 상기 질화막을 산화 방지층으로 열산화법을 이용하여 트렌치 내부에 열산화막을 형성하는 단계; 산화 방지층으로 사용된 질화막을 제거한 후 전체 구조의 상부에 테오스 산화막을 증착하는 단계; 상기 테오스 산화막과 패드 산화막을 실리콘 기판과 동일 평면이 되도록 연마하여 필드 산화막을 형성하는 단계; 상기 필드 산화막과 실리콘 기판의 저농도 채널 스톱 영역을 포함하지 않는 소정의 감광막 패턴을 형성한 후 이 감광막 패턴을 이온 저지층으로 소자 분리 영역 양측의 실리콘 기판상에 저농도 채널 스톱용 불순물과 동일한 조건으로 이온을 주입하여 고농도 채널 스톱 영역을 형성하는 단계; 및 이온 저지층으로 사용된 감광막 패턴을 제거하는 단계로 구성함을 특징으로 하는 반도체 소자 분리 방법.Forming a pat oxide film and a nitride film on a silicon substrate requiring region separation; Selectively etching the nitride film and the pad oxide film to form an isolation region, forming a trench having a predetermined depth in the silicon substrate of the isolation region, and implanting ions into the trench to form a channel stop region; Forming a thermal oxide film inside the trench using a thermal oxidation method as the oxidation prevention layer; Removing the nitride film used as the anti-oxidation layer and depositing a theos oxide film on top of the entire structure; Polishing the theos oxide film and the pad oxide film to be coplanar with a silicon substrate to form a field oxide film; After forming a predetermined photoresist pattern that does not include the low concentration channel stop region of the field oxide film and the silicon substrate, the photoresist pattern is used as an ion blocking layer on the silicon substrate on both sides of the device isolation region under the same conditions as the impurities for the low concentration channel stop. Injecting to form a high concentration channel stop region; And removing the photoresist pattern used as the ion blocking layer. 제1항에 있어서, 상기 트렌치는 약 0.5 - 1.2㎛ 정도의 깊이로 형성하는 것을 특징으로 하는 반도체 소자 분리방법.The method of claim 1, wherein the trench is formed to a depth of about 0.5-1.2 μm. 제1항에 있어서, 상기 채널 스톱용으로 주입되는 이온은 BF2이며, 이 불순물을 20 - 50KeV, 1×1012~ 1×1017원자/C㎥의 조건으로 트렌치의 내부에 주입하는 것을 특징으로 하는 반도체 소자 분리 방법.The method of claim 1, wherein the ion implanted for the channel stop is BF 2 , and the impurity is implanted into the trench under the condition of 20-50 KeV, 1 × 10 12 to 1 × 10 17 atoms / Cm 3. A semiconductor element isolation method. 제1항에 있어서, 상기 열산화막은 1000 ~ 2000 Å 정도의 두께로 형성하는 것을 특징으로 하는 반도체 소자 분리방법.The method of claim 1, wherein the thermal oxide film is formed to a thickness of about 1000 ~ 2000 GPa. 제1항에 있어서, 상기 테오스 산화막은 3000 ~ 8000Å 정도의 두께로 형성하는 것을 특징으로 하는 반도체 소자 분리방법.The method of claim 1, wherein the theos oxide film is formed to a thickness of about 3000 ~ 8000 Å. 제1항 내지 제5항 중 어느 한 항에 있어서, 테어스 산화막 및 패드 산화막의 연마는 강산의 슬러리를 사용한 화학 - 기계적 연마법인 것을 특징으로 하는 반도체 소자 분리방법.The semiconductor device separation method according to any one of claims 1 to 5, wherein the polishing of the tears oxide film and the pad oxide film is a chemical-mechanical polishing method using a slurry of strong acid. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950069586A 1995-12-30 1995-12-30 Method for forming an element isolation in a semiconductor device KR100204416B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100480571B1 (en) * 1997-11-13 2005-07-25 삼성전자주식회사 Device Separation Method in Semiconductor Devices

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100401527B1 (en) * 1996-04-24 2003-12-24 주식회사 하이닉스반도체 Isolation method of semiconductor device
KR100487513B1 (en) * 1998-07-10 2005-07-07 삼성전자주식회사 A method for fabricating trench isolation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100480571B1 (en) * 1997-11-13 2005-07-25 삼성전자주식회사 Device Separation Method in Semiconductor Devices

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