KR970054087A - Well Forming Method of Semiconductor Device - Google Patents

Well Forming Method of Semiconductor Device Download PDF

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Publication number
KR970054087A
KR970054087A KR1019950062055A KR19950062055A KR970054087A KR 970054087 A KR970054087 A KR 970054087A KR 1019950062055 A KR1019950062055 A KR 1019950062055A KR 19950062055 A KR19950062055 A KR 19950062055A KR 970054087 A KR970054087 A KR 970054087A
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South Korea
Prior art keywords
film
oxide film
oxidizable
field oxide
antioxidant
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KR1019950062055A
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Korean (ko)
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KR0179794B1 (en
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이혁재
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문정환
Lg 반도체 주식회사
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Priority to KR1019950062055A priority Critical patent/KR0179794B1/en
Priority to US08/773,594 priority patent/US5705422A/en
Priority to JP8350685A priority patent/JP2838692B2/en
Publication of KR970054087A publication Critical patent/KR970054087A/en
Application granted granted Critical
Publication of KR0179794B1 publication Critical patent/KR0179794B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

본 발명은 반도체 소자의 웰 형성방법에 관한 것으로, 반도체 기판상의 주변회로부에 완충막과, 상기 완충막 위에 산화가능막과, 상기 산화가능막 위에 산화방지막을 형성하는 공정과; 상기 산화가능막의 표면이 일부 드러나도록 산화방지막을 소정 부분 식각하는 공정과; 열산화를 실시하여 주변회로부의 산화가능막이 노출된 부분과, 기판 표면이 노출된 셀 형성부에 필드 산화막을 형성하는 공정과; 상기 산화방지막과 산화가능막 및 완충막을 제거하는 공정과; 고 에너지로 제1도전형 불순물을 이온주입하는 공정과; 상기 필드 산화막을 마스크로 하여 저 에너지로 제2도전형 불순물을 이온주입하는 공정 및; 상기 필드 산화막을 제거하고, 확산을 실시하여 제1및 제2도전형 웰을 형성하는 공정을 포함하여 소자 제조를 완료하므로써, 1) 공정단순화를 기할 수 있게 되어 공정 시간 단축 및 생산성 향상을 이룰 수 있으며, 2) 고 에너지 이온주입시 필수적으로 이용되는 4㎛ 이상의 두꺼운 감광막을 사용할 필요가 없어 고에너지 이온주입 과정에서 감광막 입자에 의해 발생되는 실리콘 기판의 격자 손상(defect)을 방지할 수 있고, 3) 래치-업 내성(immunity)을 향상시킬 수 있는 고신뢰성의 반도체 소자를 구현할 수 있게 된다.The present invention relates to a method for forming a well of a semiconductor device, the method comprising: forming a buffer film on a peripheral circuit portion on a semiconductor substrate, an oxidizable film on the buffer film, and an antioxidant film on the oxidizable film; Etching a portion of the antioxidant film to partially expose the surface of the oxide film; Forming a field oxide film by thermal oxidation to expose a portion of the peripheral circuit portion to which an oxidizable film is exposed and a substrate surface to which a substrate surface is exposed; Removing the antioxidant film, the oxidizable film, and the buffer film; Ion implanting the first conductivity type impurities with high energy; Ion implanting a second conductive impurity with low energy using the field oxide film as a mask; By completing the device manufacturing process including removing the field oxide film and performing diffusion to form the first and second conductive wells, 1) the process can be simplified, resulting in a shorter process time and improved productivity. 2) It is not necessary to use a thick photosensitive film of 4 ㎛ or more, which is essentially used for high energy ion implantation, thereby preventing lattice damage of the silicon substrate caused by the photosensitive film particles during the high energy ion implantation process. A highly reliable semiconductor device capable of improving latch-up immunity can be realized.

Description

반도체 소자의 웰 형성방법Well Forming Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2(a) 내지 제2(g)도는 본 발명에 따른 반도체 소자의 웰 형성방법을 도시한 공정수순도.2 (a) to 2 (g) are process flowcharts showing a well forming method of a semiconductor device according to the present invention.

Claims (7)

반도체 기판상의 주변회로부에 완충막과, 상기 완충막 위에 산화가능막과, 상기 산화가능막 위에 산화방지막을 형성하는 공정과; 상기 산화가능막의 표면이 일부 드러나도록 산화방지막을 소정 부분 식각하는 공정과; 열산화를 실시하여 주변회로부의 산화가능막이 노출된 부분과, 기판 표면이 노출된 셀 형성부에 필드 산화막을 형성하는 공정과; 상기 산화방지막과 산화가능막 및 완충막을 제거하는 공정과; 고 에너지로 제1도전형 불순물을 이온주입하는 공정과; 상기 필드 산화막을 마스크로 하여 저 에너지로 제2도전형 불순물을 이온주입하는 공정 및; 상기 필드 산화막을 제거하고, 확산을 실시하여 제1및 제2도전형 웰을 형성하는 공정을 포함하여 형성되는 것을 특징으로 하는 반도체 소자의 웰 형성방법.Forming a buffer film on the peripheral circuit portion on the semiconductor substrate, an oxide film on the buffer film, and an antioxidant film on the oxide film; Etching a portion of the antioxidant film to partially expose the surface of the oxide film; Forming a field oxide film by thermal oxidation to expose a portion of the peripheral circuit portion to which an oxidizable film is exposed and a substrate surface to which a substrate surface is exposed; Removing the antioxidant film, the oxidizable film, and the buffer film; Ion implanting the first conductivity type impurities with high energy; Ion implanting a second conductive impurity with low energy using the field oxide film as a mask; And removing the field oxide film and diffusing to form first and second conductive wells. 제1항에 있어서, 상기 완충막은 50Å 내지 300Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 웰 형성방법.The method of claim 1, wherein the buffer film is formed to have a thickness of about 50 μs to about 300 μs. 제1항에 있어서, 상기 제1도전형 불순물은 2MeV 내지 4MeV의 고 에너지로 이온주입되는 것을 특징으로 하는 반도체 소자의 웰 형성방법.The method of claim 1, wherein the first conductive impurity is ion implanted at a high energy of 2MeV to 4MeV. 제1항에 있어서, 상기 제2도전형 불순물은 100KeV 내지 200KeV의 저 에너지로 이온주입되는 것을 특징으로 하는 반도체 소자의 웰 형성방법.The method of claim 1, wherein the second conductive impurity is implanted at a low energy of 100 KeV to 200 KeV. 제1항에 있어서, 상기 산화가능막은 다결정실리콘으로 형성되는 것을 특징으로 하는 반도체 소자의 웰 형성방법.The method of claim 1, wherein the oxidizable film is formed of polycrystalline silicon. 제1항에 있어서, 상기 제1도전형 웰은 P형 불순물을 확산시켜 형성하는 것을 특징으로 하는 반도체 소자의 웰 형성방법.The method of claim 1, wherein the first conductive well is formed by diffusing P-type impurities. 제1항에 있어서, 상기 제2도전형 웰은 N형 불순물을 확산시켜 형성하는 것을 특징으로 하는 반도체 소자의 웰 형성방법.The method of claim 1, wherein the second conductive well is formed by diffusing N-type impurities. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950062055A 1995-12-28 1995-12-28 Well-forming method of semiconductor device KR0179794B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019950062055A KR0179794B1 (en) 1995-12-28 1995-12-28 Well-forming method of semiconductor device
US08/773,594 US5705422A (en) 1995-12-28 1996-12-27 Method for forming well of semiconductor device
JP8350685A JP2838692B2 (en) 1995-12-28 1996-12-27 Method for forming well of semiconductor device

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Application Number Priority Date Filing Date Title
KR1019950062055A KR0179794B1 (en) 1995-12-28 1995-12-28 Well-forming method of semiconductor device

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KR970054087A true KR970054087A (en) 1997-07-31
KR0179794B1 KR0179794B1 (en) 1999-03-20

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US6727161B2 (en) 2000-02-16 2004-04-27 Cypress Semiconductor Corp. Isolation technology for submicron semiconductor devices
KR100339425B1 (en) * 2000-07-21 2002-06-03 박종섭 Semiconductor device and Method for Manufacturing with recessed SOI structure
WO2004081788A1 (en) * 2003-03-10 2004-09-23 Catena Corporation Static analysis method for lyee-oriented software
JP5083088B2 (en) 2008-07-23 2012-11-28 富士通株式会社 Electronic component unit and coupling mechanism

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US5292671A (en) * 1987-10-08 1994-03-08 Matsushita Electric Industrial, Co., Ltd. Method of manufacture for semiconductor device by forming deep and shallow regions
JPH01161752A (en) * 1987-12-18 1989-06-26 Toshiba Corp Manufacture of semiconductor device
US5451530A (en) * 1990-12-21 1995-09-19 Texas Instruments Incorporated Method for forming integrated circuits having buried doped regions
JP2795565B2 (en) * 1991-10-08 1998-09-10 シャープ株式会社 Method for manufacturing semiconductor storage element

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JPH104147A (en) 1998-01-06
US5705422A (en) 1998-01-06
KR0179794B1 (en) 1999-03-20
JP2838692B2 (en) 1998-12-16

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