KR100192166B1 - Method of forming twin well of semiconductor device - Google Patents

Method of forming twin well of semiconductor device Download PDF

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KR100192166B1
KR100192166B1 KR1019950016341A KR19950016341A KR100192166B1 KR 100192166 B1 KR100192166 B1 KR 100192166B1 KR 1019950016341 A KR1019950016341 A KR 1019950016341A KR 19950016341 A KR19950016341 A KR 19950016341A KR 100192166 B1 KR100192166 B1 KR 100192166B1
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well
forming
ion implantation
semiconductor device
energy range
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KR1019950016341A
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KR970003686A (en
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황준
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks

Abstract

본 발명은 반도체 소자의 트윈웰 형성방법에 관한 것으로, 보다 구체적으로는 반도체 소자의 트윈웰 형성 공정시 3중 이온 주입 공정을 실시하여 제조 공기를 단축할 수 있는 반도체 소자의 트윈웰 형성방법에 관한 것으로 본 발명은 반도체 소자중, 특히 CMOS 소자를 제조하기 위하여 제안된 트윈웰 제조공정시 웰을 제조하기 위한 동일 이온을 각각의 이온 주입시 에너지 범위를 달리하여 실시하므로써, 웰의 경계부분의 내부 확산을 방지하고, 제조 공기를 단축할 수 있어 소자의 제조 단가를 절감할 수 있다.The present invention relates to a method of forming a twin well of a semiconductor device, and more particularly, to a method of forming a twin well of a semiconductor device capable of shortening manufacturing air by performing a triple ion implantation process during a twin well forming process of a semiconductor device. In the present invention, the diffusion of the inside of the boundary portion of a well is performed by varying the energy range of each ion implantation of the same ion for manufacturing the well during the proposed twin well fabrication process, particularly for CMOS devices. Can be prevented and manufacturing air can be shortened, thereby reducing the manufacturing cost of the device.

Description

반도체 소자의 트윈웰 형성 방법Twin Well Forming Method of Semiconductor Device

제1도는 종래의 반도체 소자의 트윈웰 구조를 나타낸 단면도.1 is a cross-sectional view showing a twin well structure of a conventional semiconductor device.

제2도(a) 내지 (c)는 본 발명에 따른 반도체 소자의 웰 형성방법을 순차적으로 나타낸 요부단면도.2 (a) to (c) are cross-sectional views of main parts sequentially showing a well forming method of a semiconductor device according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 반도체 기판 2 : 산화막1 semiconductor substrate 2 oxide film

3 : 보론 이온 4 : 인 이온3: boron ion 4: phosphorus ion

10 : P웰 이온 주입 마스크 11 : N웰 이온 주입 마스크10: P well ion implantation mask 11: N well ion implantation mask

13 : P웰 14 : N웰13: P well 14: N well

본 발명은 반도체 소자의 트윈웰 형성방법에 관한 것으로, 보다 구체적으로는 반도체 소자의 트윈웰 형성 공정시 3중 이온 주입 공정을 실시하여 제조 공기를 단축할 수 있는 반도체 소자의 트윈웰 형성방법에 관한 것이다.The present invention relates to a method of forming a twin well of a semiconductor device, and more particularly, to a method of forming a twin well of a semiconductor device capable of shortening manufacturing air by performing a triple ion implantation process during a twin well forming process of a semiconductor device. will be.

일반적으로 CMOS 기술은, 같은 설계 규칙을 갖는 PMOS 또는 NMOS 기술에 비하여 낮은 전력-지연시간의 곱(power delay product)을 얻을 수 있고, 신뢰도 또한 우수하므로, 현재의 고집적 시스템에 적합한 기술로 인식되어 있다. 저전력 정적회로를 구사할 수 있는 CMOS 소자는, 웨이퍼 기판상에 반대극성인 PMOS와 NMOS를 함께 제작해야 하므로 트윈웰의 형성은 필수적으로 요구되고 있다.In general, CMOS technology is recognized as a suitable technology for today's high-integrated systems because it can obtain a low power-delay product and superior reliability compared to PMOS or NMOS technology with the same design rules. . In a CMOS device capable of using low power static circuits, the formation of twin wells is indispensable because a PMOS and an NMOS having opposite polarities must be fabricated on a wafer substrate.

초기의 웰 구조는 N 또는 P 기판상에 P웰 또는 N웰을 형성하여 CMOS를 구성하는 단일 웰 구조로 되어 있었으나, 이러한 단일 웰은 P웰인 경우, 웰 플로팅(floating)되면 정공이 N 기판상에 쌓이게 되어 본체 전압이 높아짐으로써 기생 트랜지스터가 생기는 단점이 있으며, N웰인 경우는 필드 반전이 민감하고, 순수한 정적상태를 구축하기 어렵다는 단점이 부각되었다.Initially, the well structure had a single well structure in which a P well or N well was formed on an N or P substrate to form a CMOS. However, when the single well is a P well, holes are floated on the N substrate when the well floats. As a result, the parasitic transistor is generated due to the increase in the main body voltage, and in the case of N well, the field reversal is sensitive and it is difficult to establish a pure static state.

따라서, CMOS 소자의 제조에 있어서, P형과 N형 트랜지스터들을 개별적으로 최적화시킬 수 있고, 공정자가 웰 농도를 용이하게 조절할 수 있으며, N형과 P형 디바이스들의 임계전압, 본체 효과 및 이득을 독립적으로 최적화시킬 수 있는 트윈웰 형성방법이 제안되었다.Therefore, in the fabrication of CMOS devices, the P-type and N-type transistors can be optimized separately, the processor can easily adjust the well concentration, and independently of the threshold voltage, body effect and gain of the N-type and P-type devices. A twin well formation method has been proposed that can be optimized by the method.

종래의 트윈웰 형성방법을 도면에 의거하여 구체적으로 살펴보면, 제1도에서 나타낸 바와 같이, 우선, 낮게 도핑된 기판(1) 상부에 산화막을 500Å 정도로 성장시키고, 기판의 소정 영역에 P웰을 형성하기 위한 포토레지스트를 도포하여 P웰 마스크(10) 패턴을 형성한 다음, P형 도펀트인 보론(3:boron)를 P웰 영역에 주입하여 P웰(13)을 형성한다. 그후, P웰 마스크 패턴을 제거한 후 N웰이 될 영역의 상부 포토레지스트층을 제거하여 N형 도펀트인 인(4:phosphorus)을 N웰 영역(14)에 주입하여 N웰을 형성한다. 이후, N웰을 형성하기 위한 N웰 마스크(11)인 포토레지스트 마스크를 제거한 후, 웰의 이온 주입물들을 드라이브 인(drive-in)하여 확산시키고, 실리콘 산화막을 제거하는 공정으로 트윈웰을 형성하게 된다.The conventional twin well forming method will be described in detail with reference to the drawings. As shown in FIG. 1, first, an oxide film is grown on the lower doped substrate 1 to about 500 kV, and a P well is formed in a predetermined region of the substrate. After forming a P well mask 10 pattern by applying a photoresist, a P well 13 is formed by injecting boron (3: boron), which is a P-type dopant, into the P well region. Thereafter, after removing the P well mask pattern, the upper photoresist layer of the region to be the N well is removed to implant N-type dopant phosphorus (4: phosphorus) into the N well region 14 to form the N well. Subsequently, after removing the photoresist mask, which is the N well mask 11 for forming the N well, the ion implants in the well are drive-in and diffused, and the twin well is formed by removing the silicon oxide layer. Done.

그러나, 상기한 방법으로 형성된 트윈웰은 단일 이온 주입 방법으로 각각의 웰을 형성한 후, 고온에서 장시간의 드라이브 인 공정을 진행하여야 하기 때문에 P웰(13)과 N웰(14) 사이에 불순물의 내부확산이 크게 발생하여 고집적 소자에 형성하기 어려운 문제점이 발생하였고, 장시간의 드라이브 인 공정을 인하여 제조 공기가 긴 단점이 상존하고 있었다.However, since the twin wells formed by the above-described method have to form a respective well by a single ion implantation method, a drive-in process must be performed at a high temperature for a long time, so that impurities of P wells 13 and N wells 14 can be removed. Due to the large internal diffusion, it was difficult to form a highly integrated device, and due to a long drive-in process, a long manufacturing air had a disadvantage.

본 발명은 전술한 종래의 문제점을 해결하기 위한 것으로, 웰간의 경계면에 내부 확산을 방지하여 보다 고집적 회로 설계에 유리하고, 제조 공정 시간을 단축시킬 수 있는 반도체 소자의 트윈웰 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and provides a method of forming a twin well of a semiconductor device, which is advantageous in designing a more integrated circuit and shortening a manufacturing process time by preventing internal diffusion at an interface between wells. There is a purpose.

상기와 같은 본 발명의 목적을 달성하기 위하여 본 발명은, 반도체 소자의 트윈웰 형성방법에 있어서, 각각의 웰을 형성하기 위한 이온 주입 공정시 에너지 범위를 달리하여 3중의 이온 주입 공정을 실시하여 웰을 형성하는 것을 특징으로 한다.In order to achieve the object of the present invention as described above, the present invention, in the twin well forming method of the semiconductor device, by performing a triple ion implantation process by varying the energy range during the ion implantation process for forming each well It characterized in that to form.

이하, 첨부한 도면에 의거하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

첨부한 도면 제2도(a) 내지 (c)는 본 발명에 따른 반도체 소자의 트윈웰 형성방법을 공정 순서대로 나타낸 단면도로서, 우선, 제2도(a)에 도시된 바와 같이, 반도체 기판(1)상에 산화막(2)을 200 내지 600Å 정도 성장시킨 후, 상기 산화막(2)상에 포토레지스트막을 전면 도포한다음, 현상, 노광하여 P웰이 형성될 예정영역이 노출되도록 포토레지스트 마스크 패턴을 형성한다. 그후, 상기 포토레지스트 마스크 패턴을 P웰 이온 주입 마스크(10)으로 하여 P웰을 형성하기 위한 이온 주입을 실시한다. 상기 P웰을 형성하기 위한 이온 주입되는 이온은 보론 이온(3)으로 하고, 이온 주입은 3중으로 실시하게 되는데, 이때 1차 이온 주입은 300KeV의 에너지 범위로 실시하고, 2차 이온 주입은 100 내지 150KeV의 에너지 범위로 실시하고, 3차 이온 주입은 20 내지 30KeV의 에너지 범위로 실시한다. 상기 P형의 이온은 확산이 많이 일어나므로 적은 에너지 범위로 투사함이 바람직하다.2 (a) to (c) are cross-sectional views illustrating a process of forming a twin well of a semiconductor device according to the present invention in order of processing. First, as shown in FIG. 1) After growing the oxide film 2 on the order of 200 to 600Å, the entire surface of the photoresist film is coated on the oxide film 2, and then developed and exposed to expose the photoresist mask pattern so as to expose a region where a P well is to be formed. To form. Thereafter, ion implantation for forming P wells is performed using the photoresist mask pattern as the P well ion implantation mask 10. The ion implanted ions to form the P well is boron ions (3), the ion implantation is carried out in triple, wherein the primary ion implantation is carried out in the energy range of 300 KeV, the secondary ion implantation is 100 to The energy range is 150 KeV and the third ion implantation is performed in the energy range 20 to 30 KeV. Since the P-type ions diffuse a lot, it is preferable to project them in a small energy range.

그후, 제2도(b)에 도시된 바와 같이, P웰 이온 주입 마스크(10)를 통상의 제거방법으로 제거한 후, 다시 산화막 상부에 포토레지스트막을 형성하고, 현상 노광하여 N웰이 형성될 예정영역이 노출되도록 포토레지스트 마스크 패턴을 형성한다. 그후, 상기 포토레지스트 마스크 패턴을 N웰 이온 주입 마스크(11)으로 하여 N웰을 형성하기 위한 이온 주입을 실시한다. 상기 N웰을 형성하기 위한 이온 주입되는 이온은 인 이온(4)으로 하고, N웰도 상기 P웰과 마찬가지로 3중으로 이온 주입을 실시하게 되는데, 이때 1차 이온 주입은 600 내지 800KeV의 에너지 범위로 실시하고, 2차 이온 주입은 150 내지 200KeV의 에너지 범위로 실시하고, 3차 이온 주입은 70 내지 100KeV의 에너지 범위로 실시한다.Thereafter, as shown in FIG. 2 (b), the P well ion implantation mask 10 is removed by a conventional removal method, and then a photoresist film is formed on the oxide film, and developed and exposed to N wells. A photoresist mask pattern is formed to expose the region. Thereafter, ion implantation for forming an N well is performed using the photoresist mask pattern as an N well ion implantation mask 11. The ion implanted ions for forming the N well are phosphorus ions (4), and the N well is ion-implanted in the same manner as the P well, wherein the primary ion implantation is performed in an energy range of 600 to 800 KeV. The secondary ion implantation is carried out in an energy range of 150 to 200 KeV, and the third ion implantation is performed in an energy range of 70 to 100 KeV.

그런 다음, 제2도(c)에 도시된 바와 같이, 상기 N웰 이온 주입 마스크(11) 및 기판(1) 상부의 산화막(2)을 제거하고, 드라이브 인 공정을 진행하여 소망하는 트윈웰(13,14)을 형성한다.Next, as shown in FIG. 2C, the N well ion implantation mask 11 and the oxide film 2 on the substrate 1 are removed, and a drive-in process is performed to perform a desired twin well ( 13,14).

이상에서 자세히 설명한 바와 같이, 본 발명은 반도체 소자중, 특히 CMOS 소자를 제조하기 위하여 제안된 트윈웰 제조공정시 웰을 제조하기 위한 동일 이온을 각각의 이온 주입시 에너지 범위를 달리하여 실시하므로써, 웰의 경계부분의 내부 확산을 방지하고, 제조 공기를 단축할 수 있어 소자의 제조 단가를 절감할 수 있다.As described in detail above, the present invention is carried out by varying the energy range in each ion implantation of the same ions for manufacturing the wells in the twin-well manufacturing process proposed for manufacturing the CMOS devices, in particular, CMOS devices. It is possible to prevent the internal diffusion of the boundary portion of the and to shorten the manufacturing air can reduce the manufacturing cost of the device.

Claims (5)

기판상에 P웰 이온 주입 마스크를 형성하고, P형의 불순물을 주입한다음, N형의 이온 주입 마스크를 형성하고 N형의 불순물 이온을 주입한 후 드라이브 인 공정을 진행하는 단계를 포함하는 반도체 소자의 트윈웰 형성방법에 있어서, 상기 P웰 및 N웰을 형성하기 위한 이온 주입 공정시 각각 에너지 범위를 달리하여 3중의 이온 주입 공정을 실시하여 웰을 형성하는 것을 특징으로 하는 반도체 소자의 트윈웰 형성방법.Forming a P well ion implantation mask on a substrate, implanting a P-type impurity, forming an N-type ion implantation mask, implanting an N-type impurity ion, and then performing a drive-in process A method of forming a twin well of a device, wherein the wells are formed by performing a triple ion implantation process by varying an energy range in an ion implantation process for forming the P well and the N well. Formation method. 제1항에 있어서, 상기 트윈웰 중 P웰을 형성하기 위한 불순물 이온은 보론인 것을 특징으로 하는 반도체 소자의 트윈웰 형성방법.The method of claim 1, wherein the impurity ions for forming P wells in the twin wells are boron. 제1항 또는 제2항에 있어서, 상기 P웰을 형성하기 위하여 1차 이온 주입은 300 내지 600KeV의 에너지 범위로 실시하고, 2차 이온 주입은 100 내지 150KeV의 에너지 범위로 실시하고, 3차 이온 주입은 20 내지 30KeV의 에너지 범위로 실시하는 것을 특징으로 하는 반도체 소자의 트윈웰 형성방법.The method of claim 1, wherein the primary ion implantation is performed in an energy range of 300 to 600 KeV, the secondary ion implantation is performed in an energy range of 100 to 150 KeV, and the tertiary ion to form the P well. Twinwell forming method of a semiconductor device, characterized in that the implantation is performed in the energy range of 20 to 30 KeV. 제1항에 있어서, 상기 트윈웰 중 N웰을 형성하기 위한 불순물 이온은 인이온인 것을 특징으로 하는 반도체 소자의 트윈웰 형성방법.The method of claim 1, wherein the impurity ions for forming N wells in the twin wells are phosphorus ions. 제1항 또는 제4항에 있어서, 상기 N웰을 형성하기 위하여 1차 이온 주입은 600 내지 800KeV의 에너지 범위로 실시하고, 2차 이온 주입은 150 내지 200KeV의 에너지 범위로 실시하고, 3차 이온 주입은 70 내지 100KeV의 에너지 범위로 실시하는 것을 특징으로 하는 반도체 소자의 트윈웰 형성방법.The method of claim 1, wherein the primary ion implantation is performed in an energy range of 600 to 800 KeV, the secondary ion implantation is performed in an energy range of 150 to 200 KeV, and the tertiary ion to form the N well. Twinwell forming method of a semiconductor device, characterized in that the implantation is performed in the energy range of 70 to 100 KeV.
KR1019950016341A 1995-06-20 1995-06-20 Method of forming twin well of semiconductor device KR100192166B1 (en)

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