GB2320802A - Method of fabricating a semiconductor device having triple wells - Google Patents
Method of fabricating a semiconductor device having triple wells Download PDFInfo
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- GB2320802A GB2320802A GB9722437A GB9722437A GB2320802A GB 2320802 A GB2320802 A GB 2320802A GB 9722437 A GB9722437 A GB 9722437A GB 9722437 A GB9722437 A GB 9722437A GB 2320802 A GB2320802 A GB 2320802A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title abstract description 4
- 239000007943 implant Substances 0.000 claims abstract description 74
- 238000000034 method Methods 0.000 claims abstract description 67
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 239000012535 impurity Substances 0.000 claims abstract description 51
- 150000002500 ions Chemical class 0.000 claims abstract description 51
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 45
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 45
- 239000010703 silicon Substances 0.000 claims abstract description 45
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 25
- 238000002955 isolation Methods 0.000 claims abstract description 20
- 238000005468 ion implantation Methods 0.000 claims abstract description 13
- 230000003647 oxidation Effects 0.000 claims abstract description 10
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 10
- -1 phosphorous ions Chemical class 0.000 claims description 19
- 229910052796 boron Inorganic materials 0.000 claims description 14
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 2
- 230000007547 defect Effects 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000002513 implantation Methods 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
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- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- High Energy & Nuclear Physics (AREA)
- Manufacturing & Machinery (AREA)
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- Health & Medical Sciences (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract
A method for fabricating a semiconductor device, in which a triple well is formed using two masks upon forming transistors of a memory device, thereby achieving a simplification in the fabrication processes and obtaining stabilized characteristics of the semiconductor device. The method includes the steps of forming an element isolation mask 30 on a silicon substrate, implanting N-type impurity ions in an exposed portion of the semiconductor substrate by use of an N-well mask 4, removing the N-well mask, and forming a field oxide film on the silicon substrate while simultaneously driving the N-type impurity ions of the N-well implant region into the semiconductor substrate in accordance with a thermal oxidation process, thereby forming a diffused N-well. In accordance with this method, the N-well is formed without a drive-in process. After the formation of the N-well, a P-well mask 18 is formed on the silicon substrate. Finally, P-type impurity ions are implanted in an exposed portion of the silicon substrate while varying a concentration of the P-type impurity ions and an ion implantation energy, thereby forming a P-well in the silicon substrate and an inner P-well in the N-well. Thus, a triple well is formed.
Description
METHOD FOR FABRICATING SEMICONDUCTOR DEVICES HAVING TRIPLE WELLS
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method for fabricating semiconductor devices, and more particularly to a method for fabricating a semiconductor device, in which a triple well is formed using two masks upon forming transistors of a memory device, thereby achieving simplification in the fabrication processes and obtaining stabilized characteristics of the semiconductor device.
Description of the Prior Art
The recent trend to fabricate highly integrated semiconductor devices results in a requirement of a semiconductor device which is operative independently of the potential of an associated semiconductor substrate. To this end, a semiconductor substrate including a plurality of wells having a triple well structure in which each well has an inner well having a type different therefrom is required.
Such a triple well is formed by use of an ion implantation device using high ion implantation energy. Since N and P-wells of the triple well exhibit retrograde well characteristics, the triple well structure is problematic in that it is difficult to obtain a stable PMOS characteristic in the N-well. In the case of a diffused triple well formation process, it is complex because a drive-in process is required for both N and P-wells. Furthermore, in this case, it is difficult to achieve an easy profile control for inner P-wells (R-wells) formed in N-well regions.
In order to form such a triple well, three masks are used in accordance with conventional methods. In other words, the conventional methods have an inconvenience in that an additional mask should be used to form an inner P-well in the N-well.
SUMMARY OF THE INVENTION
Therefore, an object of the invention is to solve the abovementioned problems involved in the conventional methods and to provide a method for forming a triple well, wherein N-type impurity ions are driven in a substrate upon forming a field oxide film, so that it is unnecessary to use a separate drive-in process, thereby simplifying the overall process.
Another object of the invention is to provide a method for forming a triple well, wherein sequential ion implantation steps are carried out at appropriate doping concentrations and ion implantation energy levels, respectively, so that wells of a triple well structure, namely, a P-well, an N-well and an R-well, having appropriate characteristics are formed.
In accordance with one aspect, the present invention provides a method for fabricating a semiconductor device having a triple well, comprising the steps of: forming an element isolation mask on a P-type silicon substrate; forming an N-well mask on the element isolation mask; implanting N-type impurity ions in an exposed portion of the semiconductor substrate, thereby forming an N-well implant region; removing the N-well mask, and oxidizing a portion of the silicon substrate corresponding to a field region while simultaneously driving the N-type impurity ions of the N-well implant region into the semiconductor substrate in accordance with a thermal oxidation process, thereby forming a field oxide film and a diffused N-well; forming a P-well mask on the silicon substrate on which the element isolation mask is left; and implanting P-type impurity ions in an exposed portion of the silicon substrate while varying a concentration of the P-type impurity ions and an ion implantation energy, thereby forming a P-well in the silicon substrate and an inner P-well in the N-well.
In accordance with another aspect, the present invention provides a method for fabricating a semiconductor device having a triple well, comprising the steps of: forming an element isolation mask on a P-type silicon substrate; forming an N-well mask on the element isolation mask; implanting N-type impurity ions in an exposed portion of the semiconductor substrate, thereby forming an
N-well implant region; implanting P-type impurity ions in an exposed portion of the semiconductor substrate, thereby forming a
P-channel stop implant region; removing the N-well mask, and oxidizing a portion of the silicon substrate corresponding to a field region while simultaneously driving the N-type impurity ions of the N-well implant region into the semiconductor substrate in accordance with a thermal oxidation process, thereby forming a field oxide film and a diffused N-well; forming a P-well mask on the silicon substrate; implanting P-type impurity ions in an exposed portion of the silicon substrate and in the N-well region, thereby forming a P-well region and an R-well region; implanting Ptype impurity ions in the exposed portion of the silicon substrate, thereby forming an inner well implant region deeper than the P and
R-well regions; implanting P-type impurity ions in the exposed portion of the silicon substrate, thereby forming an N-channel deep implant region deeper than the inner well implant region; and implanting P-type impurity ions in the exposed portion of the silicon substrate, thereby forming an N-channel threshold implant region deeper than the N-channel deep implant region.
In accordance with the present invention, N-type impurity ions are implanted in a silicon substrate formed with an element isolation mask, by use of an N-well mask. After the implantation of the N-type impurity ions, a field oxide film is grown.
Accordingly, there is an advantage in that the characteristic of a diffused N-well characteristic is obtained without using any separate N-well drive-in process. It is also possible to obtain the characteristic of a high energy well associated with an NMOS by implanting impurity ions at high energy by use of a P-well mask to simultaneously form P and R-wells.
In other words, three kinds of wells, namely, an N-well, a Pwell and an R-well, are simultaneously formed using two masks in accordance with a high energy ion implantation method. The N-well formation process is carried out before the field oxidation process so that the N-well has a diffused well characteristic after the field oxidation process. Using a P-well mask, the P and R-wells are then formed.
Since the formation of the P and R-wells involves no drive-in process, the P and R-wells have a high energy well characteristic.
Accordingly, the overall process is simplified. Furthermore, the
N-well has a diffused well characteristic whereas the P and R-wells have a high energy well characteristic.
BRIEF DESCRIPTION OF THE DRAWINGS
Other objects and aspects of the invention will become apparent from the following description of embodiments with reference to the accompanying drawings in which:
FIGS. 1 to 4 are sectional views respectively illustrating sequential steps of a method for forming a triple well in a semiconductor substrate in accordance with the present invention.
FIG. 5 is a graph depicting a doping profile of the structure obtained after the formation of a triple well according to an embodiment of the present invention, which doping profile is expected along the depth of the silicon substrate;
FIG. 6 is a graph depicting a doping profile of the structure obtained after the formation of a triple well while controlling the concentration of phosphorous ions and ion implantation energy without carrying out a P-well implant and inner well implant processes, in accordance with another embodiment of the present invention, which profile is expected along the depth of the silicon substrate.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIGS. 1 to 4 are sectional views respectively illustrating sequential steps of a method for forming a triple well in a semiconductor substrate in accordance with the present invention.
In accordance with this method, a pad oxide film 2 and a nitride film 3 are first laminated over a P-type silicon substrate 1, as shown in FIG. 1. The pad oxide film 2 and nitride film 3 are partially removed at their portions disposed at a field region, in accordance with a lithography process using a mask and an etching process, thereby forming an element isolation mask 30.
Thereafter, a photoresist film is coated over the resulting structure of FIG. 1 and then exposed to light while using an N-well formation mask, as shown in FIG. 2. The photoresist film is then developed, thereby forming a photoresist film pattern constituting an N-well mask 4. Subsequently, N-type impurity ions are implanted in the silicon substrate 1, thereby forming an N-well implant region 5. The N-type impurity ions have ion implantation energy allowing the impurity ions to pass through the element isolation mask 30 while preventing the impurity ions from passing through the
N-well mask 4. Using the element isolation mask 30, P-type impurity ions are subsequently implanted in the exposed portion of the silicon substrate 1, thereby forming a P-channel stop implant region 6. The P-type impurity ions have ion implantation energy preventing the P-type impurity ions from passing through the element isolation mask 30. The formation of the N-well implant region 5 is carried out under the condition in which phosphorous ions (P31) are implanted in a dose of 1 to 2E13cm-2 using energy of 1.5 to 2 MeV. The formation of the P-channel stop implant region 6 is carried out under the condition in which phosphorous ions are implanted in a dose of 4.5 to 5.5El2cm2 using energy of 200 to 400
KeV.
Thereafter, the photoresist film used as the N-well mask 4 is completely removed. The resulting structure is then subjected to a thermal oxidation process at a temperature of, for example, 1,000 to 1,2000C for 20 to 50 minutes, thereby forming a field oxide film 7 as shown in FIG. 3. In the process of forming the field oxide film 7, the N-type impurity ions implanted in the N-well implant region 5 are diffused into the substrate 1. As a result, the resulting structure has a profile having a diffused N-well 8.
Subsequently, a photoresist film is coated over the entire exposed surface of the resulting structure and then exposed to light while using a P-well formation mask. The photoresist film is then developed, thereby removing its portion corresponding to a P-well region. Accordingly, a P-well mask 18 is formed. Subsequently, Ptype impurity ions, for example, boron ions (Bll), are implanted in the exposed portion of the silicon substrate 1 in a dose of 2 to 3El3cm~2 at energy of 400 to 500 KeV, thereby simultaneously forming a P-well implant region 9 and an R-well implant region 10. Boron ions are further implanted in both the P and R-well implant regions 9 and 10 in a dose of 1 to 2El3cm~2 using energy of 200 to 300 KeV, thereby forming an inner well implant region 11. Boron ions are further implanted in both the P and R-well implant regions 9 and 10 in a dose of 4 to 5E13cm-2 using energy of 200 to 300 KeV, thereby forming an N-channel deep implant region 13. Boron ions are further implanted in both the P and R-well implant regions 9 and 10 in a dose of 1.5 to 2El3cm2 using energy of 20 to 30 KeV, thereby forming an N-channel threshold implant region 14.
The inner well implant region 11 serves to obtain a good well characteristic between the P-well and N-channel field stop implant region 14.
In accordance with the present invention, the formation of the
P-wells is achieved by forming P-type implant regions in the N-well 8 and substrate 1 while reducing the concentration of the impurity ions and the ion implantation energy. That is, the method of the present invention involves no drive-in process which is carried out after an implantation of P-type impurity ions, in order to form the
P-wells. As a result, the resulting structure has no diffused Pwell profile. That is, the structure has a high energy implant well characteristic. On the other hand, the profile of the N-well 8 is still maintained because no drive-in process is involved in the subsequent formation of P-wells.
The P-well mask 18 is then removed, as shown in FIG. 4. Thus, a triple well is formed in the silicon substrate 1. As shown in
FIG. 4, the P-wells 15 and R-well 16 have a high energy implant characteristic whereas the N-well 8 has a diffused well characteristic obtained after the formation of the field oxide film 7.
After the removal of the P-well mask 18, the structure may be subjected to an annealing process at a temperature 900 to 1,0000C for 20 to 40 minutes, in order to remove defects generated at the
P-wells 15 and R-well 16 upon implanting impurity ions. Boron ions may also be implanted in the structure in a blanket threshold implant manner in a dose of 1 to 2El2cm~2 at energy of 20 to 30 KeV, in order to achieve an improvement in the doping profile.
Even though the N-channel threshold implant and blanket threshold implant processes are not carried out, the same effect can be obtained by a boron implantation in a dose of 2 to 4El3cm~2 at energy of 20 to 30 KeV. In this case, both the PMOS and NMOS characteristics can be controlled at one time.
Although the P-well implant and inner well implant processes are not carried out in a separate manner, the same characteristics can be obtained by a boron implantation carried out in a dose of 2 to 4El3cm2 using energy of 200 to 400 KeV upon carrying out the Pwell implant process. In this case, the entire process is simplified.
FIG. 5 illustrates a doping profile of the structure obtained after the formation of the triple well according to an embodiment of the present invention, which doping profile is expected along the depth of the silicon substrate. That is, FIG. 5 shows doping profiles of the R-well implant region 10, inner well implant region 11, N-channel deep implant region 13, and N-channel threshold implant region 14.
FIG. 6 illustrates a doping profile of the structure obtained after a boron implantation in a dose of 2 to 4E13cm-2 at an energy level of 200 to 400 KeV without carrying out the N-channel threshold implant and blanket threshold implant processes in accordance with another embodiment of the present invention. That is, FIG. 6 shows doping profiles of the R-well implant region 10,
N-channel deep implant region 13, and N-channel threshold implant region 14.
As apparent from the above description, the present invention provides a method for fabricating a semiconductor device having a triple well structure, in which wells of the triple well structure are simultaneously formed using two masks. In order to achieve an improvement in the PMOS characteristic of an N-well in the case involving an ion implantation at a high energy level, a field oxidation process is carried out after an N-well implant process.
In this case, a well drive-in effect is also obtained.
In accordance with the present invention, a doping profile, in which three kinds of wells, namely, an N-well, a P-well and an Rwell exhibit appropriate characteristics, is obtained.
Accordingly, it is possible to achieve a simplification in the fabrication processes while obtaining stabilized characteristics of the semiconductor device.
Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.
Claims (16)
1. A method for fabricating a semiconductor device having a triple well, comprising the steps of:
forming an element isolation mask on a P-type silicon substrate;
forming an N-well mask on the element isolation mask;
implanting N-type impurity ions in an exposed portion of the semiconductor substrate, thereby forming an N-well implant region;
removing the N-well mask, and oxidizing a portion of the silicon substrate corresponding to a field region while simultaneously driving the N-type impurity ions of the N-well implant region into the semiconductor substrate in accordance with a thermal oxidation process, thereby forming a field oxide film and a diffused N-well;
forming a P-well mask on the silicon substrate on which the element isolation mask is left; and
implanting P-type impurity ions in an exposed portion of the silicon substrate while varying a concentration of the P-type impurity ions and an ion implantation energy, thereby forming a Pwell in the silicon substrate and an inner P-well in the N-well.
2. The method in accordance with Claim 1, wherein the element isolation mask has a multilayer structure consisting of a pad oxide film and a nitride film, which films have no portion corresponding to the field region.
3. The method in accordance with Claim 1, wherein the formation of the N-well implant region is carried out by implanting phosphorous ions in a dose of 1 to 2E13cm-2 at an energy level of 1.5 to 2 MeV.
4. The method in accordance with Claim 1, wherein the formation step of the P-well and the inner P-well comprises the steps of:
implanting P-type impurity ions in a dose of 2 to 3E13cm~2 at an energy level of 400 to 500 KeV;
implanting P-type impurity ions in a dose of 1 to 2E13cm~2 at an energy level of 200 to 300 KeV; and
implanting P-type impurity ions in a dose of 4 to 5E12cm~2 at an energy level of 80 to 200 KeV.
5. A method for fabricating a semiconductor device having a triple well, comprising the steps of:
forming an element isolation mask on a P-type silicon substrate;
forming an N-well mask on the element isolation mask;
implanting N-type impurity ions in an exposed portion of the semiconductor substrate, thereby forming an N-well implant region;
implanting P-type impurity ions in an exposed portion of the semiconductor substrate, thereby forming a P-channel stop implant region;
removing the N-well mask, and oxidizing a portion of the silicon substrate corresponding to a field region while simultaneously driving the N-type impurity ions of the N-well implant region into the semiconductor substrate in accordance with a thermal oxidation process, thereby forming a field oxide film and a diffused N-well;
forming a P-well mask on the silicon substrate;
implanting P-type impurity ions in an exposed portion of the silicon substrate and in the N-well region, thereby forming a Pwell region and an R-well region;
implanting P-type impurity ions in the exposed portion of the silicon substrate, thereby forming an inner well implant region deeper than the P and R-well regions;
implanting P-type impurity ions in the exposed portion of the silicon substrate, thereby forming an N-channel deep implant region deeper than the inner well implant region; and
implanting P-type impurity ions in the exposed portion of the silicon substrate, thereby forming an N-channel threshold implant region deeper than the N-channel deep implant region.
6. The method in accordance with Claim 5, wherein the element isolation mask has a multilayer structure consisting of a pad oxide film and a nitride film.
7. The method in accordance with Claim 5, wherein the formation of the N-well implant region is carried out by implanting phosphorous ions in a dose of 1 to 2E13cm~2 at an energy level of 1.5 to 2 MeV.
8. The method in accordance with Claim 5, wherein the formation of the P-channel stop implant region is carried out by implanting phosphorous ions in a dose of 4 to 6E12cm~2 at an energy level of 200 to 300 KeV.
9. The method in accordance with Claim 5, wherein the formation of the inner well implant region is carried out by implanting boron ions in a dose of 4 to 5E12cm~2 at an energy level of 200 to 300
KeV.
10. The method in accordance with Claim 5, wherein the formation of the N-channel deep implant region is carried out by implanting boron ions in a dose of 4 to 5E12cm~2 at an energy level of 80 to 200 KeV.
11. The method in accordance with Claim 5, wherein the formation of the N-channel threshold implant region is carried out by implanting boron ions in a dose of 1 to 2El2cm-2 at an energy level of 20 to 30 KeV.
12. The method in accordance with Claim 5, further comprising the step of annealing the resulting structure obtained after the formation of the N-channel threshold implant region at a temperature of 900 to 1, 0000C for 20 to 40 minutes, thereby removing defects formed during the implant steps.
13. The method in accordance with Claim 5, wherein further comprising the steps of removing the P-well mask after the formation of the N-channel threshold implant region, and implanting boron ions in the resulting structure in a blanket threshold implant manner in a dose of 1 to 3.0El2cm2 at an energy level of 20 to 30 KeV.
14. A method for fabricating a semiconductor device having a triple well, comprising the steps of:
forming an element isolation mask on a P-type silicon substrate;
forming an N-well mask on the element isolation mask;
implanting N-type impurity ions in an exposed portion of the semiconductor substrate, thereby forming an N-well implant region;
implanting P-type impurity ions in an exposed portion of the semiconductor substrate, thereby forming a P-channel stop implant region;
removing the N-well mask, and oxidizing a portion of the silicon substrate corresponding to a field region while simultaneously driving the N-type impurity ions of the N-well implant region into the semiconductor substrate in accordance with a thermal oxidation process, thereby forming a field oxide film and a diffused N-well;
forming a P-well mask on the silicon substrate;
implanting P-type impurity ions in an exposed portion of the silicon substrate and in the N-well region, thereby forming a Pwell region in the silicon substrate and an inner P-well region in the N-well;
implanting P-type impurity ions in the exposed portion of the silicon substrate, thereby forming an N-channel deep implant region deeper than the P-well region;
removing the P-well mask, implanting P-type impurity ions in an exposed portion of the silicon substrate, thereby forming a blanket threshold implant region deeper than the N-channel deep implant region.
15. The method in accordance with Claim 14, wherein the formation of the P-well and the inner P-well is carried out by implanting boron ions in a dose of 2 to 4.0E12cm-2 at an energy level of 200 to 400 KeV.
16. The method in accordance with Claim 5, wherein the formation of the blanket threshold implant region is carried out by implanting boron ions in a dose of 2 to 4E12cm~2 at an energy level of 20 to 30 KeV.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960080269A KR100220954B1 (en) | 1996-12-31 | 1996-12-31 | Manufacturing method of semiconductor device having a triple well |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9722437D0 GB9722437D0 (en) | 1997-12-24 |
| GB2320802A true GB2320802A (en) | 1998-07-01 |
| GB2320802B GB2320802B (en) | 2002-01-30 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9722437A Expired - Fee Related GB2320802B (en) | 1996-12-31 | 1997-10-23 | Method for fabricating semiconductor devices having triple wells |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP2998730B2 (en) |
| KR (1) | KR100220954B1 (en) |
| GB (1) | GB2320802B (en) |
| TW (1) | TW356559B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6255153B1 (en) * | 1997-12-30 | 2001-07-03 | Hyundai Electronics Industries Co., Ltd. | Method of manufacturing a semiconductor device |
| WO2013164210A1 (en) | 2012-05-02 | 2013-11-07 | Elmos Semiconductor Ag | Pmos transistor having low threshold voltage and method for the production thereof |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100465606B1 (en) * | 1998-06-30 | 2005-04-06 | 주식회사 하이닉스반도체 | Triple well manufacturing method of semiconductor device |
| KR100524465B1 (en) * | 2003-06-30 | 2005-10-26 | 주식회사 하이닉스반도체 | Method of manufacturing in semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5397734A (en) * | 1991-10-08 | 1995-03-14 | Sharp Kabushiki Kaisha | Method of fabricating a semiconductor device having a triple well structure |
| US5702988A (en) * | 1996-05-02 | 1997-12-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Blending integrated circuit technology |
-
1996
- 1996-12-31 KR KR1019960080269A patent/KR100220954B1/en not_active IP Right Cessation
-
1997
- 1997-10-17 TW TW086115298A patent/TW356559B/en not_active IP Right Cessation
- 1997-10-23 GB GB9722437A patent/GB2320802B/en not_active Expired - Fee Related
- 1997-12-15 JP JP9362537A patent/JP2998730B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5397734A (en) * | 1991-10-08 | 1995-03-14 | Sharp Kabushiki Kaisha | Method of fabricating a semiconductor device having a triple well structure |
| US5702988A (en) * | 1996-05-02 | 1997-12-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Blending integrated circuit technology |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6255153B1 (en) * | 1997-12-30 | 2001-07-03 | Hyundai Electronics Industries Co., Ltd. | Method of manufacturing a semiconductor device |
| WO2013164210A1 (en) | 2012-05-02 | 2013-11-07 | Elmos Semiconductor Ag | Pmos transistor having low threshold voltage and method for the production thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9722437D0 (en) | 1997-12-24 |
| TW356559B (en) | 1999-04-21 |
| JPH10209295A (en) | 1998-08-07 |
| GB2320802B (en) | 2002-01-30 |
| KR19980060901A (en) | 1998-10-07 |
| KR100220954B1 (en) | 1999-09-15 |
| JP2998730B2 (en) | 2000-01-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20101023 |