KR19980060901A - Method of manufacturing a semiconductor device having a triple well - Google Patents
Method of manufacturing a semiconductor device having a triple well Download PDFInfo
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- KR19980060901A KR19980060901A KR1019960080269A KR19960080269A KR19980060901A KR 19980060901 A KR19980060901 A KR 19980060901A KR 1019960080269 A KR1019960080269 A KR 1019960080269A KR 19960080269 A KR19960080269 A KR 19960080269A KR 19980060901 A KR19980060901 A KR 19980060901A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
Abstract
본 발명은 반도체소자 제조방법에 관한 것으로, 메모리 소자의 트랜지스터 형성할때 2개의 마스크로 3중 웰(well)을 형성하여 공정의 단순화와 더불어 안정화된 특성을 갖도록 하는 공정방법이다. 즉, 공정의 단순화를 이루기 위해 소자분리마스크 공정으로 실리콘 기판상에 질화막 패턴을 형성한다음, N-웰 임플란트를 주입하고, 열산화 공정으로 필드 산화막을 형성하는 동시에 상기 N-웰 임플란트를 드라이브 인시켜 확산된 P-웰을 형성하고, P-웰 마스크로 고 에너지 이온주입공정으로 P-웰과 R-웰(N-웰영역에 형성되는 P-웰을 의미함)을 동시에 형성하여 3중 웰을 형성하는 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and to forming a triple well with two masks when forming a transistor of a memory device. That is, in order to simplify the process, a nitride film pattern is formed on a silicon substrate by a device isolation mask process, an N-well implant is implanted, and a field oxide film is formed by a thermal oxidation process, and at the same time, the N-well implant is driven in. To form a diffused P-well, and simultaneously form a P-well and an R-well (meaning a P-well formed in an N-well region) by a high energy ion implantation process using a P-well mask. To form.
Description
본 발명은 반도체소자 제조방법에 관한것으로, 특히 메모리 소자의 트랜지스터 형성할때 2개의 마스크로 3중 웰(well)을 형성하여 공정의 단순화와 더불어 안정화된 특성을 갖도록 하는 반도체소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having a stabilized and stable characteristic by forming a triple well with two masks when forming a transistor of a memory device. .
반도체소자가 고집적화됨에 따라 반도체 기판의 전위와는 별개로 동작되는 반도체소자의 필요성이 대두되었고, 그 결과 반도체 기판에 다수의 웰을 형성하면서 웰 내부에 또다른 타입의 웰이 구비된 3중 웰을 형성하게 되었다.As semiconductor devices have been highly integrated, there is a need for semiconductor devices that operate independently of the potential of the semiconductor substrate. As a result, a triple well having another type of well inside the well is formed while forming a plurality of wells in the semiconductor substrate. Formed.
한편, 고 에너지를 이용한 이온주입 공정으로 3중 웰을 형성하는 공정은 N-웰과 P-웰 모두 반대의 웰(Retrograde well) 특성을 가지는 바, N-웰에 형성되는 P MOS 특성의 안정화가 어려운 과제였다. 그리고 확산된 3중 웰(Diffused Triple well) 공정의 경우에는 N-웰과 P-웰 모두 드라이브 - 인 공정이 필요하기 때문에 공정이 복잡하고 특히 R-웰(N-웰영역에 형성되는 P-웰을 의미함)의 프로파일 조절(profile control)이 용이하지 않다는 단점이 있다.On the other hand, the process of forming a triple well by the ion implantation process using a high energy has the opposite well (Retrograde well) characteristics of both N-well and P-well, the stabilization of the P MOS characteristics formed in the N-well It was a difficult task. In the case of the diffused triple well process, since both the N-well and the P-well require a drive-in process, the process is complicated and in particular, an R-well (P-well formed in the N-well region). Profile control) is not easy.
본 발명은 상기한 문제점을 해결하기 위하여 소자분리 공정으로 질화막 패턴을 형성한다음, N-웰을 형성하고, 산화 공정으로 필드 산화막을 형성한 다음, P-웰 마스크를 써서 P-웰과 R-웰을 동시에 고 에너지 이온주입하여 3중 웰을 형성하는 반도체소자 제조방법을 제공하는데 그 목적이 있다.In order to solve the above problems, the present invention forms a nitride film pattern by an isolation process, and then forms an N-well, forms a field oxide film by an oxidation process, and then uses a P-well mask to form a P-well and an R-. It is an object of the present invention to provide a method for manufacturing a semiconductor device in which the wells are simultaneously implanted with high energy ions to form triple wells.
도 1 내지 도4는 본 발명에 의해 반도체 기판에 3중 웰을 형성하는 단계를 도시한 단면도이다.1 to 4 are cross-sectional views illustrating the step of forming a triple well in a semiconductor substrate according to the present invention.
도5는 본 발명에 의해 3중 웰을 형성한 다음 실리콘 깊이에 따라 예상되는 도핑 프로파일을 도시한 것이다.Figure 5 illustrates the anticipated doping profile depending on the silicon depth after forming a triple well by the present invention.
도6는 P-웰 임플란트와 내부 웰 임플란트를 별도로 하지 않은 경우에 실리콘 깊이에 따라 예상되는 도핑 프로파일을 도시한 것이다.FIG. 6 shows the anticipated doping profiles depending on silicon depth when the P-well implant and the internal well implant are not separately.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1 ; 실리콘 기판2 ; 패드 산화막One ; Silicon substrate 2; Pad oxide
3 ; 질화막4 ; 감광막 패턴3; Nitride film 4; Photoresist pattern
5 ; N-웰 임플란트 영역5; N-well implant area
6 ; P형 채널 스톱 임플란트 영역6; P-type channel stop implant area
7 ; 필드 산화막8 ; N-웰7; Field oxide film 8; N-well
9 ; P-웰 임플란트 영역10 ; R-웰 임플란트 영역9; P-well implant region 10; R-well implant area
11 ; 내부 웰 임플란트 영역11; Internal Well Implant Area
13 ; N-채널 디프 임플란트 영역13; N-channel deep implant area
14 ; N-채널 쓰레쉬홀드 임플란트 영역14; N-Channel Threshold Implant Area
15 ; N-웰16 ; R-웰15; N-well 16; R-well
상기 목적을 달성하기 위한 본 발명은 3중 웰을 갖는 반도체 소자 제조 방법에 있어서,The present invention for achieving the above object is a semiconductor device manufacturing method having a triple well,
P형 실리콘 기판상에 소자분리 마스크를 형성하는 단계와,Forming an isolation mask on the P-type silicon substrate;
상기 소자분리 마스크 상부에 N-웰 마스크를 형성하는 단계와,Forming an N-well mask on the device isolation mask;
N-형 불순물을 노출된 실리콘 기판으로 주입하여 N-웰 임플란트 영역을 형성하는 단계와,Implanting N-type impurities into the exposed silicon substrate to form an N-well implant region;
P형 불순물을 이온주입하여 P 채널 스톱 임플란트 영역을 형성하는 단계와,Ion implanting P-type impurities to form a P-channel stop implant region;
상기 N-웰 마스크를 제거한 다음, 열산화 공정으로 필드 영역의 실리콘 기판을 필드 산화막을 형성하는 동시에 상기 N-웰 이온을 기판 내부로 드라이브 인시켜 확산된 N-웰을 형성하는 단계와,Removing the N-well mask and then thermally oxidizing the silicon substrate in the field region to form a field oxide film and simultaneously driving in the N-well ions into the substrate to form a diffused N-well;
상기 실리콘 기판 상부에 P-웰 마스크를 형성하는 단계와,Forming a P-well mask on the silicon substrate;
노출된 실리콘 기판과 상기 N-웰 영역으로 P 형 불순물을 이온 주입하여 P-웰 영역과 R-웰 영역을 형성하는 단계를 포함한다.Ion implanting P-type impurities into the exposed silicon substrate and the N-well region to form a P-well region and an R-well region.
상기한 목적을 달성하기 위한 본 발명의 다른 실시예는 반도체 소자 제조방법에 있어서,Another embodiment of the present invention for achieving the above object is a semiconductor device manufacturing method,
P형 실리콘 기판상에 소자분리 마스크를 형성하는 단계와,Forming an isolation mask on the P-type silicon substrate;
상기 소자분리 마스크 상부에 N-웰 마스크를 형성하는 단계와,Forming an N-well mask on the device isolation mask;
N-형 불순물을 노출된 실리콘 기판으로 주입하여 N-웰 임플란트 영역을 형성하는 단계와,Implanting N-type impurities into the exposed silicon substrate to form an N-well implant region;
P형 불순물을 이온주입하여 P 채널 임플란트 영역을 형성하는 단계와,Ion implanting P-type impurities to form a P-channel implant region,
상기 N-웰 마스크를 제거한 다음, 열산화 공정으로 필드 영역의 실리콘 기판을 필드 산화막을 형성하는 동시에 상기 N-웰 이온을 기판 내부로 드라이브 인시켜 확산된 N-웰을 형성하는 단계와,Removing the N-well mask and then thermally oxidizing the silicon substrate in the field region to form a field oxide film and simultaneously driving in the N-well ions into the substrate to form a diffused N-well;
상기 실리콘 기판 상부에 P-웰 마스크를 형성하는 단계와,Forming a P-well mask on the silicon substrate;
노출된 실리콘 기판과 상기 N-웰 영역으로 P 형 불순물을 이온 주입하여 P-웰 영역과 R-웰 영역을 형성하는 단계와,Ion implanting P-type impurities into the exposed silicon substrate and the N-well region to form a P-well region and an R-well region;
내부 웰 임플란트를 노출된 기판으로 주입하여 단계와,Injecting an internal well implant into an exposed substrate,
N-채널 디프 임플란트를 주입하는 단계와,Injecting an N-channel deep implant,
N-채널 쓰레쉬홀드 임플란트를 주입하는 단계를 포함한다.Injecting an N-channel threshold implant.
본 발명에서는 소자분리 마스크를 형성후 먼저 N-웰을 형성하고 필드 산화막을 성장시킴으로써 별도의 N-웰 드라이브-인 공정이 필요하지 않으면서도 확산된 N-웰 특성을 갖도록 하는 장점을 가지고 있다. 또한, P-웰 마스크를 써서 P-웰과 R-웰을 동시에 고 에너지로 이온주입함으로써 N MOS는 고 에너지 웰 형성공정의 특성을 가지게 하는 장점이 있다.In the present invention, after forming the device isolation mask, an N-well is first formed and a field oxide layer is grown to have diffused N-well characteristics without a separate N-well drive-in process. In addition, by using a P-well mask to ion implant the P-well and the R-well at high energy simultaneously, the N MOS has the advantage of having characteristics of a high energy well forming process.
즉, 고 에너지 이온 주입방법에 의해 3종류의 웰, 즉 N-웰, P-웰, R-웰을 2개의 마스크로 동시에 형성하면서, N-웰 공정을 필드 산화(Field Oxidation)전에 실시함으로써 필드 산화공정후에는 N-웰이 확산된 웰 특성을 갖도록 한 다음 P-웰 마스크를 써서 P-웰과 R-웰을 동시에 형성한다.In other words, by using a high energy ion implantation method, three types of wells, namely N-wells, P-wells, and R-wells, are simultaneously formed with two masks, and the N-well process is performed before field oxidation. After the oxidation process, the N-well has diffused well characteristics, and then a P-well and an R-well are simultaneously formed using a P-well mask.
이때는 별도의 드라이브-인 공정이 없으므로 P-웰과 R-웰은 고 에너지 웰 특성을 가지게 되며, 그로인해 공정단순화와 더불어 N-웰은 확산된 웰 특성을 가지며, P-웰, R-웰은 고 에너지 웰 특성을 갖도록 만들 수 있다.In this case, since there is no separate drive-in process, the P-well and R-well have high energy well characteristics. Therefore, in addition to the process simplification, the N-well has diffused well characteristics, and the P-well and R-well have It can be made to have high energy well characteristics.
상술한 목적 및 특징들, 장점은 첨부된 도면과 관련한 다음의 상세한 설명을 통하여 보다 분명해 질 것이다. 이하 첨부된 도면을 참조하여 본 발명의 실시예를 상세히 설명하면 다음과 같다.The above objects, features, and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도1 내지 도4는 본 발명에 의해 반도체 기판에 3중 웰을 형성하는 단계를 도시한 단면도이다.1 to 4 are cross-sectional views illustrating the steps of forming a triple well in a semiconductor substrate according to the present invention.
도1은 P형 실리콘 기판(1)상에 패드 산화막(2)과 질화막(3)을 적층하고, 소자분리 마스크로 식각공정으로 필드 영역의 질화막(3)과 패드 산화막(2)을 제거한 것을 도시한 단면도이다.FIG. 1 shows that the pad oxide film 2 and the nitride film 3 are laminated on the P-type silicon substrate 1, and the nitride film 3 and the pad oxide film 2 in the field region are removed by an etching process using an element isolation mask. One cross section.
도2는 전체적으로 감광막을 도포한다음, N-웰 마스크로 노광 및 현상공정으로 감광막 패턴(4)을 형성하고, 고 에너지 이온 주입방법을 이용하여 N-형 불순물을 노출된 실리콘 기판(1)으로 주입하여 N-웰 임플란트 영역(5)을 형성하고, 계속하여 P형 불순물을 이온주입하여 P 채널 스톱 임플란트 영역(6)을 형성한 단면도로서, 상기 N-웰 임플란트 영역(5)은 주입할때 조건은 예를들어 인(P31)을 1-2E13 도즈량과 1.5-2MeV의 에너지로 주입한다. 그리고, 상기 P 채널 스톱 임플란트 영역(6)은 상기 질화막 패턴(3)을 임플란트 베리어로 이용하여 상기 인을 4.5-5.5E12 도즈량과 200-400KeV 에너지로 주입한다.Fig. 2 is applied to the entire photoresist film, and then the photoresist pattern 4 is formed by exposure and development with an N-well mask, and the N-type impurities are exposed to the silicon substrate 1 by using a high energy ion implantation method. A cross-sectional view of implanting the N-well implant region 5, followed by ion implantation of P-type impurities to form the P channel stop implant region 6, wherein the N-well implant region 5 is implanted. The condition is, for example, injecting phosphorus (P31) with an amount of 1-2E13 dose and energy of 1.5-2MeV. The P-channel stop implant region 6 injects the phosphorus at 4.5-5.5E12 dose and 200-400 KeV energy using the nitride film pattern 3 as an implant barrier.
도3은 상기 N-웰 마스크로 이용된 감광막(4)을 제거한다음, 필드 산화막을 제조하기 위한 예를들어 1100℃의 온도에서 30분 정도로 열산화 공정을 실시하여 필드 산화막(7)을 형성한다. 상기 필드 산화막(7)을 형성하는 공정에서 상기 N-웰 임플란트 영역(5)은 기판 내부로 확산되어 확산된 N-웰(8)프로파일을 갖게 된다. 그리고, 상기 공정후 감광막을 전체적으로 도포하고, P-웰 마스크로 노광 및 현상 공정으로 P-웰영역으로 예정된 지역의 감광막을 제거한 감광막 패턴(18)을 형성한다음, 노출된 실리콘 기판(1)으로 P형 불순물을 이온 주입하여 P-웰 임플란트 영역(9)과 R-웰 임플란트 영역(10)을 동시에 형성하는데 이때는 붕소(B11)를 2-3E13의 도즈량과 400-500KeV에너지로 주입한다. 그리고, 붕소를 1-2E13 도즈량과 200-300KeV의 에너지로 주입하여 내부 웰 임플란트 영역(11)을 형성하고, 붕소를 4-5E12의 도즈량과 80-200KeV의 에너지로 주입하여 N-채널 디프 임플란트 영역(13)을 형성하고, N-채널 쓰레쉬홀드 임플란트를 주입하여 N-채널 쓰레쉬홀드 임플란트 영역(14)을 형성한 단면도이다.Fig. 3 removes the photoresist film 4 used as the N-well mask, and then performs a thermal oxidation process at a temperature of 1100 ° C. for about 30 minutes to form a field oxide film, thereby forming a field oxide film 7. . In the process of forming the field oxide film 7, the N-well implant region 5 has an N-well 8 profile diffused into the substrate. After the process, the photoresist film is applied as a whole, and a photoresist pattern 18 is formed by removing the photoresist film in a region designated as a P-well region by an exposure and development process using a P-well mask, and then exposed to the exposed silicon substrate 1. P-type impurities are ion implanted to form the P-well implant region 9 and the R-well implant region 10 at the same time. In this case, boron (B11) is implanted at a dose of 2-3E13 and 400-500 KeV energy. In addition, boron is injected at an dose of 1-2E13 and energy of 200-300 KeV to form an internal well implant region 11, and boron is injected at an dose of 4-5E12 and energy of 80-200KeV to form an N-channel deep. The implant region 13 is formed, and the N-channel threshold implant region 14 is formed by implanting the N-channel threshold implant.
상기 내부 웰 임플란트 영역(11)은 P-웰과 N-채널 필드 스톱 임플란트영역사이의 웰 특성을 좋게 하기 위해 형성하는 것이다.The inner well implant region 11 is formed to improve the well characteristics between the P-well and the N-channel field stop implant region.
도4는 상기 감광막 패턴(18)과 상기 질화막(3), 패드 산화막(2)을 제거한 다음, 실리콘 기판에 3중 웰이 형성된 것을 도시한 단면도로서, 상기 P-웰(15)과 R-웰(16)은 고 에너지 임플란트 웰 특성을 가지지만 N-웰(8)의 경우에는 필드 산화막(7) 형성공정을 거치면서 확산된 웰 특성을 갖게 된다.FIG. 4 is a cross-sectional view illustrating that a triple well is formed on a silicon substrate after removing the photosensitive film pattern 18, the nitride film 3, and the pad oxide film 2, and the P-well 15 and the R-well. 16 has a high energy implant well characteristic, but in the case of the N-well 8, it has a well characteristic diffused through the process of forming the field oxide film 7.
참고로, 상기 감광막 패턴(18)과 상기 질화막(3), 패드 산화막(2)을 제거한 다음 900-1000℃에서 20-40분 어닐링 공정을 실시하여 상기 P-웰(15)과 R-웰(16)의 임플란트를 기판내부로 드라이브 인 시킨다. 그리고, 다시 전면 쓰레쉬홀드 임플란트로 붕소를 1 내지 1E12 도즈량과 20-30KeV 에너지로 주입할 수 있다. 한편, 상기 N 채널 쓰레쉬홀드 임플란트를 생략하고, P-웰 마스크로 사용되는 감광막 패턴(18)과 상기 질화막(3), 패드 산화막(2)을 제거한 다음, 전년 쓰레쉬홀드 임플란트를 도즈량이 2 내지 4E13의 붕소를 20-30KeV 에너지로 주입할 수 있다.For reference, the photoresist pattern 18, the nitride layer 3, and the pad oxide layer 2 may be removed, and then subjected to an annealing process at 900-1000 ° C. for 20-40 minutes to form the P-well 15 and the R-well ( Drive the implant of 16) into the substrate. Then, boron may be injected again into the front threshold implant at an amount of 1 to 1E12 dose and 20-30 KeV energy. Meanwhile, the N-channel threshold implant is omitted, the photoresist pattern 18 used as the P-well mask, the nitride layer 3, and the pad oxide layer 2 are removed, and the dose amount of the previous year implant implant is 2 To 4E13 boron may be injected at 20-30 KeV energy.
그리고, 상기 P-웰 임플란트와 내부 웰 임플란트를 각각 별도로 진행하지 않고 P-웰 임플란트를 주입할때 붕소의 도즈량이 2 내지 4E13과 200-400KeV 에너지로 주입하여 공정을 간단하게 할 수 있다.In addition, the dosing amount of boron may be injected at 2 to 4E13 and 200 to 400 KeV energy to simplify the process when the P-well implant is injected without separately proceeding the P-well implant and the internal well implant.
도5는 본 발명에 의해 3중 웰을 형성한 다음 실리콘 깊이에 따라 예상되는 도핑 프로파일을 도시한 것으로, 실리콘 기판 내부에서 부터 R-웰 임플란트 영역(10), 내부 웰 임플란트 영역(11), N-채널 디프 임플란트 영역(13) 및 N-채널 쓰레쉬홀드 임플란트 영역(14)의 프로파일을 나타낸다.FIG. 5 illustrates the anticipated doping profile according to the silicon depth following the formation of a triple well by the present invention, from the inside of the silicon substrate to the R-well implant region 10, the inner well implant region 11, N The profiles of the channel deep implant region 13 and the N-channel threshold implant region 14 are shown.
도6는 본 발명의 다른 실시예에 의해 P-웰 임플란트와 내부 웰 임플란트를 별도로 하지 않은 경우의 도핑 프로파일을 도시한 것으로, 실리콘 기판 내부에서 부터 R-웰 임플란트 영역(10), N-채널 디프 일플란트 영역(13) 및 N-채널 쓰레쉬홀드 임플란트 영역(14)의 프로파일을 나타낸다.FIG. 6 shows a doping profile when a P-well implant and an internal well implant are not separately provided according to another embodiment of the present invention. FIG. 6 shows an R-well implant region 10 and an N-channel dip from inside a silicon substrate. Profiles of one implant region 13 and N-channel threshold implant region 14 are shown.
본 발명은 2개의 마스크를 가지고 3중 웰을 동시에 형성하는 공정으로 고 에너지 임플란트 방법으로 이온주입을 하는 경우 N-웰의 PMOS 특성 개선을 위해 N-웰 임플란트 후 필드 산화 공정을 실시하여 웰 드라이브 인 효과를 동시에 얻는다.The present invention is a process of forming a triple well with two masks simultaneously. When ion implantation is performed by a high energy implant method, a field oxidation process is performed after an N-well implant to improve the PMOS characteristics of the N-well. Get the effect at the same time.
또한 전체 공정에서는 세가지 종류의 웰, 즉 N-웰, P-웰, R-웰이 가장 적절한 특성을 갖는 도핑 프로파일을 얻게 됨으로 인하여 전반적은 트랜지스터 특성안정화와 수율 향상을 기대할 수 있다.In the overall process, three types of wells, namely, N-well, P-well, and R-well, have a doping profile having the most appropriate characteristics. Therefore, overall transistor stability and yield improvement can be expected.
아울러 본 발명의 바람직한 실시예들은 예시의 목적을 위해 개시된 것이며, 당업자라면 본 발명의 사상과 범위안에서 다양한 수정, 변경, 부가등이 가능할 것이며, 이러한 수정 변경 등은 이하의 특허 청구의 범위에 속하는 것으로 보아야 할 것이다.In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the following claims You will have to look.
Claims (15)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
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| KR1019960080269A KR100220954B1 (en) | 1996-12-31 | 1996-12-31 | Manufacturing method of semiconductor device having a triple well |
| TW086115298A TW356559B (en) | 1996-12-31 | 1997-10-17 | Method for fabricating semiconductor devices having triple well |
| GB9722437A GB2320802B (en) | 1996-12-31 | 1997-10-23 | Method for fabricating semiconductor devices having triple wells |
| JP9362537A JP2998730B2 (en) | 1996-12-31 | 1997-12-15 | Method for manufacturing semiconductor device having triple well |
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| KR1019960080269A KR100220954B1 (en) | 1996-12-31 | 1996-12-31 | Manufacturing method of semiconductor device having a triple well |
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| KR19980060901A true KR19980060901A (en) | 1998-10-07 |
| KR100220954B1 KR100220954B1 (en) | 1999-09-15 |
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| JP (1) | JP2998730B2 (en) |
| KR (1) | KR100220954B1 (en) |
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| KR100465606B1 (en) * | 1998-06-30 | 2005-04-06 | 주식회사 하이닉스반도체 | Triple well manufacturing method of semiconductor device |
| WO2013164210A1 (en) | 2012-05-02 | 2013-11-07 | Elmos Semiconductor Ag | Pmos transistor having low threshold voltage and method for the production thereof |
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| US5702988A (en) * | 1996-05-02 | 1997-12-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Blending integrated circuit technology |
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| GB9722437D0 (en) | 1997-12-24 |
| GB2320802A (en) | 1998-07-01 |
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| GB2320802B (en) | 2002-01-30 |
| KR100220954B1 (en) | 1999-09-15 |
| JPH10209295A (en) | 1998-08-07 |
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