JP3216110B2 - Method of manufacturing complementary semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a complementary semiconductor device including a high breakdown voltage transistor and a normal breakdown voltage transistor.

[0002]

2. Description of the Related Art A logic circuit section or the like which is usually constituted by a transistor having a high breakdown voltage, and an offset layer for extending a depletion layer is constituted by a transistor having a high breakdown voltage provided between a drain layer and a channel section. Conventionally, when manufacturing a complementary semiconductor device in which a high breakdown voltage portion is integrated, for example, a channel stop layer in a normal breakdown voltage N-channel transistor, an offset layer in a high breakdown voltage P-channel transistor, and a high breakdown voltage The channel stop layer in the N-channel transistor has been formed by the same ion implantation process.

[0003]

However, in the above-described conventional example, first, the impurity concentration of the channel stop layer in the N-channel transistor with a high breakdown voltage and the offset layer of the offset layer in the P-channel transistor with a high breakdown voltage are equal to each other. In principle, it has been impossible in principle to simultaneously increase both the threshold voltage of the parasitic MOS transistor in the element isolation region of the N-channel transistor having a withstand voltage and the drain withstand voltage of the P-channel transistor having a high withstand voltage.

Further, since the impurity concentration of the channel stop layer in the N-channel transistor of the high breakdown voltage and the normal breakdown voltage becomes equal to each other, the threshold voltage of the parasitic MOS transistor in the element isolation region of the N-channel transistor of the high breakdown voltage and the normal breakdown voltage In principle, it has also been impossible in principle to simultaneously increase both the withstand voltage between the drain layer and the channel stop layer in the N-channel transistor.

On the other hand, a channel stop layer in a normal breakdown voltage N-channel transistor, an offset layer in a high breakdown voltage P-channel transistor, and a channel stop layer in a high breakdown voltage N-channel transistor are formed by separate ion implantation, respectively. There is also a method of freely setting the impurity concentration of. However, in this method, not only the ion implantation step but also the photolithography step increases. Therefore, with the conventional method, a highly reliable complementary semiconductor device cannot be manufactured without increasing the manufacturing cost.

[0006]

According to a method of manufacturing a complementary semiconductor device according to the present invention, an offset layer 43 having a lower impurity concentration than the drain layer 64 is provided between a drain layer 64 and a channel portion. Withstand voltage transistor 73
And a method of manufacturing a complementary semiconductor device including normal breakdown voltage transistors 71 and 72 not provided with the offset layer 43.
Channel stop layers 21, 22, 2 in 1, 73
At the same time as introducing impurities of the second conductivity type into the first region where the fourth and fourth regions are to be formed, the channel stop layers 41 and 42 of the second conductivity type channel transistor 72 having a normal breakdown voltage are used.
Introducing the second conductivity type impurity into the second region where the offset layer 43 is to be formed in the second region where the offset layer 43 is to be formed in the high breakdown voltage first conductivity type channel transistor 73; At the same time as introducing the first conductivity type impurity 32 into the fourth region where the channel stop layers 33 and 34 of the withstand voltage second conductivity type channel transistor 74 are to be formed, the first conductivity type impurity is introduced into the second and third regions. And introducing a type impurity 32.

[0007]

In the method for manufacturing a complementary semiconductor device according to the present invention, both the first conductivity type impurity 32 and the second conductivity type impurity are introduced into the second and third regions to perform impurity compensation. In contrast, only the first conductivity type impurity 32 is introduced into the fourth region. In addition, the introduction of these impurities causes any of the channel stop layers 21, 22, 24,
26, 33, 34, 41, and 42 are performed simultaneously with the introduction of impurities.

Therefore, without increasing the number of manufacturing steps, the channel stop layers 41 and 42 of the normal breakdown voltage second conductivity type channel transistor 72 and the offset layer 4 of the high breakdown voltage first conductivity type channel transistor 73 are reduced.
3 and the impurity concentration of the channel stop layers 33 and 34 in the high breakdown voltage second conductivity type channel transistor 74 can be relatively increased.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a logic circuit portion composed of transistors with normal breakdown voltage and a high breakdown voltage portion composed of transistors with high breakdown voltage are integrated with each other.
P-channel transistor is LOC
One embodiment of the present invention applied to the manufacture of a complementary semiconductor device in which an OS offset drain type and an N-channel transistor is an offset drain type will be described with reference to FIGS.

In this embodiment, by a conventionally known method,
As shown in FIG. 1, N wells 14 and 15 are first formed in a logic circuit section 12 and a P channel transistor formation region of a high breakdown voltage section 13 in a P type Si substrate 11, and then formed later. An SiN film (not shown) having a reverse pattern to the SiO ₂ film for element isolation is patterned on the surface of the Si substrate 11.

Thereafter, the channel stop layer to be formed in both the P-channel and N-channel transistors of the logic circuit section 12 and the channel stop layer and the offset layer to be formed in the P-channel transistor of the high breakdown voltage section 13 are in reverse patterns. Photoresist (not shown)
Patterning is performed on the iN film.

Thereafter, using this photoresist as a mask, N-type impurities (not shown) are ion-implanted into the Si substrate 11 to form N ⁻ layers 21 to 26 in the N wells 14 and 15. The photoresist is stripped. And Si
After the SiO ₂ film 27 for element isolation is formed by the LOCOS method using the N film as an oxidation prevention mask, the SiN film is removed.

Next, as shown in FIG. 2, a channel stop layer to be formed in the N-channel transistors of both the logic circuit section 12 and the high withstand voltage section 13 and an offset layer to be formed in the P-channel transistor of the high withstand voltage section 13 , And a region between the N wells 14 and 15 is patterned with a photoresist 31 having an inverted pattern. Then, using the photoresist 31 as a mask, a P-type impurity 32 is added to the Si substrate 1.
After the ion implantation into the photoresist 1, the photoresist 31 is stripped.

The dose and acceleration energy for ion implantation of the above-mentioned N-type impurity and P-type impurity 32 are determined by the threshold voltage required for the parasitic MOS transistor in the element isolation region and the impurity concentration in the LOCOS offset layer. Is determined from the relationship between the pressure and the breakdown voltage. For example, as an N-type impurity, phosphorus is ion-implanted at an acceleration energy of 60 keV and a dose of 6 × 10 ¹² cm ⁻² , and as a P-type impurity 32, boron is injected at an acceleration energy of 270 keV and 2 × 10 ^13. Ions are implanted at a dose of cm ^-2 .

As a result, as shown in FIG.
With P layer 33-35 is formed, N ^- layer 22, 24, 32
Impurity compensation is performed on each of the portions 3 and 26 and the entire N ⁻ layer 25 to form the P ⁻ layers 41 to 44. Thereafter, a P-well 45 for forming the N-channel transistor of the logic circuit portion 12 in the N-well 14, SiO ₂ film as a gate oxide film on the surface of the element active region surrounded by the SiO ₂ film 27 46 is formed.

Then, an impurity (not shown) is ion-implanted to control the threshold voltage, and a gate electrode is formed with a polycrystalline Si film 47 or the like, and then N ⁻ layers 51 to 54 are formed.
Further, after forming a side wall made of an insulating film such as the SiO ₂ film 55 on the polycrystalline Si film 47, the P ⁺ layers 61 to 64 and the N
⁺ Layers 65 to 68 are formed. Through the above steps, a P-channel transistor 71 and an N-channel transistor 72 are formed in the logic circuit section 12, and a LOCOS offset drain P-channel transistor 73 and an offset drain N-channel transistor 74 are formed in the high breakdown voltage section 13. I do.

In the above embodiment, ion implantation of an N-type impurity (not shown) for forming the channel stop layers and the like of the P-channel transistors 71 and 73,
Table 1 summarizes the ion implantation of the P-type impurity 32 for forming the channel stop layers and the like of the channel transistors 72 and 74. In Table 1, ○ indicates that ion implantation is performed, and X indicates that ion implantation is not performed.

[0018]

[Table 1]

In the above embodiment, the impurity concentration of the P layers 33 and 34 in the N-channel transistor 74 is
Since the impurity concentrations of the P ⁻ layers 41 to 44 of the channel transistor 72 and the P channel transistor 73 are higher than those of the P ⁻ layers 41 to 44, the threshold voltage of the parasitic MOS transistor in the element isolation region of the N channel transistor 74 is high. For this reason, it is possible to extend a polycrystalline Si wiring (not shown) on the SiO ₂ film 27 on the P layers 33 and 34, and the layout flexibility is large. Therefore, the chip size can be reduced, and the manufacturing cost can be reduced.

Conversely, since the impurity concentration of P ⁻ layer 43 in P channel transistor 73 is lower than that of P layers 33 and 34 in N channel transistor 74, the drain breakdown voltage of P channel transistor 73 is further reduced. Can be higher. Further, the impurity concentration of the P ⁻ layers 41 and 42 in the N-channel transistor 72 is set to
4, the N ⁺ layer 65,
Junction breakdown between the 66 and the P ^- layers 41 and 42 and leakage current can be reduced.

Further, as described above, the impurity concentrations of the P layers 33 and 34 in the N-channel transistor 74 are relatively increased, and the impurity concentrations of the P ⁻ layers 41 to 44 in the N-channel transistor 72 and the P-channel transistor 73 are reduced. Although it is relatively low, in this embodiment, the manufacturing cost is hardly increased because the number of manufacturing steps is not increased by only changing the mask pattern as compared with the conventional example.

In the above-described embodiment, as shown in FIG. 2, after forming the element isolation SiO ₂ film 27, the impurity 32 for forming the channel stop layer is ion-implanted. This is because impurities 3 on the surface of the Si substrate 11 are changed due to a change in the thickness of the formed SiO ₂
This is for suppressing the change of the density of No. 2. But,
Before forming the SiO ₂ film 27, and an SiN film for forming the SiO ₂ film 27 as a mask, in a self-aligning manner impurities 32 may be ion implanted into the isolation region.

In the above-described embodiment, the C
P-channel transistor 7 of MOS transistors
3 is a LOCOS offset drain type and the N-channel transistor 74 is an offset drain type. Conversely, a P-channel transistor is an offset drain type and an N-channel transistor is a LOCOS offset drain type. It is also possible to make all the transistors LOCOS offset drain type.

[0024]

In the method for manufacturing a complementary semiconductor device according to the present invention, the channel stop layer in the second-conductivity-type channel transistor having the normal breakdown voltage and the offset in the first-conductivity-type channel transistor having the high breakdown voltage can be manufactured without increasing the number of manufacturing steps. The impurity concentration of the channel stop layer in the high-breakdown-voltage second-conductivity-type channel transistor can be relatively increased.

For this reason, the withstand voltage between the drain layer and the channel stop layer in the normal withstand voltage transistor is high, and the drain withstand voltage of the high withstand voltage transistor is further higher.
In addition, the threshold voltage of the parasitic MOS transistor in the element isolation region of the high breakdown voltage transistor is high, and a highly reliable complementary semiconductor device can be manufactured with almost no increase in manufacturing cost.

[Brief description of the drawings]

FIG. 1 is a side sectional view showing an initial step of an embodiment of the present invention.

FIG. 2 is a side sectional view showing a middle stage process of one embodiment.

FIG. 3 is a side sectional view showing a final step of the embodiment.

[Explanation of symbols]

21 N ⁻ layer 22 N ⁻ layer 24 N ⁻ layer 26 N ⁻ layer 32 impurity 33 P layer 34 P layer 41 P ⁻ layer 42 P ⁻ layer 43 P ⁻ layer 64 P ⁺ layer 71 P channel transistor 72 N channel transistor 73 P Channel transistor 74 N-channel transistor

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8238 H01L 27/092

Claims (1)

(57) [Claims] 1. A high-breakdown-voltage transistor in which an offset layer having a lower impurity concentration than the drain layer is provided between a drain layer and a channel portion, and a normal-breakdown-voltage transistor in which the offset layer is not provided. In the method of manufacturing a complementary semiconductor device, a second conductivity type impurity is introduced into a first region of the first conductivity type channel transistor where a channel stop layer is to be formed, and simultaneously a second conductivity type impurity of the second conductivity type channel transistor is formed. Second to form channel stop layer
Region and the third region where the offset layer is to be formed in the high-breakdown-voltage first conductivity type channel transistor,
The step of introducing the impurity of the second conductivity type, and the step of introducing the impurity of the first conductivity type into the fourth region where the channel stop layer is to be formed in the channel transistor of the second conductivity type having a high withstand voltage. Introducing the impurity of the first conductivity type into a third region.