JP3188132B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reducing junction capacitance in a semiconductor device which performs channel implantation and suppresses a short channel effect.

[0002]

2. Description of the Related Art A method of manufacturing a semiconductor device of this type is described below.
This will be described with reference to the drawings of FIGS. In FIG. 14, reference numeral 51 denotes a semiconductor substrate of one conductivity type, for example, a P-type silicon substrate, on which an SiO2 film 52 and a Si3 N4 film 5 are formed.
After forming a resist film 54 having an opening on the N-well formation region 55, phosphorus ions (31P +) are implanted using the resist film 54 as a mask to form the N-well formation region 55. .

Next, after etching the Si3N4 film 53 using the resist film 54 as a mask, the resist film 54 is removed, and then the well is oxidized to form a LOCO for well formation.
An S oxide film 56 is formed. Subsequently, the Si3N4 film 53 is formed.
Is removed by etching, as shown in FIG.
Boron ion (11B +) using OS oxide film 56 as a mask
Is implanted to form a P-well formation region 57.

[0006] Next, as shown in FIG. 16, an N-well region 58 and a P-well region 59 are formed by well diffusion over the entire surface of the substrate. Subsequently, as shown in FIG. 17, the pad oxide film 52 and the LOCOS oxide film 56 on the substrate are etched. Next, the pad oxide film 60 and the Si3 N4 film 6 are formed thereon.
1 and a P-channel type and an N-channel type MO.
After forming a resist film 62 on the S transistor formation region, the pad oxide film 6 is formed using the resist film 62 as a mask.
0 and the Si3 N4 film 61 are removed by etching. And
After a resist film 63 is formed on the N-well region 58, boron ions (11B +) are implanted to form a channel stopper layer forming region 64 in the P-well region 59.

Next, a resist film 63 and a resist film 62
After removing the LOCOS oxide film 65, field oxidation is performed as shown in FIG. 18 to form a LOCOS oxide film 65 for element isolation, and a channel stopper layer 66 is formed below the LOCOS oxide film 65 on the P well region 59. Then, the LO
The pad oxide film 60 is formed by using the COS oxide film 65 as a mask.
Then, the Si3N4 film 61 is etched. After the gate oxide film 67 is formed by thermally oxidizing the substrate, a resist film 68 is formed on the N well region 58 as shown in FIG.
Using the resist film 68 as a mask, boron ions (11B +) are implanted to form a deep channel implantation layer 69 below the gate oxide film 67 on the P well region 59.

Subsequently, after removing the resist film 68,
A resist film (not shown) for masking the P-well region 59 is formed, and P-channel threshold voltage control ion implantation is performed in the N-well region. Next, after removing the resist film, a polysilicon layer 7 for forming a gate electrode is formed on the entire surface of the substrate.
0 and a tungsten silicide film 71 are laminated and etched through a resist film (not shown) to form a polycide gate electrode as shown in FIG.

Next, after forming a resist film (not shown) on the P-channel type MOS transistor formation region, for example, phosphorus ions (31P +) or arsenic ions (75As +) are implanted using the polycide gate electrode as a mask. To form a low concentration N- type source / drain diffusion layer 72. Similarly, after a resist film (not shown) is formed on the N-channel MOS transistor formation region, boron ions (11B
+) Or boron fluoride (49BF2 +) is implanted to form a low concentration P- type source / drain diffusion layer 73.

Next, as shown in FIG. 21, a sidewall layer 74 is formed on the side walls of both polycide gate electrodes, and as shown in FIG. 22, a resist film 75 is formed on a P-channel MOS transistor formation region. Thereafter, using the polycide gate electrode and the side wall layer 74 as a mask, for example, phosphorus ions (31P +) or arsenic ions (75A
s +) is implanted to form a high concentration N + type source / drain diffusion layer 76. Similarly, as shown in FIG. 23, a resist film 77 is formed on the N-channel type MOS transistor formation region.
Is formed, for example, using the polycide gate electrode and the sidewall layer 74 as a mask, for example, boron ions (11
B +) or boron fluoride (49BF2 +) was implanted to form a high concentration P + type source / drain diffusion layer 78.

In the deep channel implanted layer 69 formed as described above, the short channel effect can be suppressed, but the junction capacitance between the source / drain diffusion layer and the substrate is increased due to the high impurity concentration. was there. Further, since a dedicated resist film is used to form the channel stopper layer 66 and the deep channel implantation layer 69, there is a disadvantage that the number of manufacturing steps is increased.

[0010]

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device which can reduce the junction capacitance and the number of manufacturing steps.

[0011]

Therefore, according to the present invention, a channel stopper layer and a deep channel implantation layer are simultaneously formed by injecting impurities from above a silicon substrate through a LOCOS oxide film and a gate electrode. Further, a resist film for forming a source / drain diffusion layer was also used as a mask for injecting the impurity.

Further, according to the present invention, an impurity is implanted through a LOCOS oxide film by using a resist film formed so as to cover the source / drain diffusion layer formation region as a mask,
The channel stopper layer and the deep channel implantation layer are formed simultaneously.

[0013]

According to the above structure, according to the method of manufacturing a semiconductor device of the present invention, impurities are implanted from above the silicon substrate by penetrating the LOCOS oxide film and the gate electrode.
Since the deep channel implantation layer is formed at a relatively deep position in the source / drain diffusion layer region, the junction capacitance between the source / drain diffusion layer and the substrate can be reduced. Further, using the resist film for forming the source / drain diffusion layers, the impurity for forming the deep channel implantation layer is implanted.

In the present invention, the deep channel implantation layer is formed by implanting impurities by penetrating the LOCOS oxide film using the resist film formed so as to cover the source / drain diffusion layer formation region as a mask.
Since it is not implanted into the drain diffusion layer region, the junction capacitance between the source / drain diffusion layer and the substrate can be further reduced.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings. In FIG. 1, reference numeral 1 denotes a semiconductor substrate of one conductivity type, for example, a P-type silicon substrate. A pad oxide film 2 having a thickness of about 500.degree. The Si3N4 film 3 is formed by the LPCVD method. Subsequently, after forming a resist film 4 having an opening on the N-well formation region 5, for example, phosphorus ions (31P +) are accelerated to 160 V by using the resist film 4 as a mask.
KeV, implantation amount 4.0E12 / cm2 to 5.0E12
/ Cm2 (4.0E12 is 4.0 times 10 12
It is the meaning of the square. Hereinafter, the same applies. Inject under the condition of).

Next, using the resist film 4 as a mask, S
After etching the i3N4 film 3, the resist film 4 is removed, and then the well is oxidized to form a LOCOS oxide film 6 for forming a well. Subsequently, the Si3N4 film 3 is removed by etching. Then, as shown in FIG. 2, using the LOCOS oxide film 6 as a mask, for example, boron ions (11B +) are implanted under the conditions of an acceleration voltage of 80 KeV and an implantation amount of 4.0E12/cm@2 to form a P-well formation region 7. .

Subsequently, as shown in FIG. 3, an N-well region 8 and a P-well region 9 are formed by well diffusion over the entire surface of the substrate. Next, as shown in FIG. 4, after etching the pad oxide film 2 and the LOCOS oxide film 6 on the substrate, a pad oxide film 10 and a Si3N4 film 11 are formed on the entire surface of the substrate. And P-channel type and N-channel type M
After a resist film 12 is formed on the OS transistor formation region, the pad oxide film 10 and the Si3N4 film 11 are etched using the resist film 12 as a mask. Thereafter, the resist film 12 is removed, and the substrate is subjected to field oxidation using the Si3N4 film 11 as a mask as shown in FIG. 5 to form a LOCOS oxide film 13 having a thickness of about 4000 to 5000 for element isolation. Then, the pad oxide film 10 and the Si3 N4 film 11 are removed by etching. Thereafter, the gate oxide film 14 is formed by thermally oxidizing the substrate.

Subsequently, after a polysilicon layer 15 having a thickness of about 2000 .ANG. And a tungsten silicide film 16 having a thickness of about 2000 .ANG. Are formed on the substrate,
A resist film (not shown) is formed on the P-channel type and N-channel type MOS transistor formation regions, and the polysilicon layer 15 and the tungsten silicide film 16 are selectively etched through the resist film as shown in FIG. Then, polycide gate electrodes 17A and 17B are formed.

Next, a resist film (not shown) is formed on the N-well region 8 to form the resist film and the N-channel type MO.
Polycide gate electrode 17 on S transistor formation region
Using A as a mask, for example, arsenic ions (75 As +) are implanted at about 1.0E13 / cm 2,
A lightly doped N @--type source / drain diffusion layer 18 of the transistor is formed. Similarly, after removing the resist film on the N-well region 8, a resist film (not shown) is formed on the P-well region 9 to remove the resist film and the gate electrode 17B on the P-channel MOS transistor formation region. As a mask, for example, boron fluoride ion (49BF2 +) is implanted at about 3.0E13 / cm2 to form a P-channel MO.
A low concentration P @-type source / drain diffusion layer 19 of the S transistor is formed.

Next, as shown in FIG. 7, a sidewall layer 20 is formed on the side walls of the polycide gate electrodes 17A and 17B. In this step, the sidewall layer 20 is formed by etching back an approximately 3000 ° SiO 2 film over the entire surface of the substrate by LPCVD. continue,
As shown in FIG. 8, a resist film 2 is formed on the N-well region 8.
Then, for example, arsenic ions (75 As @ +) are implanted at about 5.0E15/cm@2 using the resist film 21, the polycide gate electrode 17A on the N-channel MOS transistor formation region and the sidewall layer 20 as a mask. Then, a high concentration N @ + type source / drain diffusion layer 22 of an N channel type MOS transistor is formed.

Next, as shown in FIG.
For example, boron ions (11B +) are introduced into the P-well region 9 using the mask 1 as an acceleration voltage of approximately 150 KeV to 400 KeV.
KeV, implantation amount 1.0E13 / cm2 to 2.0E13
/ Cm @ 2 to form an implantation layer 23 through the LOCOS oxide film 13 and the polycide gate electrode 17A. As a result, a channel stopper layer 23A is formed below the LOCOS oxide film 13, and a deep channel implant layer 23B for suppressing the short channel effect is formed below the polycide gate electrode 17A. Is reduced. That is, since the deep channel implantation layer 23B is formed at a position relatively shallow from the substrate surface below the polycide gate electrode as shown in FIG. 9, the short channel effect can be suppressed, and furthermore, in the source / drain diffusion layer region, Deeper and deeper between the source / drain diffusion layer and the deep channel implant layer.
The junction capacitance between the drain diffusion layer and the substrate is reduced.

Subsequently, after removing the resist film 21 on the N-well region 8, a resist film 24 is formed on the P-well region 9 as shown in FIG.
Using the gate electrode 17B and the sidewall layer 20 on the P-channel type MOS transistor formation region as a mask, for example, boron fluoride ion (49BF2 +) is added to about 2.0E1.
By implanting 5 / cm @ 2, a high concentration P @ + type source / drain diffusion layer 25 of a P channel type MOS transistor is formed.

Next, as shown in FIG. 11, for example, phosphorus ions (31P +) are introduced into the N-well region 8 using the resist film 24 as a mask at an acceleration voltage of about 350 KeV to 700 keV.
KeV, implantation amount 1.0E13 / cm2 to 2.0E13
/ Cm @ 2 to form an implantation layer 26 through the LOCOS oxide film 13 and the polycide gate electrode 17B. As a result, a channel stopper layer 26A is formed below the LOCOS oxide film 13, and a deep channel implant layer 26B for suppressing the short channel effect is formed below the polycide gate electrode 17B. Is reduced.

As described above, according to the present invention, the mask alignment step for forming the channel stopper layer and the mask alignment step for forming the deep channel implantation layer can be reduced, and the junction capacitance can be reduced. Further, another embodiment of the formation of the implant layer which can reduce the junction capacitance will be described with reference to FIGS.

First, after the step of FIG. 5 of the first embodiment, that is, after forming the LOCOS oxide film 13 and the gate oxide film 14, the N well region 8 and the P well region 9 are formed as shown in FIG. A resist film 2 is formed on the region for forming the N @-
7 is formed. Then, using the resist film 27 as a mask, for example, boron ions (11B +) are implanted into the P well region 9 under the conditions of an acceleration voltage of about 150 KeV to 400 KeV and an implantation amount of 1.0E13 / cm2 to 2.0E13 / cm2. , An implantation layer 28 is formed. This allows
A channel stopper layer 28 is provided below the LOCOS oxide film 13.
A is formed, a deep channel implantation layer 28B for suppressing the short channel effect is formed below the polycide gate electrode formation region, and a mask made of the resist film 27 is formed below the source / drain diffusion layer formation region. Since the ion implantation is not performed, the junction capacitance between the source / drain diffusion layer and the substrate is further reduced. Hereinafter, in a state where the implantation layer 28 is formed as shown in FIG.
As described in the step of FIG. 6, the polycide gate electrodes 17A and 17B and the N− and P− source / drain diffusion layers 18 and 19 are formed. Thereafter, a semiconductor device is manufactured by performing the same steps as in the first embodiment.

In this embodiment, the gate electrode is a polycide gate electrode. However, the present invention is not limited to this. For example, a silicide gate electrode or a high melting point metal gate electrode may be used.

[0027]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the impurity is implanted from above the silicon substrate by penetrating the LOCOS oxide film and the gate electrode. Since it is formed at a relatively deep position below the layer region, the junction capacitance between the source / drain diffusion layer and the substrate can be reduced, and the speed of the device can be increased.

Further, since the step of implanting the impurity for forming the deep channel implantation layer is performed by using the resist film for forming the source / drain diffusion layers, the number of manufacturing steps can be reduced. Further, since the LOCOS oxide film is penetrated and impurities are implanted by using the resist film formed so as to cover the source / drain diffusion layer formation region as a mask, the deep channel implantation layer is formed in the source / drain diffusion layer region. Since it is not implanted below, the junction capacitance between the source / drain diffusion layer and the substrate is further reduced.

[Brief description of the drawings]

FIG. 1 is a first cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a second sectional view illustrating the method for manufacturing a semiconductor device according to the present invention;

FIG. 3 is a third sectional view illustrating the method for manufacturing a semiconductor device according to the present invention;

FIG. 4 is a fourth sectional view illustrating the method for manufacturing a semiconductor device according to the present invention;

FIG. 5 is a fifth sectional view illustrating the method for manufacturing a semiconductor device of the present invention;

FIG. 6 is a sixth sectional view illustrating the method for manufacturing a semiconductor device according to the present invention;

FIG. 7 is a seventh sectional view illustrating the method for manufacturing a semiconductor device of the present invention;

FIG. 8 is an eighth sectional view showing the method for manufacturing a semiconductor device according to the present invention;

FIG. 9 is a ninth cross-sectional view illustrating the method for manufacturing a semiconductor device of the present invention;

FIG. 10 is a tenth view illustrating the method for manufacturing a semiconductor device of the present invention;
FIG.

FIG. 11 is an eleventh view illustrating the method for manufacturing a semiconductor device of the present invention;
FIG.

FIG. 12 is a first cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 13 is a second sectional view illustrating the method of manufacturing the semiconductor device according to another embodiment of the present invention;

FIG. 14 is a first cross-sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 15 is a second cross-sectional view showing the conventional method for manufacturing a semiconductor device.

FIG. 16 is a third cross-sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 17 is a fourth cross-sectional view illustrating the conventional method for manufacturing a semiconductor device.

FIG. 18 is a fifth sectional view illustrating the method for manufacturing the conventional semiconductor device.

FIG. 19 is a sixth sectional view illustrating the method for manufacturing the conventional semiconductor device.

FIG. 20 is a seventh sectional view showing the conventional method for manufacturing a semiconductor device.

FIG. 21 is an eighth sectional view showing the conventional method for manufacturing a semiconductor device.

FIG. 22 is a ninth sectional view illustrating the conventional method for manufacturing a semiconductor device.

FIG. 23 is a tenth cross-sectional view showing a conventional method for manufacturing a semiconductor device.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ identification code FI H01L 29/78 (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 21/265 H01L 21/336 H01L 21/76 H01L 21/8234-21/8238 H01L 27/08-27/092 H01L 29/78

Claims (2)

(57) [Claims] 1. A LOCOS on a silicon substrate of one conductivity type.
Forming an oxide film and forming a gate oxide film on the substrate except for the LOCOS oxide film.
And a resist covering the source / drain diffusion layer formation region
Forming a film and penetrating the LOCOS oxide film using the resist film as a mask
To implant the channel stopper layer and
Process for forming a deep channel implantation layer simultaneously
If, gate on the gate oxide film after removing the resist film
Forming a gate electrode, and forming source / drain diffusion layers at both ends of the gate electrode.
Manufacturing a semiconductor device, comprising the steps of:
Method. 2. A well region of one conductivity type on a silicon substrate.
And forming a reverse conductivity type well region, and Forming a LOCOS oxide film on the substrate; Form a gate oxide film on the substrate except for the LOCOS oxide film
The process of Covering the reverse conductivity type well region and one conductivity type
Over the source / drain diffusion layer formation region on the well region
Forming a resist film to be coated; Penetrate LOCOS oxide film using the resist film as a mask
To implant the channel stopper layer and
Process for forming a deep channel implantation layer simultaneously
When, After removing the resist film, one conductivity type and reverse conductivity type
Form gate electrode on MOS transistor formation area
Process and Forming a resist film on the reverse conductivity type well region;
Resist film and reverse conductivity type MOS transistor formation region
Inject impurity of opposite conductivity type using upper gate electrode as mask
Source / drain of MOS transistor of reverse conductivity type
Forming a diffusion layer; After removing the resist film, on the well region of one conductivity type
A resist film is formed on the resist film and one conductivity type M
The gate electrode on the OS transistor formation region is To screen
To implant one conductivity type impurity
Forming a source / drain diffusion layer of a transistor.
A method of manufacturing a semiconductor device.