JP3162937B2 - Method for manufacturing CMOS semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a CMOS semiconductor device having a PMOS transistor and an NMOS transistor, and more particularly to a method for simplifying an ion implantation process, reducing a leakage current in a weak inversion region of a transistor, and reducing a leakage current. An object of the present invention is to make it possible to improve a transistor driving capability with an increase in carrier mobility due to a thinner gate oxide film and a lower concentration of substrate impurities. here,
The PMOS transistor is a P-channel type MOS transistor, and the NMOS transistor is an N-channel type MOS transistor.
It means transistor.

[0002]

2. Description of the Related Art In recent years, a CMOS microcomputer or the like used for an IC card has been required to have a low voltage of about 1.2 [V]. Therefore, in such a CMOS semiconductor device,
It is necessary for the switching device that the threshold voltage be reduced to about 0.6 [V] and the leakage current be low.

A method of manufacturing such a conventional CMOS semiconductor device will be described with reference to FIGS. First, as shown in FIG. 9, after forming an N-well region 52 in a PMOS transistor formation region of a semiconductor substrate of one conductivity type, for example, a P-type silicon substrate 51, a low pressure CVD method is performed on the substrate 51 via a pad oxide film. A silicon nitride film is formed thereon, and the silicon nitride film is covered with a photoresist film 55, and the silicon nitride film is selectively etched using the photoresist film 55 as a mask. A nitride film 54A is formed by lamination, and a pad oxide film 5 is formed in the PMOS transistor formation region.
3B and a silicon nitride film 54B are laminated.

Next, after removing the photoresist film 55, boron ions (11B +) are implanted into the substrate 51 while the PMOS transistor forming region side is masked with the photoresist film 56 as shown in FIG. Then, the boron ions (11B +) are implanted into the region except for the portion where the pad oxide film 53A and the silicon nitride film 54A are stacked.

Subsequently, after the photoresist film 56 is removed, thermal oxidation is performed using the silicon nitride films 54A and 54B as a mask, as shown in FIG.
The oxide film 57 is formed, and the ion-implanted boron ions (11B +) are diffused below the substrate to form a channel stopper layer 58. Next, as shown in FIG. 12, using the photoresist film 59 as a mask, boron ions (11B +) are implanted shallowly into the PMOS transistor formation region.

Subsequently, as shown in FIG. 13, after removing the photoresist film 59, boron ions (11B +) are deeply implanted into the NMOS transistor formation region using the photoresist film 60 as a mask. Next, after removing the dummy oxide film, as shown in FIG.
A gate oxide film 61 is formed on the transistor formation region. Here, the channel doped diffusion layer 62 is formed in the channel region.
Is formed. A gate electrode 63 made of polysilicon or the like is formed on the gate oxide film 61, and each impurity is implanted using the gate electrode 63 as a mask. As shown in FIG. Layers 64 and 66, drain diffusion layer 6
5, 67 were formed.

[0007]

However, in the conventional manufacturing method, in order to form a channel dope layer in each MOS transistor formation region, a channel ion implantation step and two mask alignment steps associated therewith are separately performed. And there is a problem that the number of processes is large.

In addition, there is a problem that the leakage current is large in the weak inversion region of the MOS transistor, and the threshold voltage cannot be reduced much.

[0009]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a step of forming a reverse conductivity type well region in a one conductivity type MOS transistor formation region of a one conductivity type semiconductor substrate. Selectively forming a silicon nitride film in the one conductivity type and the opposite conductivity type MOS transistor formation region on the substrate; and selectively forming a photoresist film on the one conductivity type MOS transistor formation region in the silicon nitride film. And implanting one conductivity type impurity into the substrate at an acceleration voltage such that the photoresist film functions as a mask and the silicon nitride film in the reverse conductivity type MOS transistor formation region functions as a mask. Ion implantation step, the photoresist film acts as a mask,
A second ion implantation step of implanting an impurity of one conductivity type into the substrate at an accelerating voltage penetrating the silicon nitride film in the MOS transistor formation region of the opposite conductivity type; and a silicon ion implantation step after removing the photoresist film. A LOCOS oxide film is formed by performing thermal oxidation using the film as an oxidation resistant mask, and a channel stopper layer and a channel dope layer are formed by diffusing each impurity ion-implanted in the first and second ion implantation steps. Forming a dummy oxide film by performing a dummy oxidation after removing both silicon nitride films; and forming the gate oxide film by removing the dummy oxide film and performing a thermal oxidation. Using the oxide film as a mask, an impurity of one conductivity type is applied from above the gate oxide film for adjusting the threshold voltage to both MOs of the substrate. And it has a third ion implantation step of implanting the transistor formation region.

The present invention also provides a step of forming a well region of the opposite conductivity type in a region of forming a MOS transistor of one conductivity type of a semiconductor substrate of one conductivity type, and a MOS transistor of one conductivity type and a reverse conductivity type on the substrate. Selectively forming a silicon nitride film in the formation region, selectively forming a photoresist film on the silicon nitride film in the one conductivity type MOS transistor formation region, and using the photoresist film as a mask A first ion implantation step of implanting one conductivity type impurity into the substrate at an acceleration voltage such that the silicon nitride film in the MOS transistor formation region of the opposite conductivity type functions as a mask, and the photoresist film functions as a mask; In addition, an impurity of one conductivity type is injected into the substrate with an acceleration voltage penetrating the silicon nitride film in the MOS transistor formation region of the opposite conductivity type. Second ion implantation step, LOCOS by thermal oxidation as oxidation resistant mask both silicon nitride film after removing the photoresist film
Forming an oxide film and forming a channel stopper layer and a channel dope layer; forming a dummy oxide film by performing dummy oxidation after removing both silicon nitride films; and after removing the dummy oxide film. A step of forming a gate oxide film by performing thermal oxidation, and a third step of injecting one conductivity type impurity into both MOS transistor formation regions of the substrate using the LOCOS oxide film as a mask.
Ion implantation step.

[0011]

According to the above structure, the first and second ion implantation steps for implanting impurities for forming the channel stopper layer and the channel-doped diffusion layer are performed with one mask, so that the number of times of mask alignment can be reduced as compared with the conventional case. Can be reduced. Further, in the CMOS semiconductor device manufactured by the manufacturing method of the present invention, the surface impurity concentration of the channel region is reduced by the third ion implantation step in which formation of the dummy oxide film, formation of the gate oxide film, and subsequent mask alignment are unnecessary, Leakage current in the weak inversion region can be reduced.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the method of manufacturing a CMOS semiconductor device according to the present invention will be described below in detail with reference to the drawings. First, FIG.
As shown in FIG. 1, after an N well region 2 is formed in a PMOS transistor formation region of a semiconductor substrate of one conductivity type, for example, a P type silicon substrate 1, a silicon nitride film is formed on the substrate 1 via a pad oxide film by a low pressure CVD method. (SiN film) is formed, a photoresist film 5 is coated thereon, and the silicon nitride film is selectively etched using the photoresist film 5 as a mask, so that the pad oxide film 3A and the silicon A nitride film 4A is formed by lamination, and a pad oxide film 3 is formed in the PMOS transistor formation region.
B and a silicon nitride film 4B are laminated.

Next, after the photoresist film 5 is removed, in the first ion implantation step, for example, at a dose of 4E13 / cm2 (4E13
Means 4 times 10 13. The same applies to the following. ) Is implanted shallowly into the substrate 1 at an acceleration voltage of about 30 KeV, which is a condition that does not penetrate the pad oxide film 3A and the silicon nitride film 4A, and the boron ions (11B +) 3A
Then, the first ion-implanted region 7 is formed by implanting the silicon nitride film 4A into the region excluding the portion where the silicon nitride film 4A is laminated.

Subsequently, in a second ion implantation step, for example, boron ions (11B +) having an implantation amount of 1E12 / cm 2 or less are used.
Is deeply implanted into the substrate 1 at an acceleration voltage of about 160 KeV, which is a condition capable of penetrating the pad oxide film 3A and the silicon nitride film 4A, and a channel to be described below is also provided below the pad oxide film 3A and the silicon nitride film 4A. A second ion implantation region 8 for forming the doped diffusion layer 11 is formed.

Next, after removing the photoresist film 6, thermal oxidation is performed using the silicon nitride films 4A and 4B as a mask to form a LOCOS oxide film 9 as shown in FIG. Boron ion (1
1B +) diffuses to form a channel-doped diffusion layer 11 in the channel stopper layer 10 and the channel region. Next, after removing the pad oxide film 3A and the silicon nitride film 4A, dummy oxidation is performed. After the dummy oxide film is removed, thermal oxidation is performed to remove the dummy oxide film to about 160 ° C. as shown in FIG.
A gate oxide film 12 having a thickness of about 170 ° is formed. Subsequently, in a third ion implantation step, for example, an implantation amount of 1.
Boron ions (11B @ +) of 15E12 / cm @ 2 are implanted shallowly over the entire surface of the substrate at an acceleration voltage of about 25 KeV. As a result, as shown in FIG.
By implanting 2 / cm 2 of impurity, 0.6
The threshold voltage of [V] is set.

Next, a gate electrode 1 made of polysilicon or the like is formed on the gate oxide film 12 as shown in FIG.
3 are formed, and the respective impurities are implanted using the gate electrode 13 as a mask, so that the source diffusion layers 14 and 1 are formed in both MOS transistor formation regions as shown in FIG.
6, the drain diffusion layers 15 and 17 are formed. From the above steps, according to the present embodiment, the first and second ion implantation steps are performed using one mask, so that the number of mask alignment steps can be reduced as compared with the related art.

In the CMOS semiconductor device manufactured by the manufacturing method of the present invention, the surface impurity of the channel region is formed by forming a dummy oxide film, forming a gate oxide film, and then performing a third ion implantation process for controlling a threshold voltage. The concentration is reduced, and the leak current in the weak inversion region can be reduced. Further, as shown in FIG. 8, in the present invention, the subthreshold current (2) can be made smaller than that of the conventional (1).

Therefore, according to the present invention, the threshold voltage can be lowered without increasing the leakage current.
It can cope with a lower voltage of the OS semiconductor device, and is particularly suitable for application to a CMOS semiconductor device for a portable device such as an IC card. Furthermore, in a CMOS semiconductor device for a portable device which remarkably dislikes a leak current, the threshold voltage is set to 0.
It can be set to 55 [V] to 0.6 [V]. In addition, it has been reported from the circuit design department that in a usage as a normal low-voltage device, good switching characteristics can be obtained as a CMOS semiconductor device even when the threshold voltage is set to 0.4 [V]. .

Generally, a substrate bias generation circuit is known as one of the techniques for increasing the speed by lowering the threshold voltage. Since the substrate bias circuit can control the threshold voltage of the N-channel MOS transistor by utilizing the substrate bias effect, the threshold voltage of the NMOS circuit can be reduced while maintaining good weak inversion characteristics. It is possible to set.

However, since the voltage generated by the substrate bias circuit is usually -2 [V] to -3 [V], it cannot be used for an IC card such as power supply voltage +1.2 [V]. In addition, the substrate bias effect is reduced by an N-channel type MO.
This method is effective only for S transistors and is useful for NMOS circuits, but cannot be applied to P-channel transistors. Therefore, a substrate bias generation circuit is meaningless for speeding up CMOS circuits. ,
The speed was controlled by the threshold voltage of the P-channel MOS transistor.

According to the present invention, not only the N-channel MOS transistor but also the P-channel MOS transistor has a low threshold value, so that the speed of the CMOS circuit can be increased.

[0022]

As described above, according to the present invention, the first and second ion implantation steps for implanting impurities for forming the channel stopper layer and the channel-doped diffusion layer are performed using one mask. The number of times can be reduced as compared with the conventional case, which can contribute to rationalization of the manufacturing process.

Further, in the CMOS semiconductor device manufactured by the manufacturing method of the present invention, the weak inversion characteristics of the MOS transistor can be improved. In particular, the present invention relates to 1.2
It is suitable for manufacturing a low-voltage CMOS semiconductor device of about [V].

[Brief description of the drawings]

FIG. 1 is a first sectional view illustrating a method for manufacturing a CMOS semiconductor device of the present invention.

FIG. 2 is a second sectional view illustrating the method for manufacturing the CMOS semiconductor device of the present invention.

FIG. 3 is a third sectional view illustrating the method for manufacturing the CMOS semiconductor device according to the present invention;

FIG. 4 is a fourth sectional view illustrating the method for manufacturing the CMOS semiconductor device according to the present invention;

FIG. 5 is a fifth sectional view illustrating the method for manufacturing the CMOS semiconductor device of the present invention.

FIG. 6 is a sixth sectional view illustrating the method for manufacturing the CMOS semiconductor device according to the present invention;

FIG. 7 is a diagram illustrating a relationship between a threshold voltage and an ion implantation amount.

FIG. 8 is a diagram showing a relationship between a subthreshold current and a gate voltage.

FIG. 9 is a cross-sectional view for explaining a conventional manufacturing method.

FIG. 10 is a cross-sectional view for explaining a conventional manufacturing method.

FIG. 11 is a cross-sectional view for explaining a conventional manufacturing method.

FIG. 12 is a cross-sectional view for explaining a conventional manufacturing method.

FIG. 13 is a cross-sectional view for explaining a conventional manufacturing method.

FIG. 14 is a cross-sectional view for explaining a conventional manufacturing method.

FIG. 15 is a cross-sectional view for explaining a conventional manufacturing method.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8238 H01L 27/092

Claims (1)

(57) [Claims] An MO of one conductivity type is provided on a semiconductor substrate of one conductivity type.
Forming a well region of the opposite conductivity type in the S transistor formation region; selectively forming a silicon nitride film in the one conductivity type and the opposite conductivity type MOS transistor formation region on the substrate; Selectively forming a photoresist film on the silicon nitride film in the MOS transistor formation region, and forming the photoresist film as a mask and the silicon nitride film in the reverse conductivity type MOS transistor formation region as a mask. A first ion implantation step of implanting an impurity of one conductivity type into the substrate at an acceleration voltage, and an acceleration voltage in which the photoresist film functions as a mask and penetrates a silicon nitride film in a region for forming the opposite conductivity type MOS transistor. A second ion implantation step of implanting an impurity of one conductivity type into the substrate, and removing the photoresist film. LOC by performing thermal oxidation of both silicon nitride film as the oxidation resistant mask after
While forming an OS oxide film, the first and second ion
Forming a channel stopper layer and a channel dope layer by diffusing each impurity ion-implanted in the ion implantation step; and forming a dummy oxide film by performing a dummy oxidation after removing both silicon nitride films. Removing the dummy oxide film, performing thermal oxidation to form a gate oxide film, and then masking the LOCOS oxide film.
A third ion implantation step of implanting one conductivity type impurity from above the gate oxide film into the both MOS transistor formation regions of the substrate for adjusting a threshold voltage. A method for manufacturing a CMOS semiconductor device.