JPH02264464A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To carry out the formation of a well and the implantation of channel ions using the same mask to lessen photoengraving processes in number, to implant impurity ions for the formation of the well with a prescribed energy so as to dispense with a thermal diffusion process, and to inject impurity of the same conductivity type with the well so as to prevent punch-through. CONSTITUTION:An SiO2 film 2 is provided to a P<->-Si substrate 1, and an Si3N4 mask 3 is deposited thereon through a resist 4. An isolating oxide film 3 is formed, and the mask 3 is removed. A resist mask 28 is deposited, and B<+> ions are implanted. In this case, regions 29 are formed by the injection of B<+> ions at a high energy and a P well 6 is formed at a low energy. The regions 29 serve as a channel stopper. Moreover, B ions are implanted into a channel 13 with a low energy to carry out the adjustment of a punch-through preventive Vth. Then, a resist mask 30 is coated, P<+> ions are implanted properly choosing the implantation energy to form a region 31 and an N well 5, and B<+> and As<+> ions are implanted to form a channel layer 15 for the prevention of punch- through and for the adjustment of Vth. By this constitution, not only processes can be lessened in number but also a semiconductor device of this design can be reduced in production time.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device in which a well is formed in a semiconductor substrate and a transistor is formed on the main surface of the well. The present invention relates to a method of manufacturing a semiconductor device, which is improved so that the manufacturing steps and manufacturing time required for the manufacturing process can be reduced.

[Prior Art] A typical example of a semiconductor device in which a well is formed in a semiconductor substrate and a transistor is formed on the main surface of this well is a complementary type M
OS) transistor (hereinafter referred to as CMOS transistor). CMOS) transistor is n-channel MO
It is characterized by a mixture of S) transistors and p-channel MOS) transistors. The advantage of CMOS) transistors is that the DC voltage flowing between the power supply terminals is very small.
The reason is that the current consumption is extremely low.

By the way, among the process techniques for constructing a CMOS structure, the most characteristic technique is the well forming technique. NMO3 on the same semiconductor substrate! =In order to produce PMO3, the formation regions of each element must be separated. That is, a p-well region for forming an n-channel device and an n-well region for forming a p-channel, channel device must be provided.

A conventional well formation technique will be explained with reference to the drawings.

FIGS. 5A to 5S are cross-sectional views showing the manufacturing process of a conventional CMO transistor.

Referring to FIG. 5A, an oxide film 2 and a nitride film 3 are sequentially formed on a semiconductor substrate 1 (for example, a silicon substrate). Next, a resist 4 is applied to the entire surface of the semiconductor substrate 1.

Next, referring to FIG. 5B, the resist 4 is patterned to expose the portion where the N-well is to be formed.

Using this patterned resist 4 as a mask, the nitride film 3 is patterned.

Next, use the patterned resist 4 as a mask,
An impurity for forming an N well, such as phosphorus, is implanted.

After that, the resist 4 is removed.

Next, referring to FIG. 5C, using the nitride film 3 as a mask,
A thick isolation oxide film 2a is selectively formed on a portion of a semiconductor substrate 1. After that, nitride film 3 is removed.

Next, referring to FIG. 5D, an impurity for forming a p-well, such as boron, is implanted into the entire surface. Next, referring to FIG. 5E, heat treatment (6 to 8 hours) is performed to deeply diffuse the well-forming impurity. After that, isolation oxide film 2
By removing a, a semiconductor substrate 1 in which an N well 5 and a P well 6 are formed is obtained.

Next, referring to FIG. 5F, oxide film 7, nitride film 8, and resist 9 are sequentially formed on the main surface of semiconductor substrate 1. Referring to FIG.

Next, referring to FIG. 5G, in order to define the active region, the resist 9 is patterned by photolithography so that the pattern of the resist 9 remains in the upper portion of the active region. Thereafter, the nitride film 8 is patterned using the patterned resist 9 as a mask. Then, a resist is formed on the entire surface of the semiconductor substrate 1 including the pattern of the resist 9 (not shown).

Next, referring to FIG. 5H, the resist 10 is patterned so that the pattern of the resist 10 remains on the N-well region 5. Thereafter, using the pattern of the resist 10 and the pattern of the resist 9 as masks, the same boron ions as those forming the P well 6 are implanted into the non-active region to form the isolation section 11. The reason for implanting boron into the non-active region is as follows. That is, in the next step, a thick isolation oxide film is formed in the inactive region to form the active region, but the impurity bofun forming the P-well 6 is absorbed by the isolation oxide film, so the non-active region is formed. The concentration of boron in the active region is reduced. When the boron concentration decreases, a phenomenon called latch-up occurs. Latch-up is a phenomenon in which a parasitic bipolar transistor formed in an OMO3 structure performs a switching operation due to a noise signal or the like, and the inverter enters a shunt state. Therefore, an isolation step is necessary in which boron is implanted into the non-active region to form the isolation section 11.

After the isolation process, the pattern of resist 9 and the pattern of resist 10 are removed.

Thereafter, referring to FIG. 5A, thermal oxidation is performed using the pattern of nitride film 8 as a mask, thereby forming a thick isolation oxide film 7a in the non-active region. Thereafter, the nitride film 8 is removed to obtain the semiconductor substrate 1 in which the active region is defined.

Next, referring to FIG. 51, a pattern of resist 12 is formed on N-well region 5 by photolithography.

Thereafter, using the pattern of the resist 12 as a mask, boron ions are implanted into the channel region 13 of the MO8TJ1) transistor to be formed on the P well 6. The purpose of ion implantation into the channel region 13 is to make the threshold voltage of the MO8 transistor appropriate and to prevent punch-through. Punch-through refers to a phenomenon in which when the drain voltage is increased, the drain depletion layer extends into the channel region and finally connects with the source region, resulting in the current not being able to be controlled by the gate voltage. After that, the pattern of the resist 12 is removed.

Next, fifthly, referring to the figure, a pattern of resist 14 is formed on P-well region 6 by photolithography.

Thereafter, boron and arsenic ions are implanted into the channel region 15 of the MOS transistor to be formed in the N well 6 using the pattern of the resist 14 as a mask. The reason for using boron at this time is to balance the threshold voltages of the respective transistors formed in the P well 6 and the N well 5.

Next, referring to FIG. 5L, the pattern of the resist 14 is removed. Next, referring to FIG. 5M, the thin oxide film 51 formed on the active region is removed.

Next, referring to FIG. 5N, a gate oxide film 50 is formed on the main surface of each well 5, 6. Thereafter, a polysilicon layer 16 to become a gate electrode is formed over the entire surface of the semiconductor substrate 1 including the gate oxide film 50.

Next, referring to FIG. 50, the polysilicon layer 16 is patterned to form a gate electrode 17 on the N well 5,
A gate electrode 18 is formed on the P well 6.

Next, referring to FIG.
9, and using this pattern of resist 19 as a mask, boron ions are implanted into the N well 5. As a result, a source-drain region 20 is formed in the N-well 5, and as a result, a p-channel MO3FET is formed.
is formed.

Thereafter, the pattern of resist 19 is removed.

Next, referring to FIG. 5Q, the resist 2 is placed over the N well 5.
1, and using this pattern of resist 21 as a mask, arsenic ions are implanted into the P well 6.

As a result, the source/drain region 22 is placed inside the P well 6.
is formed, resulting in the formation of an N-channel MOSFET. After that, the pattern of the resist 21 is removed.

Next, referring to FIG. 5R, an insulating film 23 made of 5i02 is formed over the entire surface of the semiconductor substrate 1 including the gate electrodes 17 and 18.

Thereafter, referring to FIG. 5S, a contact hole 39 is formed in the insulating film 23 and wiring is performed using the aluminum metal 24, thereby completing CMO8FE,T.

FIG. 6 shows another conventional example of the CMO5FET manufacturing method disclosed in Japanese Unexamined Patent Publication No. 63-192268. In this conventional example, referring to FIG. 6, a technique is disclosed in which a well region 26 is formed in a semiconductor substrate 1 by ion-implanting well-forming impurity ions (B+ ions) into the semiconductor substrate 1 with high energy. has been done.

Further, according to this conventional example, the well region 26 and the channel stopper region 25 are formed simultaneously by using a specially shaped mask 27.

[Problems to be Solved by the Invention] The conventional CMO8FET manufacturing method is configured as described above. However, there were problems as described below.

That is, in the conventional example shown in FIGS. 5A to 5S, as shown in FIG. Treatment was necessary. In addition, in this conventional example, until the state shown in FIG. 5M is achieved, the fifth
Referring to Figure B, Figure 5G, Figure 5H, Figure 5J, and Figure 5, five photolithography steps were required.

Further, in the conventional example shown in FIG. 6, since no impurity is implanted into the channel region, there is a problem that punch-through of the transistor occurs when a MOSFET is formed.

Therefore, it is an object of the present invention to improve the method of manufacturing transistors in the well region so as to avoid transistor punch-through, and at the same time reduce the number of manufacturing steps and manufacturing time required for manufacturing. .

[Means for Solving the Problems] The present invention relates to a method of manufacturing a semiconductor device in which a well is formed in a semiconductor substrate and a transistor is formed on the main surface of the well. According to this method, first, a mask is formed on the main surface of a semiconductor substrate to expose a well formation region. Subsequently, using the mask, well-forming impurity ions are ion-implanted into the main surface of the well-forming region of the semiconductor substrate at a high energy that provides an impurity concentration distribution with a maximum concentration deeper than the transistor-forming region.

Next, using the above mask, impurities of the same conductivity type as the well-forming impurity ions are injected onto the main surface of the well-forming region of the semiconductor substrate at low energy to create an impurity concentration distribution in which the impurity stays in the channel-forming region of the transistor. Implant ions.

[Operation] According to the present invention, since the formation of a well and the implantation of channel ions are performed using the same mask, the number of photolithography steps is reduced.

In addition, when forming a well, well-forming impurity ions are implanted into the main surface of the well-forming region of the semiconductor substrate with high energy to give an impurity concentration distribution that reaches its maximum concentration deeper than the transistor-forming region. There is no need to thermally diffuse impurities. Hence,
The time for forming wells is reduced.

Further, since impurity ions of the same conductivity type as the well-forming impurity ions are also implanted into the channel region, punch-through of the transistor is prevented.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1A to 1G are cross-sectional views showing the well forming process according to the present invention.

Referring to FIG. 1A, an oxide film 2, a nitride film 3, and a resist 4 are sequentially formed on a semiconductor substrate 1 (for example, a p-silicon substrate).

Next, referring to FIG. 1B, in order to define the active region, the resist 4 is patterned by photolithography so that the pattern of the resist 4 remains on the active region. Subsequently, the nitride film 3 is patterned using the pattern of the resist 4. After that, the pattern of resist 4 is removed.

Next, referring to FIG. 1C, a thick isolation oxide film 7a is selectively formed on a portion of the semiconductor substrate 1 using the patterned nitride film 3 as a mask. The thickness of the isolation oxide film 7a is
It is set to about 5000A. After that, nitride film 3 is removed.

Next, referring to FIG. 1D, a pattern of resist 28 is formed at a position covering the N-well region to be formed. next,
Using the pattern of the resist 28 as a mask, boron was applied to the exposed main surface of the portion of the semiconductor substrate 1 where the P-well was to be formed, at an energy of 400 keV and a dose of 'lXl.
The first ion implantation is performed under the condition of 0" Cm-2 (7). When the implantation energy is selected in the range of 350 to 450 keV, the ions pass through the thick isolation oxide film 7a,
Impurities are also implanted into lower region 29 of isolation oxide film 7a. After that, the energy was 100 keV.

A second ion implantation is performed at the same position using the same mask (resist 28) under the condition of a dose of 1.times.10.sup.12 cm.sup.-2. The energy for performing the second ion implantation may be low enough to cause ions passing through the isolation oxide film 7a to be trapped in the isolation oxide film 7a, but is not limited thereto. Through these two ion implantations, a P well region 6 is formed in the semiconductor substrate 1. Second
Figure A shows the concentration distribution of the formed P-well region 6. Referring also to FIG. 2A, the depth of the P-well 6 is approximately 1.2 μm. It can be seen that the impurity concentration at the bottom of the P-well 6 is high.

Referring to FIG.
This means that the impurity concentration of No. 9 also becomes high. That is,
The region 29 below this isolation oxide film 7a is nothing but an isolation portion (ie, a channel stopper region) for preventing latch-up.

Continuously, using the same mask (resist 28), apply an energy of 50 keV and a dose of 2.5 x 10 to the same position.
" Boron ions are implanted under conditions of Cm-2. By this ion implantation, the channel region 1 of the transistor is
3, boron is injected. The boron implanted into the channel region 13 serves to prevent bunch-through of the transistor and also serves to adjust the threshold voltage. FIG. 2B shows the concentration distribution of the P-well region thus formed, and it can be seen that ions are also implanted into the channel region.

Note that by continuously increasing or decreasing the energy from 400 keV to 50 keV, a P-well having a uniform concentration distribution as shown in FIG. 2C is formed. When the concentration distribution in the P-well region becomes uniform in this way, punch-through can be prevented more efficiently.

After that, after removing the pattern of the resist 28,
Referring to the figure, resist 3 is placed at a position covering P-well region 6.
0 pattern is formed. Next, using the pattern of the resist 30 as a mask, an energy of 700 keV is applied to the exposed main surface of the portion of the semiconductor substrate 1 where the N-well is to be formed.
Under the condition of a dose of 1×1()11 cm−2, 1
Perform the second phosphorus ion implantation. Inject energy to 40
When the voltage is selected in the range of 0 to 120 OkeV, ions pass through the isolation oxide film 7a, and the lower region 31 of the isolation oxide film 7a
Phosphorus is also injected. After that, continue with energy 2
A second ion implantation of phosphorus is performed at the same position using the same mask (resist 30) under the conditions of 00 keV and a dose of 1×10 12 cm −2 . By performing these two ion implantations, an N well region 5 is formed in the semiconductor substrate 1. FIG. 3A shows the concentration distribution of the formed N-well region 5. Referring to FIG. 3A, the depth of N-well 5 is approximately 1.2 μm. It can be seen that the impurity concentration at the bottom of the N-well 5 is high.

Subsequently, using the same mask (resist 30), apply irradiation at the same position at an energy of 20 keV and a dose of 2°5×10”.
, cm-2, boron ions were implanted, and at the same time, the energy was 180 keV and the dose was 1.5 x 10".
Arsenic ions are implanted under am-2 conditions. Through this ion implantation, ions are implanted into the channel region 15 of the transistor. The boron and arsenic implanted into the channel region 15 serve to prevent punch-through of the transistor and also serve to adjust the threshold voltage. Note that the purpose of using boron in combination is to balance the threshold voltages of the respective transistors formed in the P well 6 and the N well 5. FIG. 3B shows the concentration distribution of the N-well region thus formed, and it can be seen that ions are also implanted into the channel region.

Note that by continuously increasing or decreasing the energy from 700 keV to 20 keV, an N-well having the concentration distribution shown in FIG. 3C is formed.

When the concentration distribution in the N-well region becomes uniform as shown in FIG. 3C, bunch-through can be prevented more efficiently.

Thereafter, referring to FIG. 1F, the pattern of the resist 30 is removed. Next, referring to FIG. 1G, thin oxide on the active region! 151 is removed. After that, Figures 5N to 5
By going through the conventional process shown in Figure S, CM
An OSFET is formed.

Although the embodiments have been described above using specific numerical values, the present invention is not limited thereto. The preferred conditions are
They are summarized in Table 1. In Table 1, Example 1 is a preferable condition when the thickness of the isolation oxide film is 5000A, and Example 2 is a preferable condition when the thickness of the isolation oxide film is 6000A.

(Margin below) In this embodiment, FIG. 1G (corresponds to FIG. 5M).

), the photoengraving process has reached the first stage.
Referring to FIG. B, FIG. 1D, and FIG. 1E, the process may be performed three times. Therefore, the number of photoengraving steps has been reduced to 2 compared to conventional methods.
This means that the number of times has decreased.

Further, when forming a well, conventionally a heat treatment for 6 to 8 hours was required to diffuse impurity ions, but the present invention does not require heat treatment for such a purpose. Therefore, manufacturing time is reduced.

FIG. 4 is a sectional view of another semiconductor device to which the present invention can be applied. The semiconductor device shown in FIG. 4 has a single conductivity type well. Referring to FIG. 4, a p+ layer 32 is formed on the main surface of semiconductor substrate 1 (for example, a p-silicon substrate).

An isolation oxide film 33 is formed on the main surface of the p+ layer 32 to isolate the transistor from other elements.

The transistor includes a source/drain region 34, a channel region 35, and a gate electrode 36 formed through a gate oxide film. An insulating film 37 is formed over the entire surface of the semiconductor substrate 1 including the gate electrode 36. A contact hole 39 is provided in the insulating film 37, and an aluminum metal 38 for wiring is connected to the source/drain 34.

In this embodiment, the ion implantation for the formation of p+ layer 32 and the ion implantation into channel region 35 are performed in the same manner and using the same mask as shown in FIG. 1D.

The present invention can be summarized as follows.

(1) The method according to claim 1, comprising:
A low energy ion implantation follows a high energy ion implantation.

(2) In the method described in item 1 above, the high-energy ion implantation and the low-energy ion implantation are performed successively by continuously decreasing the implantation energy.

(3) The method according to claim 1,
A high energy ion implantation follows a low energy ion implantation.

(4) In the method described in (3) above, high-energy ion implantation and low-energy ion implantation are performed successively by continuously decreasing the implantation energy.

(5) In the method described in (1) above, the high-energy ion implantation includes a step of implanting impurity ions at a first energy, and a step of implanting impurity ions at a second energy lower than the first energy. process.

(6) The method according to claim 1, comprising:
Prior to the mask forming step, the method further includes a step of forming an isolation oxide film on the main surface of the semiconductor substrate for electrically insulating and isolating the transistor formation region from other element formation regions.

(7) In the method described in (6) above, the high energy is energy large enough for the implanted impurity to pass through the isolation oxide film, and the low energy is the energy that the implanted impurity is trapped in the isolation oxide film. It is an energy of such magnitude that it is

(8) The method according to (7) above, wherein the well-forming impurity has p-type conductivity, the high energy is in the range of 250 to 550 keV, and the low energy is in the range of 10 to 550 keV. It is within the range of 3QkeV.

(9) In the method described in (7) above, the well-forming impurity has N-type conductivity, the high energy is in the range of 300 to 1500 keV, and the low energy is in the range of 100 to 220 keV. within range.

(10) Forming a second conductivity type well in the first conductivity type semiconductor substrate, forming a second conductivity type channel transistor on the main surface of the first conductivity type semiconductor substrate, and further forming a second conductivity type channel transistor on the main surface of the second conductivity type well. A method for manufacturing a complementary field effect transistor comprising forming a channel transistor of a first conductivity type on a main surface of the semiconductor substrate, the channel transistor forming region of the first conductivity type and the channel transistor of the second conductivity type. a step of forming an isolation oxide film on the boundary with the formation region for electrically insulating and isolating both regions; and a step of forming a mask on the main surface of the semiconductor substrate at a position covering one channel transistor formation region. using the mask to provide an impurity concentration distribution on the exposed main surface of the other channel transistor formation region of the semiconductor substrate that has a maximum concentration deeper than the transistor formation region; a step of ion-implanting a well-forming impurity using energy; A method for manufacturing a complementary field effect transistor, comprising: ion-implanting an impurity of the same conductivity type as a well-forming impurity at low energy to give an impurity concentration distribution in which the impurity remains in the well-forming impurity.

(11) The method according to item 10, further comprising the step of removing a mask covering one of the channel transistor formation regions, and the other channel transistor formation region on the main surface of the semiconductor substrate. forming a mask at a position that covers the semiconductor substrate; and using the mask to form a mask on the exposed main surface of one of the channel transistor formation regions of the semiconductor substrate, the concentration is at its maximum at a depth deeper than the transistor formation region. A step of ion-implanting well-forming impurities with high energy to give an impurity concentration distribution, and forming a channel of the transistor on the exposed main surface of one channel transistor formation region of the semiconductor substrate using the mask. A method comprising the step of ion-implanting an impurity of the same conductivity type as a well-forming impurity at low energy to provide an impurity concentration distribution in which the impurity remains on the main surface of the region.

[Effects of the Invention] As described above, according to the present invention, the formation of a well and the implantation of channel ions are performed using the same mask, so the number of photolithography steps is reduced.

Also, when forming wells, do you need to check if the semiconductor substrate is covered with sea urchins?
Well-forming impurity ions are implanted into the main surface of the well-forming region using high energy to give an impurity concentration distribution with a maximum concentration deeper than the transistor-forming region, so there is no need to thermally diffuse the impurities. Hence,
The time required for heat diffusion is reduced.

Furthermore, impurity ions of the same conductivity type as the well-forming impurity ions are implanted into the channel region, thereby preventing punch-through of the transistor.

[Brief explanation of drawings]

FIGS. 1A to 1G are cross-sectional views showing the steps of an embodiment of the present invention. FIGS. 2A to 2C illustrate P formed according to the present invention.
FIG. 3 is a diagram showing the distribution of impurity concentration in a well region. FIGS. 3A-3C illustrate N formed according to the present invention.
FIG. 3 is a diagram showing the distribution of impurity concentration in a well region. FIG. 4 is a sectional view of another semiconductor device to which the present invention is applied. FIGS. 5A to 5S are cross-sectional views showing the manufacturing process of a conventional CMOSFET. FIG. 6 is a sectional view showing still another conventional example of a well forming method. In the figure, 1 is a semiconductor substrate, 5 is an N well, 6 is a P well, 7a is an isolation oxide film, 13 is a channel region, and 15 is a channel region. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] A method for manufacturing a semiconductor device in which a well is formed in a semiconductor substrate and a transistor is formed on the main surface of the well, the method comprising: exposing a region where the well is to be formed on the main surface of the semiconductor substrate. a step of forming a mask, and using the mask to apply well-forming impurities to the main surface of the well-forming region of the semiconductor substrate with high energy to give an impurity concentration distribution having a maximum concentration deeper than the transistor-forming region; a step of implanting ions into the main surface of the well formation region of the semiconductor substrate using the mask at low energy to provide an impurity concentration distribution in which the impurity remains in the channel formation region of the transistor; A method for manufacturing a semiconductor device, comprising: a step of implanting impurity ions of the same conductivity type as;