JP2947816B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a retrograde well in a self-aligned manner.

[Prior Art] NMO in a semiconductor device with integrated MOS transistors
A CMOS semiconductor device configured by combining both transistors is more widely required than a circuit including only S or PMOS transistors because of its advantages such as low power consumption. In the CMOS structure, it is necessary to manufacture transistors of the opposite channel conductivity type on the same substrate, so that it is necessary to form a well of the opposite conductivity type to the channel conductivity type. Here, in such a CMOS type configuration, a parasitic bipolar transistor is inevitably formed, and a large current flows so much as to destroy the element due to noise on a power supply line. However, for this purpose, a retrograde well having a high concentration region at the bottom as an impurity profile is used because of its advantage of increasing latch-up resistance.

FIG. 5 shows a process of forming two conductivity type retrograde wells in a semiconductor device by high energy implantation according to a conventional method in order to form a CMOS structure.

First, a field oxide film 2 is formed on a silicon substrate 1 by a normal LOCOS (LOCal Oxidation of Silicon) method as shown in a sectional view of FIG.

Subsequently, as shown in FIG. 3B, a resist 4 is patterned on the p-well side to form a retrograde n-well 5, and an impurity for giving an n-type such as phosphorus (P ⁺ ) is applied at 600 keV.
Ion implantation is performed at a high energy such as 5 × 10 ^{12 to} 5 × 10 ¹³ cm ⁻² .

Next, the resist 4 patterned in FIG. 3B is removed, and a resist 6 is patterned on the n-well side to form a retrograde p-well 7 and impurities such as boron (B ⁺ ) for giving a p-type are 200 keV or the like. High energy, 5 × 10 ¹² 〜5
Ion implantation is performed by implantation at an implantation amount of about × 10 ¹³ cm ⁻² , and then the resist 6 is removed.

[Problems to be solved by the invention]

In a conventional CMOS fabrication flow of a retrograde well by high energy implantation, a photolithography process has to be performed twice to form a well, and the process becomes longer, resulting in a problem of mask displacement. Further, in order to use high-energy implantation, it is necessary to pattern a resist having a thickness of 3 μm, which makes it difficult to control dimensions and fine patterning.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and a well has been formed in a self-aligned manner to shorten a well process, and has a CMO having a high-performance MOS transistor.
It is an object of the present invention to obtain a method capable of manufacturing a semiconductor device having an S configuration.

[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a CMOS structure, wherein a first conductivity type well and a second conductivity type are formed following a field oxidation step of a semiconductor substrate. Forming the mold well; patterning a resist for forming the first conductivity type well; ionizing the impurity of the first conductivity type well to a high concentration once or plural times by using the resist as a mask; After the step of injecting and removing the resist, the entire surface is reverse to the first conductivity type through a field oxide film formed in the isolation region and an oxide film formed with a uniform thickness in the active region. Ion-implanting the impurity of the second conductivity type well once or a plurality of times to a concentration lower than that of the impurity of the first conductivity type well. The ion implantation of the impurity in the well and the ion implantation of the impurity in the second conductivity type well are performed by the impurity concentration in the vicinity of the semiconductor substrate surface of the first conductivity type well and in the vicinity of the semiconductor substrate surface of the second conductivity type well. Is performed so that the semiconductor substrate has the same impurity concentration as the impurity of the first conductivity type well and the impurity concentration of the second conductivity type well before the impurity ion implantation.

[Operation] In the method for manufacturing a semiconductor device according to the present invention, after forming a field oxide film, a first conductivity type well is formed using a mask, and after removing the mask, the field oxide formed in the isolation region is removed. The impurity of the second conductivity type well opposite to the first conductivity type is ion-implanted over the entire surface through an oxide film formed with a uniform thickness on the film and the active region, thereby forming a first region.
Since a well of the conductivity type and a well of the second conductivity type are formed,
Since the photolithography process only needs to be performed once, the well can be formed in a self-aligned manner, and the process can be shortened. In addition, the surface concentration of the semiconductor substrate in the active region can be made substantially equal to the impurity concentration before the well is formed. .

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a method of forming a retrograde well of two conductivity types according to an embodiment of the present invention, and the method will be described below.

First, as shown in FIG. 1A, a normal LOCOS method (LOCal Oxidati
on of Silicon; a method of patterning a nitride film on an underlying oxide film and oxidizing the substrate using this as a mask)
A field oxide film 2 is formed, and an active region 3 for forming an element such as a transistor in a later step is defined. Here, an underlying oxide film having a thickness of about 300 ° remains on active region 3.

Next, as shown in FIG. 3B, the resist 4 is patterned to form a retrograde n-well 5.

Thereafter, phosphorus (P ⁺ ) implantation is performed a plurality of times at a high energy of about 600 keV while changing the energy and the implantation amount to form a retrograde n-well 5. At this time ~ 1000 from the surface
In order not to increase the well impurity concentration in a shallow region of about Å, low-energy implantation is not performed, and the entire implantation is performed. The implantation amount is the following boron (B ⁺ ) implantation amount, specifically, 5 × Double the injection amount of about 10 ^{12 to} 5 × 10 ¹³ cm ^-2 .

Next, as shown in FIG. 5C, after removing the resist 4 shown in FIG. 5B, boron (B ⁺ ) is applied at about 200 keV to form a retrograde p-well 7 over the entire surface of the substrate. The implantation is performed a plurality of times at a high energy while changing the energy and the implantation amount. However, similarly to the above, the low energy implantation is not performed so as not to increase the well impurity concentration near the surface. The injection amount here is half the injection amount of phosphorus (P ⁺ ), that is, about 5 × 10 ^{12 to} 5 × 10 ¹³ cm ⁻² as in the conventional method. A similar impurity concentration profile is obtained.

As a result, the n-well formed in FIG. 1 (b) is implanted more heavily than in the conventional method, but the impurity concentration giving the opposite conductivity type in FIG. 1 (c) becomes an appropriate impurity concentration similar to that of the conventional method. , The required two conductivity type retrograde wells can be formed.

The solid line in FIG. 2 (a) is a retrograde n-well 5 made at a higher concentration than the conventional method after the step of FIG. 1 (b).
The impurity concentration profile under the active region 3 is shown, and the impurity concentration is lowered near the surface. The dotted line in FIG. 2 (a) shows a well impurity concentration profile in which the well concentration has increased to the substrate surface in the conventional method.

FIG. 2 (b) shows the impurity concentration profile of the retrograde p-well 7 according to the conventional concentration after the step of FIG. 1 (c), and the impurity concentration near the surface is reduced. FIG. 2 (c) shows the impurity concentration profile of the retrograde n-well 5 after the step of FIG. 1 (c), and the profile shown by the solid line in FIG. 2 (a) which is the profile before the step. It can be seen that the density was canceled out and the density became appropriate.

After completion of the above-described process, an impurity giving n-type near the substrate surface where the channel of the MOS transistor is formed and
The total amount of impurities that give the mold is small, and even if an operation is performed to adjust the well concentration with impurities that give the opposite conductivity type.
The performance of the MOS transistor does not deteriorate.

FIG. 3 shows a method of forming a retrograde well of two conductivity types according to a second embodiment of the present invention, and the method of the second embodiment will be described below.

In FIG. 3A, a field oxide film 3 is formed on a p-type silicon substrate 31 by a normal LOCOS method for element isolation.
2 is formed, and an active region 33 for forming an element such as a transistor in a later step is defined. Here the thickness on the active area 33
The underlying oxide film 32 of about 300 mm remains.

Next, the resist 34 is patterned to form a retrograde n-well.

Thereafter, a retrograde n-well (38 in FIG. 3D) is formed by phosphorus (P ⁺ ) implantation using the resist 34 as a mask.

Next, as shown in FIG. 3C, after removing the resist 34 shown in FIG. 3B, boron (B ⁺ ) is implanted into the entire surface of the substrate to form a retrograde p-well (FIG. 3D). To form 39).

Here, the retrograde n-well and the retrograde p-well are formed by the following method.

The formation of such a well is performed by high energy implantation of P ⁺ exceeding 600 keV or B ⁺ in order to prevent the portion (34a) under the field oxide film from being easily inverted as shown in FIG. The impurity layer 34 is formed by high energy implantation exceeding 200 keV. The implantation amount at this time is such that the applied voltage to the wiring material deposited on the field oxide film 32 causes an inversion layer below the field oxide film 32 to have an appropriate potential that is not so high. That is, the implantation dose may be such that the concentration immediately below the field oxide film 32 is 1 × 10 ¹⁷ cm ⁻³ . As a result, the junction capacitance can be reduced. Subsequently, in order to form a high concentration region 37 at the bottom part peculiar to the retrograde well, P ⁺ ion implantation is performed at a high energy of 3 MeV or the like, or B ⁺ ion implantation is performed at a high energy of 2 MeV or the like at about 2 to 4 μm. Done to the depth. A high concentration region 37 is formed.

Next, as shown in FIG.
The impurity concentration of the shallower region 36 is increased, low energy of P ⁺ of 600 keV or less or low energy of B ⁺ of 200 keV or less is performed one or more times. To increase the concentration of the intermediate region 35 between the concentration region 37 and P ⁺ with an energy of 600 keV or more and 3 MeV or less, or of B ⁺ with an energy of 200 keV or more and 2 MeV or less, 1
One or more ion implantations are performed.

Subsequently, in the step of FIG. 4D, an annealing process is performed to activate the injection layer performed in FIGS. 5B and 5C.

4A shows an impurity concentration profile below the field oxide film 32 of the silicon substrate 31 processed according to FIG. 3, and FIG. 4B shows an impurity concentration profile below the active region 33. By using the well forming method, a deep well is formed as compared with FIG.

The formation of the retrograde n-well as described above was carried out at twice the concentration of FIG.
By forming the well at the concentration shown in FIG.
2 as well as the p-well 39 formed in the step of FIG. 3C, and the n-well 38 formed in the steps of FIG. 3B and FIG. , And the required two conductivity type retrograde wells can be formed.

In the above embodiment, the p-type substrate is used. However, an n-type substrate may be used. Alternatively, the n-well may be formed first, but the p-well may be formed first more densely.

[Effects of the Invention] As described above, in the method of manufacturing a semiconductor device according to the present invention, the photolithography process for forming the well only needs to be performed once, and the well can be formed in a self-aligned manner. In addition to shortening, the impurity concentration of the channel forming portion on the surface of the semiconductor substrate in the active region can be made substantially the same as the impurity concentration before the well is formed. This has the effect of improving the performance of the device.

[Brief description of the drawings]

FIG. 1 is a diagram showing a manufacturing method according to a first embodiment of the present invention. FIG. 2 is a diagram showing a well impurity profile when the method of FIG. 1 is used. FIG. 3 is a view showing a manufacturing method according to a second embodiment of the present invention. FIG. 4 is a diagram showing an impurity profile of a well when the method of FIG. 3 is followed. FIG. 5 is a diagram showing a conventional manufacturing method. 1,31 is a silicon substrate, 2,32 is a field oxide film, 3,33 is an active region, 4,34 is a resist, 5,38 is a retrograde n-well, 6,34 is a resist, and 7,39 is a retrograde p Wells, 34 and 34a are injection layers, 35 is an intermediate region, 36 is a shallow region, 37
Is a high concentration region. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] In a method of manufacturing a semiconductor device having a CMOS structure, a step of forming a first conductivity type well and a second conductivity type well following a field oxidation step of a semiconductor substrate includes the step of forming the first conductivity type well. A step of patterning a resist for forming; a step of ion-implanting the impurity of the first conductivity type well once or a plurality of times with a high concentration using the resist as a mask; Impurities of the second conductivity type well opposite to the first conductivity type are doped over the entire surface via the formed field oxide film and the oxide film formed with a uniform thickness on the active region. Implanting ions one or more times at a concentration lower than that of the impurities; ion-implanting impurities in the wells of the first conductivity type; The ion implantation of the impurity is performed by adjusting the impurity concentration in the vicinity of the semiconductor substrate surface of the first conductivity type well and in the vicinity of the semiconductor substrate surface of the second conductivity type well. And a method of manufacturing the semiconductor device, wherein the impurity concentration of the second conductivity type well is set to be substantially the same as the impurity concentration before ion implantation of the impurity.