JP3430102B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having different threshold voltages in the same chip and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, some LSI circuits have different threshold voltages in the same chip. In this type of LSI circuit, generally, the threshold voltage is controlled by changing the substrate impurity concentration immediately below the gate electrode by ion implantation or the like using an additional mask.

Further, a technique of changing the threshold voltage by changing the film thickness of the gate oxide film is also used.

Further, in order to reduce the resistance of the gate electrode made of polycrystalline silicon, a two-layered gate in which a metal (for example, tungsten or titanium is sputtered and silicidized by heat treatment) is applied to the polycrystalline silicon. -For a semiconductor device forming the gate electrode, the threshold value is changed by changing the relationship between the film thickness of the polycrystalline silicon of the gate electrode and the film thickness of the metal deposited on the surface of the polycrystalline silicon. Techniques such as controlling the voltage within a range defined by changes in the work function value are used.

On the other hand, Japanese Unexamined Patent Publication No. 8-213476 discloses a semiconductor device in which N-type and P-type conductive polysilicon is used for the gate electrodes of an NMOS transistor and a PMOS transistor, respectively.
There is disclosed a method of manufacturing a semiconductor device in which transistors having different threshold voltages are simultaneously manufactured by using P-type (or N-type) gates for S) transistors.

[0006]

In any of the above-described conventional semiconductor devices and the method of manufacturing the same, an additional process or an additional mask is required, resulting in a long manufacturing time and a high manufacturing cost. In the conventional transistor, when the polarity of the gate electrode and the polarity of the substrate of the transistor are the same, the threshold voltage is lowered by channel doping, so that it becomes a buried channel type. There have been problems such as a decrease in threshold voltage due to the effect, (2) deterioration in subthreshold characteristics, and (3) decrease in punch-through withstand voltage.

In the prior art disclosed in Japanese Unexamined Patent Publication No. 8-213476, an N-gate NMOS transistor,
Since the P-gate PMOS transistor, the P-gate NMOS transistor, and the N-gate PMOS transistor are arranged adjacent to each other via the field oxide film, a PMO having a P-type gate electrode and an N-type gate electrode is provided.
It is difficult to achieve miniaturization as compared with the case where an S transistor and an NMOS transistor having a P-type gate electrode and an N-type gate electrode are arranged adjacent to each other. Moreover, since the ion implantation into the gate electrode and the ion implantation into the source / drain are performed in different steps, the manufacturing time becomes longer and the manufacturing cost increases accordingly.

An object of the present invention is to have different threshold voltages in the same chip and to configure all of them with surface channel transistors, so that the threshold voltage is lowered due to the short channel effect, the subthreshold characteristic is deteriorated, and the punch-through transistor is punched. −
It is an object of the present invention to provide a semiconductor device which can reduce breakdown voltage and the like and can be miniaturized.

Another object of the present invention is to provide a method of manufacturing a semiconductor device which can manufacture semiconductor devices having different threshold voltages in the same chip without requiring additional steps and masks. Especially.

[0010]

According to a first method for manufacturing a semiconductor device of the present invention, an N well diffusion layer and a P well diffusion layer are formed adjacent to each other, and the N well diffusion layer and the P well diffusion layer are formed on the N well diffusion layer and the P well diffusion layer. A step of forming a gate electrode, masking a source region and a drain region of the PMOS transistor to be formed in the N well diffusion layer, and a gate electrode other than a gate electrode to be P-type with a mask, A step of implanting a P-type impurity at the same time, a source region and a drain region of the NMOS transistor to be formed in the P-well diffusion layer, and a gate electrode other than the gate electrode to be N-type are masked with a mask, and the opening of the mask is formed. Through the step of simultaneously implanting N-type impurities from the source region and the drain to form sidewalls on both sides of the gate electrode after forming the gate electrode. The width of the mask used to inject the impurity into the region is formed so as to deviate from both sides of the gate electrode to ½ of the width of the sidewall, and the mask used to inject the impurity into the gate electrode. The width of the opening is formed so as to be shifted from both sides of the gate electrode to ½ of the width of the sidewall.

A second method of manufacturing a semiconductor device according to the present invention is
An N well diffusion layer and a P well diffusion layer are formed adjacent to each other,
Forming a polycrystalline silicon gate electrode having a low concentration N-type impurity introduced therein and a polycrystalline silicon gate electrode having a low concentration P-type impurity introduced into the N well diffusion layer and the P well diffusion layer; The source region and drain region of the PMOS transistor to be formed in the N well diffusion layer and the gate electrode other than the gate electrode to be made P type at high concentration are masked with a mask, and P type impurities are simultaneously injected from the opening of the mask. And the NM to be formed in the P-well diffusion layer
A source region and a drain region of the OS transistor, and a step of masking a portion other than the gate electrode to be made N-type at high concentration with a mask, and simultaneously implanting N-type impurities from the opening of the mask, After forming the gate electrode, sidewalls are formed on both sides of the gate electrode, and the width of the mask used for implanting impurities into the source region and the drain region covers the gate electrode from both sides of the gate electrode. The width of the opening of the mask used for implanting impurities into the gate electrode is shifted to ½ of the width, and the width of the opening of the mask is shifted to ½ of the width of the sidewall from both sides of the gate electrode. , Is characterized.

[0012]

[0013]

[0014]

[0015]

[0016]

[0017]

[0018]

[0019]

According to the method of manufacturing a semiconductor device of the present invention,
A semiconductor device having different threshold voltages can be manufactured in the same chip by performing ion implantation into the gate electrode and ion implantation into the source / drain at the same time without requiring an additional step and a mask. .

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. As shown in FIG. 1, a semiconductor device according to an embodiment of the present invention includes a P-type silicon substrate 1, N-well diffusion layers 2 and P formed on the P-type silicon substrate 1 and adjacent to each other. A well diffusion layer 3, a P-gate PMOS transistor 100 and an N-gate PMOS transistor 101 formed in the N-well diffusion layer 2,
A P-gate NMOS transistor 200 and an N-gate NMOS transistor 201 formed in the P-well diffusion layer 3
And.

That is, in each transistor of the present invention,
Even in the same NMOS transistor, a P-gate NMOS transistor 200 having a P-type gate electrode 71 and an N-gate NMOS transistor 201 having an N-type gate electrode 72 are provided.
And the same PMOS transistor is provided with the P-gate PMOS transistor 100 and the N-type PMOS transistor 100 having the P-type gate electrode 71.
It is composed of four types of transistors, an N-gate PMOS transistor 101 having a type gate electrode 72.

A source diffusion layer 4, a drain diffusion layer 5, and a gate oxide film 6 are formed in each transistor.

In the case of this embodiment, the threshold voltage is 0.2.
~ 0.4V (absolute value) NMOS transistor and PMOS transistor, and threshold voltage 1V (absolute value)
Some NMOS transistors and PMOS transistors are formed in the same chip. The value of the threshold voltage is an example and is not limited to this.

FIGS. 2A and 2B are simulations of the substrate bias characteristics (substrate bias (V) -threshold voltage (V)) in each transistor of the semiconductor device according to the embodiment of the present invention. It is a graph which shows the result.

FIG. 2A shows the substrate bias characteristics of the NMOS transistor. Where ● is N-gate NMOS
The substrate bias characteristics of the transistor 201 are shown, and ■ represents P
The substrate bias characteristic of the gate NMOS transistor 200 is shown. As can be seen from FIG. 2 (A), N gate NMO
The P-gate NMOS transistor 200 is higher than the S-transistor 201 by about 1V when the substrate bias is 0V (threshold voltage).

FIG. 2B shows the substrate bias characteristics of the PMOS transistor. Where ● is P-gate PMOS
The substrate bias characteristics of the transistor 100 are shown, and ■ represents N
The substrate bias characteristic of the gate PMOS transistor 101 is shown. As can be seen from FIG. 2B, the P gate PMO
The N-gate PMOS transistor 101 is higher than the S-transistor 100 by about 1V when the substrate bias is 0V (threshold voltage).

In this way, the NMOS transistor 20
0, 201 and the PMOS transistors 100, 101 have the same channel doping, but the substrate bias characteristics are different between the NMOS transistors 200, 201 and the PMOS transistors 100, 101.

Here, the result of the simulation shown in FIG. 2 will be briefly described. The threshold voltage of the MOS transistor is expressed by the following formula, but VT can be controlled by changing any of the parameters. In the present invention, the work function φMS is changed and different transistors are formed on the same chip.

VT = φMS-Qss / Co + 2φf-((2ε
iεoqNsub (| 2φf | + Vsub)) ^1/2 / Co) where φMS: work function between gate electrode and silicon substrate Qss: interface state density Co: gate capacitance per unit area φf: Fermi potential [epsilon] i: relative permittivity of gate oxide film [epsilon] o: permittivity in vacuum q: electron charge amount Nsub: substrate impurity concentration Vsub: substrate bias voltage First, the PMOS transistor will be described. The P-gate PMOS transistor 100 formed on the N-well diffusion layer 2 has a large work function difference between the P-type gate electrode 71 and the N-well diffusion layer 2 and thus has a low threshold voltage. However, the N formed on the same N well diffusion layer 2
In the gate PMOS transistor 101, since the work function difference between the N-type gate electrode 72 and the N well diffusion layer 2 is small, the threshold voltage increases in the negative direction. For this reason,
In general, the N-gate PMOS transistor 101 becomes a buried channel type because impurities of a conductivity type opposite to that of the substrate are doped in the channel region in order to reduce the absolute value of the threshold voltage. In this embodiment, the surface channel type is used and a relatively high threshold value is required due to the characteristics of the circuit, so that it is used without channel doping.

Similarly, in the NMOS transistor 200, the P-gate NMOS transistor 200 has a small work function difference between the P-type gate electrode 71 and the P-well diffusion layer 3, so that the threshold voltage becomes high and the N-gate becomes negative. Since the NMOS transistor 201 has a large work function difference between the N-type gate electrode 72 and the P well diffusion layer 3, the threshold voltage becomes low.

That is, the N-gate NMOS transistor 201 or the P-gate PMOS transistor 100, which has a large work function difference by utilizing the work function difference, is connected to the channel gate.
P-gate NMOS transistor 200 or N-gate PMOS having a small work function difference due to a surface channel type transistor having a threshold value of about 0.2 to 0.4 V.
Since the transistor 101 has the same substrate concentration as the N-gate NMOS transistor 201 or the P-gate PMOS transistor 100, the threshold voltage is 1 in absolute value.
It becomes a surface channel type transistor of about V.

Here, the necessity of the surface channel type transistor is shown below. The transistor of each channel is N
By providing the p-type and p-type gate electrodes, the threshold voltage is changed by the difference in work function φms between the gate electrode and the silicon substrate without changing the substrate impurity concentration Nsub. For this reason, since all the transistors are formed by the surface channel type, it is possible to reduce the drawbacks of the buried channel type, such as the lowering of the threshold voltage, the deterioration of the subthreshold characteristics, the lowering of the punch-through breakdown voltage, and the like.

FIG. 2C shows the dependence of the gate electrode concentration on the threshold voltage of the NMOS transistor.
It is a graph which shows the result of having carried out. Here, ● indicates the gate electrode concentration of the N-gate NMOS transistor 201, and ■ indicates the gate electrode concentration of the P-gate NMOS transistor 200. As can be seen from FIG. 2C, even if the substrate concentration (N well and P well concentration) is constant,
It can be seen that the threshold voltage can be controlled by changing the impurity concentration of the gate electrode.

Next, a method of manufacturing the semiconductor device of the present invention will be described with reference to FIG.

First, an N well diffusion layer 2 and a P well diffusion layer 3 are formed on a P type silicon substrate 1 so as to be adjacent to each other. Then, polycrystalline silicon is deposited through the gate oxide film 6 and a gate electrode is formed by an etching technique (see FIG. 3A).

Then, the source for forming the PMOS transistor and the drain and the gate electrode other than the gate electrode to be P-type are masked with a resist 8 by using a lithographic technique, and P-type impurities such as fucabolone (BF ₂ ) are masked. Ion implantation is performed with energy of 30 KeV and dose of 3.0E15 cm ^-2 (see FIG. 3B).

Next, the resist 8 which is a mask material is peeled off (see FIG. 3C).

Next, except for the source and the drain for forming the NMOS transistor, and the gate electrode to be made N-type, masking is performed with a resist 8 using the same lithography technique, and arsenic (As) which is an N-type impurity is used. Energy-50
Ion implantation is performed with KeV and a dose amount of 1.5E15 cm ⁻² (see FIG. 3D).

Next, the resist 8 which is a mask material is peeled off (see FIG. 3E). As a result, the semiconductor device according to the embodiment of the present invention is completed.

FIGS. 4A and 4B are explanatory views for explaining the arrangement of masks used in the method of manufacturing a semiconductor device according to the embodiment of the present invention. Figure 4 (A)
Shows a schematic cross-sectional view when the mask 9 used for forming the source and the drain and the P-type silicon substrate 1 are aligned with each other. Although it depends on the type of resist (positive type or negative type), in the present embodiment, it is assumed that impurities are introduced into the place where the mask does not exist, the gate width dimension L1 is 0.35 μm, and the MOS transistor is LDD (lightly) for relaxing the electric field near the drain of the
Targeting devices with a Doped Drain structure,
The width of the side wall 10 of the transistor is 0.0 times as large as the displacement amount L2 (about 0.04 μm) from the gate electrode which occurs during the exposure process of forming the source and drain.
8 to 0.1 μm is provided. In addition, sidewall 1
0 is formed by depositing polysilicon on the entire surface of the wafer, patterning it, processing the gate electrode by etching, then depositing an overall oxide film, and performing an etch bag. The shift amount of 0.04 μm is generally the maximum shift amount in a device having a gate size of 0.35 μm.

In the source and drain forming process, the mark constituted by the gate electrode 70 is aligned (not shown), and the standard deviation amount at that time is 0.04 μm. Therefore, the mask size L3 for masking the gate electrode 70 is 0.35 μm for the gate electrode + 0.04 μm for the shift amount × 2 = 0.43 μm. Gate electrode 7
No impurities are introduced into 0, and impurities are introduced into only the source and the drain.

FIG. 4B shows a schematic cross-sectional view when the mask 9 used when implanting impurities only in the gate electrode 70 and the P-type silicon substrate 1 are aligned with each other. Also in this case, the mask 9 has a gate electrode 0.35 μm + deviation 0.04 μm × 2 = 0.43 μm with respect to the gate electrode 70.
By opening with the size L4, impurities are introduced only into the gate electrode 70, and no impurities are introduced into the source and the drain. In any case, it can be seen that the side wall 10 configured with a width twice the amount of displacement plays an important role.

After that, the impurities are uniformly diffused in the gate electrode 70 by the anneal after introducing the impurities into the gate electrode 70.

However, since the exposure apparatus used in the actual LSI manufacturing uses the reduction projection exposure apparatus, the mask is 5
It is about 10 times larger.

Next, a method of changing the concentration of the gate electrode will be described. For example, if the gate electrode of N-type polycrystalline silicon doped at a low concentration is masked so that impurities for forming a source and a drain do not enter, a low concentration N gate NMOS transistor or a low concentration Concentration N Gate PM
An OS transistor can be formed. Similarly, if P-type polycrystalline silicon doped in a low concentration is used as a gate electrode, a low concentration P gate NMOS transistor or a low concentration P gate PMOS transistor can be formed. Also,
A P-type impurity is implanted at a high concentration into the gate electrode to be P-type, and an N-type impurity is simultaneously implanted at a high concentration into the gate electrode to be N-type.

As described above, according to another method of manufacturing a semiconductor device of the present invention, a high-concentration N gate, a low-concentration N gate transistor, and a high-concentration N gate transistor and a high-concentration transistor are not required. The high-concentration P-gate and low-concentration P-gate transistors can be formed as surface channel type NMOS transistors and PMOS transistors.

As described above, since the polarity or concentration of the gate electrode is changed together with the step of forming the source and drain regions of the transistor, there is no additional step even in the same chip, and the low threshold is obtained. A surface channel type transistor which can obtain a value voltage and a high threshold voltage can be formed.

The present invention is not limited to the above-mentioned embodiment, and various modifications can be made within the scope of the technical matters described in the claims. For example, boron or the like may be used as the P-type impurity, and phosphorus or the like may be used as the N-type impurity. Further, as disclosed in Japanese Patent Laid-Open No. 8-213476, an N gate NMOS transistor, a P gate PMOS transistor, and a P gate NMOS are manufactured by using the method for manufacturing a semiconductor device of the present invention.
It is also possible to manufacture a semiconductor device in which a transistor and an N-gate PMOS transistor are adjacently arranged in this order.

[0050]

According to the semiconductor device of the present invention, an NMOS transistor and a PMOS transistor having a low threshold voltage of about 0.2 to 0.4 V and a high threshold voltage of about 1 V are provided in the same chip. PM transistors and gate transistors with different gate electrodes in the same chip
Since the OS transistor can be configured as a surface channel type transistor, it is possible to reduce a decrease in threshold voltage due to a short channel effect, deterioration of subthreshold characteristics, a decrease in punch-through breakdown voltage, and the like.

Further, by changing the impurity concentration of the gate electrode, more threshold voltage can be obtained.

Furthermore, since the PMOS transistor having the P-type gate electrode and the N-type gate electrode and the NMOS transistor having the P-type gate electrode and the N-type gate electrode are arranged adjacent to each other, the P-gate PMOS transistor and the N-type Between gate PMOS transistor and P gate NM
No field oxide film (element isolation region) is required between the OS transistor and the N-gate NMOS transistor,
Further miniaturization can be achieved as compared with the semiconductor device disclosed in Japanese Patent Laid-Open No. 8-213476.

According to the method of manufacturing a semiconductor device of the present invention,
A semiconductor device having different threshold voltages can be manufactured in the same chip by performing ion implantation into the gate electrode and ion implantation into the source / drain at the same time without requiring an additional step and a mask. Therefore, it is possible to reduce the manufacturing time and the manufacturing cost.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.

2A and 2B are simulations of substrate bias characteristics (substrate bias (V) -threshold voltage (V)) in each transistor of the semiconductor device according to the embodiment of the present invention. It is a graph which shows a result, (C) is
6 is a graph showing the result of simulating the gate electrode concentration dependence on the threshold voltage of an NMOS transistor.

FIG. 3 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 4A and FIG. 4B are explanatory views for explaining the arrangement of masks used in the method for manufacturing a semiconductor device according to the embodiment of the present invention.

[Explanation of symbols]

1: P-type silicon substrate 2: N well diffusion layer 3: P-well diffusion layer 4: Source diffusion layer 5: Drain diffusion layer 6: Gate oxide film 70: Gate electrode 71: P-type gate electrode 72: N-type gate electrode 8: Resist 9: Mask 10: Sidewall 100: P-gate PMOS transistor 101: N-gate PMOS transistor 200: P-gate NMOS transistor 201: N-gate NMOS transistor

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Claims (2)

(57) [Claims] 1. A step of forming an N well diffusion layer and a P well diffusion layer adjacent to each other, and forming a gate electrode on the N well diffusion layer and the P well diffusion layer; and forming a gate electrode on the N well diffusion layer. Forming a source region and a drain region of the PMOS transistor and a gate electrode other than the gate electrode to be P-type with a mask, and simultaneously implanting P-type impurities from the opening of the mask. A source region and a drain region of the NMOS transistor to be made, and a mask other than the gate electrode to be made N-type with a mask, and simultaneously implanting N-type impurities from the opening of the mask, After forming the electrode, sidewalls are formed on both sides of the gate electrode, and a gate electrode of a mask used when implanting impurities into the source region and the drain region is formed. The covering width is formed so as to deviate from both sides of the gate electrode to ½ of the width of the sidewall, and the width of the opening of the mask used for implanting impurities into the gate electrode is the width of the sidewall from both sides of the gate electrode. Of 2
A method of manufacturing a semiconductor device, wherein the semiconductor device is formed with a shift of one-half. 2. A N-well diffusion layer and a P-well diffusion layer are formed adjacent to each other, and a low-concentration polycrystalline silicon gate electrode and a low-concentration N-type impurity introduced into the N-well diffusion layer and the P-well diffusion layer are provided. A step of forming a gate electrode of polycrystalline silicon having a high concentration of p-type impurities introduced therein, a source region and a drain region of the PMOS transistor to be formed in the n-well diffusion layer, and a gate region to be highly concentrated to be p-type. -A mask other than the gate electrode is masked and a P-type impurity is simultaneously injected through the opening of the mask; a source region and a drain region of an NMOS transistor to be formed in the P well diffusion layer; Masking parts other than the gate electrode to be patterned with a mask, and simultaneously implanting N-type impurities from the opening of the mask, and after forming the gate electrode, the gate electrode is formed. The sidewalls are formed on both sides of the electrode, and the width of the mask used for implanting impurities into the source region and the drain region covers the gate electrode from both sides of the gate electrode to ½ of the width of the sidewall. The width of the opening of the mask, which is formed by implanting impurities into the gate electrode, is 2 times the width of the sidewall from both sides of the gate electrode.
A method of manufacturing a semiconductor device, wherein the semiconductor device is formed with a shift of one-half.