JP2000174218A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the breakdown voltage, reduce the on-resistance, and at the same time achieve high integration. SOLUTION: In a semiconductor device, a source region 4, a channel region 8, and a drain region 5 are provided. Further, a gate electrode 7 is formed on the channel region 8, and a plurality of configurations consisting of an N- layer (drift region) 22 that is formed shallowly (a first N- layer 22A) below the gate electrode 7 and deeply (a second N- layer 22B) near the drain region 5 between the channel region 8 and the drain region 5 are provided via an element separation film 9A. In the semiconductor device, a channel stopper layer 38 is formed below the element separation film 9A.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to an LD (Lateral Double) as a high-voltage element used in, for example, a liquid crystal driving IC.
Diffused) MOS transistor technology.

[0002]

2. Description of the Related Art Here, the LDMOS transistor structure means that a diffusion region formed on the surface side of a semiconductor substrate is diffused with an impurity having a different conductivity type to form a new diffusion region. The difference in the lateral diffusion is used as the effective channel length. By forming a short channel, the element is suitable for low on-resistance.

FIG. 12 is a cross-sectional view for explaining a conventional LDMOS transistor, and shows an N-channel type LDMOS transistor structure as an example. Although the description of the structure of the P-channel LDMOS transistor is omitted, it is well known that the structure is the same except for the conductivity type.

In FIG. 12, reference numeral 1 denotes one conductivity type, for example, P
A semiconductor substrate 2 is an N-type well region, in which a P-type body region 3 is formed in the N-type well region 2 and an N-type diffusion region 4 is formed in the P-type body region 3. And an N-type diffusion region 5 in the N-type well region 2.
Are formed. A gate electrode 7 is formed on the substrate surface with a gate insulating film 6 interposed therebetween, and a channel region 8 is formed in a surface region of the P-type body region 3 immediately below the gate electrode 7.
Are formed.

The N-type diffusion region 4 is a source region, the N-type diffusion region 5 is a drain region, and the N-type well region 2 below the LOCOS oxide film 9A is a drift region. Reference numerals 10 and 11 denote a source electrode and a drain electrode, respectively, reference numeral 12 denotes a P-type diffusion region for taking the potential of the P-type body region 3, and reference numeral 13 denotes an interlayer insulating film.

In the above LDMOS transistor,
By forming the N-type well region 2 by diffusion, the concentration on the surface of the N-type well region 2 is increased, so that the current easily flows on the surface of the N-type well region 2 and the breakdown voltage can be increased. The LDMOS transistor having such a configuration is called a surface relaxation type (RESURF) LDMOS, and the dopant concentration of the drift region of the N-type well region 2 is set so as to satisfy the RESURF condition. Such a technique is disclosed in Japanese Patent Application Laid-Open No. 9-139438.

[0007]

However, FIG.
As shown in (1), the N-type well region 2 is uniformly formed to the same depth position, which hinders further increase in breakdown voltage and reduction in on-resistance.

Further, as shown in FIG.
When a plurality of MOS transistors are arranged side by side via the element isolation film 9B, the size of the element isolation film 9B for isolating adjacent transistors becomes longer, which hinders high integration. That is, the element isolation film 9
Since the N-type well region 2 adjacent via B is formed by a well-known well diffusion process, the N-type well region 2 has a large spread in the lateral direction and a large depletion layer.
2 (approximately 10 μm to 30 μm).

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a semiconductor device which can meet the demand for higher breakdown voltage and lower on-resistance and which can be highly integrated, and a method of manufacturing the same.

[0010]

In order to solve the above-mentioned problems, the present invention has a source region 4, a channel region 8 and a drain region 5, and a gate electrode 7 is formed on the channel region 8. Between the channel region 8 and the drain region 5, at least below the gate electrode 7, shallow (first N− layer 22 A) and near the drain region 5 deep (second N− layer 22 B). N-
The structure composed of the layer (drift region) 22 corresponds to the element isolation film 9.
In a semiconductor device in which a plurality of semiconductor devices are juxtaposed via A, for example, when an N-channel LDMOS transistor is described as an example, a channel stopper layer 38 is formed below the element isolation film 9A. By making the drift region formed under the gate electrode 7 shallow, the RESURF effect is enhanced and high integration can be achieved.

The manufacturing method includes two types of N-type impurities (for example, arsenic ion and arsenic ion) for forming the N- layer 22 serving as the drift region in the P-type well region 21 in the P-type semiconductor substrate 1. (Phosphorus ion) is ion-implanted. Next, a silicon nitride film 34 serving as a mask for LOCOS oxidation is formed on the substrate 1 in a later step, and a photoresist film 36 formed so as to cover the silicon nitride film 34 is used as a mask to form a P-type film on the surface of the substrate. Impurities (for example, boron ions) are ion-implanted. Subsequently, the first and second LOCOS oxide films 9A and 9B are formed by selective oxidation using the silicon nitride film 34 as a mask, and each of two types of N-type impurities (for example, arsenic ions and phosphorus ions) is diffused. From the difference in the coefficients, the surface layer of the substrate and the P-type well region 2 are relatively large.
1 at a relatively deep position in each of the lightly doped N- layers 22.
A and 22B are formed, and a channel stopper layer 38 is formed below the second LOCOS oxide film 9B. continue,
By using a photoresist film 39 formed on the substrate 1 on the drain formation region as a mask, a P-type impurity (for example, boron ion) is ion-implanted and diffused into the surface layer of the substrate in the source formation region to diffuse the source formation region. N- layer 2 formed at a relatively deep position in P-type well region 21
2B is offset by this diffusion of boron ions. Next, a gate insulating film 6 is formed on the substrate 1, and a gate electrode 7 is formed so as to extend over the first LOCOS oxide film 9A from the gate insulating film 6, and then the gate electrode 7 and the drain are formed. A P-type body region 3 is formed adjacent to one end of the gate electrode 7 by implanting and diffusing a P-type impurity (for example, boron ion) using the photoresist film 40 formed so as to cover the region as a mask. I do.
Then, a photoresist film 42 is formed on the source forming region and the drain forming region formed in the P-type body region 3.
And forming N-type diffusion regions 4 and 5 serving as source / drain regions by implanting N-type impurities (for example, phosphorus ions and arsenic ions) using the mask as a mask.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor device according to the present invention and a method for manufacturing the same will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view for explaining an LDMOS transistor of the present invention, and shows an N-channel type LDMOS transistor structure as an example.
Although the description of the structure of the P-channel LDMOS transistor is omitted, it is well known that the structure is the same except for the conductivity type. The same components as those in the conventional configuration are denoted by the same reference numerals, and the description will be simplified.

In FIG. 1, reference numeral 1 denotes a semiconductor substrate of one conductivity type, for example, a P-type semiconductor. Reference numeral 21 denotes a P-type well region, in which an N− layer 22 is formed and a P-type well is formed. A body region 3 is formed. An N-type diffusion region 4 is formed in the P-type body region 3, and an N-type diffusion region 5 is formed in the N− layer 22. A gate electrode 7 is formed on the surface of the substrate with a gate insulating film 6 interposed therebetween, and a channel region 8 is formed in a surface region of the P-type body region 3 immediately below the gate electrode 7.

Further, the N-type diffusion region 4 is a source region,
The first LOCOS is formed by using the N-type diffusion region 5 as a drain region.
The N − layer 22 under the oxide film 9A is used as a drift region.

Then, the LDMOS transistor having the above-described structure is used as a second LOCOS oxide film 9 as an element isolation film.
B are arranged side by side through the second LOCO
A channel stopper layer 38 is formed below the S oxide film 9B.

Although not shown in the drawings, a source electrode 10 and a drain electrode 11 are formed so as to contact the N-type diffusion regions 4 and 5 as in the conventional structure.
A P-type diffusion region 12 for taking the potential of the P-type body region 3 is formed adjacent to the D-type diffusion region 4, and is covered with an interlayer insulating film 13.

A feature of the present invention is that the N- layer 22 is formed in the P-type well region 21 as described above, and the N- layer 22 is formed shallow below the gate electrode 7 (the first N- layer 22). 22
A), it is formed deep near the N-type diffusion region (drain region) 5 (the second N− layer 22B).

Also, a second LOCO as an element isolation film
In a configuration in which a plurality of bodies are provided in parallel via the S oxide film 9B,
The channel stopper layer 38 is formed under the second LOCOS oxide film 9B.

As a result, the concentration of the first N− layer 22A formed shallowly below the gate electrode 7 is formed to be high, the on-resistance becomes small, the current easily flows, and the N-type diffusion region ( Since the concentration of the second N− layer 22B near the drain region 5 (the position of the drift region) is formed low, the depletion layer is easily expanded, and high breakdown voltage can be achieved (see the concentration distribution diagram shown in FIG. 11).

The channel stopper layer 38 formed under the second LOCOS oxide film 9B allows the second L
The expansion of the depletion layer in the diffusion regions 4 and 5 of the LDMOS transistors adjacent to each other via the OCOS oxide film 9B can be suppressed, and the size of the second LOCOS oxide film 9B itself can be reduced, so that high integration can be achieved. . In addition, high integration can be achieved by employing the N− layer 22 instead of the N-type well region 2 as in the conventional configuration. With such a configuration, the size of the second LOCOS oxide film 9B itself can be reduced to L1 (about 5 μm to about 8 μm) (the conventional size L2 is about 10 μm).
μm to 30 μm). Further, by providing an interval of about 2 μm to 3 μm from the end of the second LOCOS oxide film 9B to the channel stopper layer 38, a high breakdown voltage can be achieved. Note that the LDMOS transistor of the present embodiment has a withstand voltage of about 30 V.

Hereinafter, a method of manufacturing the above-described semiconductor device will be described with reference to the drawings.

In FIG. 2, after a pad oxide film 30 is formed on a P-type semiconductor substrate 1, an N- layer 22 which will become a drift region in a later step is formed in a P-type well region 21 using a photoresist film 31 as a mask. The first and second ion-implanted layers 32 and 33 are formed by ion-implanting two types of N-type impurities (for example, arsenic ions and phosphorus ions).
In this step, for example, arsenic ions are accelerated to an acceleration voltage of 160
At an implantation condition of 3 × 10 ¹² / cm ² at KeV, and an implantation amount of 4
This is performed under an implantation condition of × 10 ¹² / cm ² .

Next, referring to FIG.
The second photoresist film 3 so as to cover the silicon nitride film 34 patterned through the photoresist film 35 of FIG.
After the formation of the second photoresist film 6, a P-type impurity (for example, boron ion) is ion-implanted into a certain region on the substrate surface (a region where a channel stopper layer 38 is formed in a later step) using the second photoresist film 36 as a mask. By implanting, an ion implantation layer 37 for forming a channel stopper layer is formed. In this step, for example, boron ions are accelerated to approximately 60 KeV.
Then, the implantation is performed under an implantation condition of 5 × 10 ¹³ / cm ² . Then, the ion implantation process for forming the channel stopper layer of the LDMOS transistor is carried out in a normal high withstand voltage MO (not shown).
Since the step is performed in the same step as the step of forming the channel stopper layer formed in the S transistor, the number of manufacturing steps does not increase unnecessarily. In FIG. 4, the first and second photoresist films 35 and 36 are removed. Then, the substrate surface is selectively oxidized using the silicon nitride film 34 as a mask to form first and second LOs having a thickness of about 7300 °.
The COS oxide films 9A and 9B are formed, and the arsenic ions are diffused into the substrate 1 due to the difference between the diffusion coefficients of arsenic ions and phosphorus ions implanted in the substrate surface layer as described above. A first N- layer 22A is formed on the substrate 1 and the phosphorus ions are diffused into the substrate 1 so that a second N- layer 22A is formed at a relatively deep position in the P-type well region 2.
Is formed, and the second LOCOS is further formed.
A channel stopper layer 38 is formed below oxide film 9B. The first LOCOS oxide film 9A serves as a part of a gate insulating film 6 described later to increase the breakdown voltage, and the second LOCOS oxide film 9B serves as an element isolation film. . Then, the second LOCOS oxide film 9B
The distance from the end to the channel stopper layer 38 is about 2
A higher breakdown voltage is achieved by opening about 3 μm to 3 μm.

Subsequently, in FIG. 5, after a photoresist film 39 is formed on the substrate 1 on the drain formation region, a P-type impurity (for example, By ion-implanting and diffusing boron ions, the phosphorus ions forming the second N − layer 22B of the source forming region are offset by the boron ions, and the second ions of the source forming region are eliminated.
Of the N− layer 22B. In this step, for example, boron ions are implanted at an acceleration voltage of 80 KeV and an implantation amount of 8 × 1.
After performing under the implantation condition of 0 ¹² / cm ² , approximately 1100 ° C.
For 2 hours. FIG. 11 is a diagram showing impurity concentration distributions when the arsenic ion (shown by a solid line), phosphorus ion (shown by a dotted line), and boron ion (shown by a dashed line) are respectively diffused. The concentration distribution of the substrate with the phosphorus ions as the parent is superimposed with the concentration distribution with the boron ions as the parent and is offset.

As described above, in the present invention, when forming the drift region, the difference between the diffusion coefficients of arsenic ions and phosphorus ions having different diffusion coefficients is utilized to form the second N formed deep in the substrate near the source formation region. The layer 22B is offset by diffusing boron ions implanted in a later step, and the first N− layer 2 formed on the surface of the substrate is formed on the source forming region side.
Only 2A remains, and a semiconductor device with reduced on-resistance can be provided by a relatively simple manufacturing process.

Next, in FIG. 6, after a gate insulating film 6 having a thickness of about 800 ° is formed on the substrate 1, about 2500 ° is formed so as to extend from the gate insulating film 6 onto the LOCOS oxide film 9. The gate electrode 7 having a thickness of 5 nm is formed.

Subsequently, referring to FIG.
Using a photoresist film 35 formed so as to cover the drain formation region as a mask, a P-type impurity (for example, boron ion) is implanted and diffused, so that the P-type body region is adjacent to one end of the gate electrode 7. Form 3 In this step, for example, boron ions are implanted at an acceleration voltage of about 40 KeV under an implantation condition of 5 × 10 ¹³ / cm ² , and then thermally diffused at about 1050 ° C. for 2 hours.

In FIG. 8, an N-type impurity is implanted by using a photoresist film 42 having openings on the source formation region and the drain formation region formed in the P-type body region 3 as a mask. N to be the area
Forming diffusion regions 4 and 5 are formed. In this step, for example, when forming a source / drain region having a so-called LDD structure, first, for example, phosphorus ions are implanted at an acceleration voltage of about 40 KeV with the photoresist film 40 shown in FIG. After the implantation under the implantation condition of 5 × 10 ¹³ / cm ² , as shown in FIG.
A sidewall spacer film 41 is formed at the side end of the substrate, and for example, arsenic ions are implanted at an acceleration voltage of about 80 KeV at a dose of 5 × 10 ¹⁵ / cm 3 using the photoresist film as a mask.
Inject under ² injection conditions. In this embodiment, it goes without saying that the source / drain regions are not limited to the LDD structure.

In FIG. 9, a photoresist film 38 is formed to form a P-type diffusion region 12 formed at a position adjacent to the N-type diffusion region 4 in order to take the potential of the P-type body region 3. A P-type impurity (for example, boron difluoride ion) is implanted as a mask to form the P-type diffusion region 12. In this step, for example, boron difluoride ions are implanted at an acceleration voltage of about 60 KeV and an injection amount of 4 ×.
The implantation is performed under an implantation condition of 10 ¹⁵ / cm ² .

Hereinafter, the source electrode 10,
After the formation of the drain electrode 11, the interlayer insulating film 13 is formed to complete the semiconductor device.

As described above, in the method of manufacturing a semiconductor device according to the present invention, when forming the N − layer 22 serving as the drift region, arsenic ions and phosphorus ions having different diffusion coefficients, Since the film is formed using the difference in diffusion coefficient from boron ions having a diffusion coefficient substantially equal to or greater than that, the manufacturing process is simple.

Also, the step of forming the channel stopper layer 38 is performed simultaneously with the step of forming the channel stopper layer of a normal high voltage MOS transistor.
The number of manufacturing steps does not increase.

FIG. 10 is a sectional view showing a semiconductor device according to another embodiment of the present invention. A feature different from the above-described embodiment is that a plurality of LDMOS transistors are juxtaposed via an element isolation film 9B. The arrangement of the diffusion regions 4 and 5 is reversed. With such an arrangement, higher integration can be achieved. That is, as in the embodiment, the diffusion regions 5 (drain regions) whose potentials fluctuate are separated from each other by the element isolation film 9B.
In the configuration in which the diffusion region 4 (source region) and the diffusion region 5 (drain region) are adjacent to each other, the size of the element isolation film 9B can be made smaller because one of them has a fixed potential. .

The feature of enabling the above-described high integration is applied to the LDMOS transistor of the conventional configuration shown in FIG. 12, that is, the one in which the N-type well region 2 is uniformly formed to the same depth position. Needless to say, it is effective.

[0036]

According to the semiconductor device of the present invention, the low-concentration layer serving as the drift region is formed to be shallow at least below the gate electrode and deep near the drain region.
When a plurality of semiconductor devices having such a configuration are arranged side by side via an element isolation film, a channel stopper layer can be formed under the element isolation film. Thus, the size of the element isolation film itself can be reduced, and high integration can be achieved.

Further, in the method of manufacturing a semiconductor device according to the present invention, the step of forming the channel stopper layer includes:
Since this step is performed simultaneously with the step of forming a channel stopper layer of a normal high-breakdown-voltage MOS transistor, the number of manufacturing steps does not increase.

Further, in the present invention, at the time of forming the drift region, at least two kinds of second conductivity type impurities having different diffusion coefficients and substantially the same as the diffusion coefficient of at least one or more kinds of second conductivity type impurities. The formation process is simplified by utilizing the difference in diffusion coefficient between at least one or more types of first conductivity type impurities having a diffusion coefficient equal to or greater than that.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 6 is a sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 7 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 8 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 9 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 10 is a sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 11 is a concentration distribution diagram of various ions for explaining the principle of forming a drift region according to the present invention.

FIG. 12 is a sectional view showing a conventional semiconductor device.

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 5F032 AA14 AA26 BA05 CA03 CA17 CA24 DA43 5F040 DA05 DA22 DB03 DC01 EB01 EB11 EE01 EE05 EF02 EF04 EF05 EF11 EK01 EK07 EM02 FB05 FC14 FC17 5F048 AA01 BC03 BC BD01 BE03 BE04 BG12 BH07 DA25 DB07

Claims (5)

[Claims] An element isolation structure comprising a source region, a channel region, and a drain region, a gate electrode formed on the channel region, and a drift region formed between the channel region and the drain region. A semiconductor device comprising a plurality of semiconductor devices arranged side by side via a film, wherein a channel stopper layer is formed below the element isolation film. 2. A semiconductor device comprising: a source region, a channel region, and a drain region; a gate electrode formed on the channel region; a shallow region between the channel region and the drain region at least below the gate electrode; In a semiconductor device having a structure in which a plurality of drift regions are formed deep in the vicinity of a region and arranged in parallel with each other via an element isolation film, a channel stopper layer is formed below the element isolation film. . A first conductivity type well region formed in a first conductivity type semiconductor substrate; a gate electrode formed on the substrate via a gate insulating film; and a gate electrode adjacent to the gate electrode. A first conductivity type body region formed; a second conductivity type source region and a channel region formed in the first conductivity type body region; and a position separated from the first conductivity type body region. A second conductive type drain region, and a second conductive type drift region formed shallowly below the gate electrode and deeply near the drain region from the channel region to the drain region. A semiconductor device comprising a plurality of devices arranged side by side via an element isolation film having a channel stopper layer formed below. 4. A method for forming a low-concentration second conductivity type layer which becomes a drift region through a post-process in a first conductivity type well region in a first conductivity type semiconductor substrate. A step of ion-implanting an impurity; and an step of forming an oxidation-resistant film on the substrate and then ion-implanting a first conductivity-type impurity into a surface layer of the substrate using a photoresist film formed so as to cover the oxidation-resistant film as a mask. And selectively oxidizing the oxidation resistant film as a mask to form first and second L
An OCOS oxide film is formed, and a low-concentration second layer is formed at a relatively deep position in the well region of the first conductivity type and at the surface layer of the substrate, respectively, based on a difference in diffusion coefficient between the two types of impurities of the second conductivity type. Forming a conductive type layer, and further forming a channel stopper layer under the second LOCOS oxide film; and using the photoresist film formed on the substrate on the drain formation region as a mask, the substrate surface layer in the source formation region The second conductivity type layer formed at a relatively deep position in the first conductivity type well region in the source forming region is ion-implanted and diffused with the first conductivity type impurity. Forming a gate insulating film in a region other than the first and second LOCOS oxide films on the substrate, and straddling over the first LOCOS oxide film from the gate insulating film. After the gate electrode is formed as described above, the first conductive type impurity is implanted and diffused by using the photoresist film formed so as to cover the gate electrode and the drain formation region as a mask, so as to be adjacent to one end of the gate electrode. Forming a first conductivity type body region as described above, and using a photoresist film having openings on a source formation region and a drain formation region formed in the first conductivity type body region as a mask to remove a second conductivity type impurity. Implanting to form source / drain regions. 5. A method according to claim 1, wherein said low-concentration second-conductivity-type layer serving as said drift region is substantially equal to two types of second-conductivity-type impurities having different diffusion coefficients and a diffusion coefficient of one of said second-conductivity-type impurities. The method of manufacturing a semiconductor device according to claim 4, wherein the semiconductor device is formed using a difference in diffusion coefficient between the first conductivity type impurity having a higher diffusion coefficient and the first conductivity type impurity.