JP2001196578A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique to improve a high-breakdown voltage MOS transistor. SOLUTION: A semiconductor device is characterized in that the device is provided with a gate electrode 16 formed on a P-type well 2 via a gate oxide film 9, an N+ high-concentration source layer 12 formed is such a way as to adjoin the end part on one side of the end parts of this electrode 16, an N+ high-concentration drain layer 12 formed separately from the other end part of the electrode 16, a P-type body layer 14 formed under the lower part of the electrode 16 and an N- low-concentration drain layer 10 formed shallow under at least the electrode 16 and formed deep in the vicinity of the drain layer 12, which extends from the lower part of the electrode 16 to the drain layer 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a high voltage MOS transistor technology used for, for example, a liquid crystal driving IC.

[0002]

2. Description of the Related Art A conventional semiconductor device and a method of manufacturing the same will be described below with reference to the drawings.

Here, as a high withstand voltage element used for the above-mentioned liquid crystal driving IC or the like, for example, an LD (Lateral Double Dif) is used.
fused) MOS transistors. This L
The DMOS transistor structure means that a diffusion layer formed on the surface of a semiconductor substrate is diffused with an impurity of a different conductivity type to form a new diffusion layer, and a difference in the lateral diffusion of these diffusion layers is determined by an effective channel. The element is used as a long element, and a short channel is formed, so that the element is suitable for low on-resistance.

FIG. 7 is a cross-sectional view for explaining a conventional DMOS transistor. As an example, an N-channel DM
An OS transistor structure is illustrated. Although the description of the structure of the P-channel DMOS transistor is omitted, it is well known that the structure is the same except that the conductivity type is different.

In FIG. 7, reference numeral 51 denotes one conductivity type, for example, P
A semiconductor substrate 52 is an N-type well, a P-type body layer 53 is formed in the N-type well 52, and an N-type diffusion layer 54 is formed in the P-type body layer 53. An N-type diffusion layer 55 is formed in the N-type well 52. A gate electrode 57 is formed on the substrate surface with a gate oxide film 56 interposed therebetween.
A channel layer 58 is formed in a surface region of the mold body layer 53.

The N-type diffusion layer 54 is used as a source diffusion layer and the N-type diffusion layer 55 is used as a drain diffusion layer.
The N-type well 52 under the oxide film 59 is used as a drift layer. Reference numerals 60 and 61 denote a source electrode and a drain electrode, respectively, 62 a P + type diffusion layer for taking the potential of the P type body layer 53, and 63 an interlayer insulating film.

In brief, the manufacturing method will be described. The N-type well 52 is formed by ion-implanting and diffusing an N-type impurity into the semiconductor substrate 51, and a gate oxide film 56 is formed on the substrate 51. Is formed, a gate electrode 57 is formed with the gate oxide film 56 interposed. Then, the P-type body layer 53 is formed by ion-implanting and diffusing a P-type impurity using the gate electrode 57 as a mask, and then the N-type diffusion layers 54 and 55 are formed.

As described above, in the DMOS transistor, by forming the N-type well 52 by diffusion, the concentration on the surface of the N-type well 52 is increased.
Current can easily flow on the surface, and high withstand voltage can be achieved.

The DMOS transistor having such a configuration is called a reduced surface area (hereinafter referred to as RESURF) DMOS. The drift concentration of the drift layer of the N-type well 52 is RESUR.
It is set so as to satisfy the F condition. Such a technique is disclosed in Japanese Patent Application Laid-Open No. 9-139438.

[0010]

Here, the above DMOS
In the transistor structure, as shown in FIG. 7, the N-type well 52 is uniformly formed to the same depth position.
This has been a hindrance to further increasing the breakdown voltage and reducing the on-resistance.

Since the P-type body layer 53 is formed so as to surround the entire N-type diffusion layer 54,
There is also a problem that the junction capacitance at this portion increases.

[0012]

SUMMARY OF THE INVENTION Accordingly, a semiconductor device according to the present invention has been made in view of the above problems, and includes, for example, a gate electrode formed on a P-type well via a gate oxide film, A high-concentration N-type source layer formed adjacent to one end of the gate electrode; a high-concentration N-type drain layer formed separately from the other end of the gate electrode; A low-concentration N-type drain layer that is formed at least shallowly below the gate electrode and deeply near the drain layer from below the gate electrode to the high-concentration N-type drain layer. It is characterized by the following.

Thus, a semiconductor device having a high withstand voltage and a small on-resistance can be provided.

Another object of the present invention is to provide a method of manufacturing the same. For example, two types of N-type impurities are formed in a P-type well to form a low-concentration reverse conductivity type layer through a post-process. After the ion implantation, a certain region on the P-type well is selectively oxidized to form a selective oxide film. Subsequently, after a P-type impurity is ion-implanted into the P-type well in the source formation region using the resist film formed on the P-type well in the drain formation region as a mask, the P-type impurity and the two types of N By diffusing the n-type impurities, a low-concentration N-type layer comprising a first N-type layer formed at a relatively shallow position in the P-type well and a second N-type layer formed at a relatively deep position is formed.
Form a drain layer. Next, an N-type impurity is ion-implanted into a P-type well to form a high-concentration N-type source layer adjacent to one end of a gate electrode to be formed in a later step. A high-concentration N-type drain layer is formed at the separated position. Further, a P-type impurity is ion-implanted into the P-type well to form a P-type body layer adjacent to the N-type source layer from below one end of the gate electrode. Forming a gate electrode on the P-type well via a gate oxide film.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor device according to the present invention and a method for manufacturing the same will be described below with reference to the drawings.

FIG. 5A is a cross-sectional view for explaining a high withstand voltage MOS transistor of the present invention, and shows an N-channel MOS transistor structure as an example. Although the description of the structure of the P-channel MOS transistor is omitted, it is well known that the structure is the same except that the conductivity type is different. FIG. 5 (B)
It is sectional drawing of the XX line direction of FIG. 5 (A), and represents sectional drawing of the gate width direction of the gate electrode 16 mentioned later.

In FIG. 5, reference numeral 1 denotes a semiconductor substrate (P-Sub) of one conductivity type, for example, a P-type, and 2 denotes a P-type well (P-sub).
In (W), a gate electrode 16 is formed on the P-type well 2 with a gate oxide film 9 interposed therebetween. A high-concentration N + type source layer (N + layer) 12 is formed adjacent to one end of the gate electrode 16, and a high-concentration N + type drain layer (N + layer) is formed at a position separated from the other end of the gate electrode 16. N +
Layer 12 is formed. And the gate electrode 1
6, a P-type body layer (PB layer) 14 is formed adjacent to the N + type source layer 12, and the gate electrode 1
6, from the lower side to the high-concentration N + type drain layer 12, below the gate electrode 16 shallower (first N− layer 10A),
In addition, a low-concentration N- type drain layer 10 is formed deeply (in the second N- layer 10B) near the N + type drain layer 12 (see FIG. 3). Although not shown in the drawings, a source electrode and a drain electrode are formed so as to contact the N + type source / drain layer 12 via an interlayer insulating film. 17 is the P-type body layer 1
4 is a P-type diffusion layer formed adjacent to the N-type source layer 12 so as to take the potential of the P-type diffusion layer via the P-type well 2. 17
Is connected to

A feature of the present invention is that, as described above, an N- layer (low-concentration N-type drain layer) 10 is formed in the P-type well 2, and this N- layer 10 is formed shallow below the gate electrode 16. (The first N− layer 10A) and is formed deep near the drain layer 12 (the second N− layer 10B).

As a result, the first N− layer 10 A formed shallowly below the gate electrode 16 has a high carrier concentration, so that the on-resistance becomes small and a current easily flows, and the second N− layer 10 A near the drain layer 12 is formed. The depletion layer is easily expanded in the N− layer 10B, and the breakdown voltage can be increased (see the concentration distribution diagram shown in FIG. 6). Note that the N-channel MOS transistor of the present embodiment has a withstand voltage of about 30V.

Further, the P-type body layer 14 is formed only below the gate electrode 16, and the conventional P-type body layer 53 (shown in FIG. 7) surrounds the entire high-concentration N-type source layer 54 (see FIG. 7). 7), the junction capacitance can be reduced, and the structure is effective for increasing the speed.

Hereinafter, a method of manufacturing the above-described semiconductor device will be described with reference to the drawings.

In FIG. 1, after a pad oxide film 3 is formed on a P-type well 2 formed in a P-type semiconductor substrate 1,
Two types of N-type impurities (for example, arsenic ions and phosphorus ions) for forming an N- layer 10 (see FIG. 3) which will be a low-concentration drain layer in a later step using the resist film 4 as a mask Is ion-implanted to form first and second ion-implanted layers 6A and 6B. In this step, for example, an arsenic ion is accelerated at an accelerating voltage of about 160 KeV for 3 hours.
The implantation is performed at an implantation amount of × 10 ¹² / cm ² , and phosphorus ions are implanted at an acceleration voltage of about 50 KeV and under an implantation condition of 4 × 10 ¹² / cm ² .

Next, referring to FIG. 2, using a silicon nitride film (not shown) formed on the substrate 1 as a mask, a certain region on the substrate surface is subjected to a heat treatment at 1000 ° C. for 4 hours by LOCOS method to be selectively oxidized. A selective oxide film 8 (constituting a part of an element isolation film and a gate oxide film) having a thickness of about 730 nm is formed. Further, the selective oxide film 8
A gate oxide film 9 having a thickness of about 80 nm is formed on the surface of the substrate other than the above.

Subsequently, in FIG. 3, after a resist film 11 is formed on the P-type well 2 on the drain formation region, the resist film 11 is used as a mask to form a P-type well on the surface layer of the P-type well 2 in the source formation region. By implanting type impurities (for example, boron ions) and diffusing the arsenic ions and phosphorus ions together with the boron ions, a first N− layer 10A is formed on the relatively surface layer in the P-type well 2, A low-concentration N- type drain layer 10 formed by forming a second N- layer 10B at a relatively deep position is formed.

In this step, for example, after boron ions are implanted at an acceleration voltage of about 80 KeV at an implantation amount of 8 × 10 ¹² / cm ^2, a thermal diffusion treatment is performed at about 1100 ° C. for 2 hours.

As a result, the N-type drain layers 10 having different depths as described above are formed due to differences in diffusion coefficients of three types of ions (boron ions, arsenic ions, and phosphorus ions).

That is, as described above, the arsenic ions are diffused into the P-type well 2 due to the difference between the diffusion coefficients of the arsenic ions and the phosphorus ions implanted in the surface of the P-type well 2, and are relatively diffused to the surface. One N- layer 10A is formed, and the phosphorus ions are diffused into the P-type well 2 to form a second N- layer 10B at a relatively deep position. Then, the phosphorus ions forming the second N- layer 10B in the source forming region are canceled by the boron ions, and the second N- layer 10B in the source forming region is extinguished (shown in FIG. 3). As described above, the first N− layer 10A is formed at a shallow position on the surface of the substrate in the source formation region.)

FIG. 6 is a diagram showing impurity concentration distributions when the arsenic ions (shown by solid lines), phosphorus ions (shown by dotted lines), and boron ions (shown by dashed lines) are respectively diffused. As can be seen from the graph, the n-type impurity concentration distribution of the substrate due to phosphorus ions is
It is superposed on the type impurity concentration distribution and is offset.

As described above, according to the present invention, arsenic ions and phosphorus ions having different diffusion coefficients are used when forming the low-concentration N-type drain layer (N− layer 10), and the phosphorus ions are added to a predetermined region (source forming region). Is diffused to form a second N− layer 10 that is to be formed deep in the substrate on the source forming region side.
B is offset by diffusing boron ions having a diffusion coefficient substantially equal to or higher than the diffusion coefficient of the phosphorus ions, and a first N− layer formed on the surface of the substrate is formed on the source forming region side. It is possible to provide a semiconductor device in which only 10 A remains and the on-resistance is reduced by a relatively simple manufacturing process.

Further, the action of the boron ions for canceling (the presence of boron ions in the region shown by the dotted line in FIG. 5A) causes the drain layer (N− layer 10
B) The expansion of the depletion layer can be suppressed.

Further, referring to FIG. 4, N-type impurities are ion-implanted using the resist film as a mask to form an N + layer (hereinafter referred to as a high-concentration N-type source / drain layer 12). That is, first, phosphorus ions are applied to the surface layer of the substrate at an acceleration voltage of about 80 KeV, for example, at a concentration of 2 × 10 ¹⁵ / cm 2 while a region other than the high concentration N-type source / drain layer formation region is covered with a resist film (not shown). Ion implantation is performed under the condition ² to form a high concentration N-type source / drain layer 12.

Next, a P-type impurity is ion-implanted so as to penetrate the N- layer 10A using the resist film 13 as a mask, so that the P-type impurity is adjacent to the N-type source layer 12.
The mold body layer 14 is formed. That is, first, the resist film 1
In a state where the area other than the P-type body layer forming area is covered in 3, for example, boron difluoride ion is applied to the surface layer of the substrate for about 1 hour.
The P-type body layer 14 is formed by ion implantation at an acceleration voltage of 20 KeV under an implantation condition of 3 × 10 ¹² / cm ² .

Subsequently, in FIG.
A polysilicon film having a thickness of about 0 nm is formed, and POCl ₃ is thermally diffused from the gas phase into a conductive (N-type) film using POCl ₃ as a thermal diffusion source. After that, tungsten silicide (about 100 nm) is formed on the polysilicon film. WSix)
A gate electrode 16 for each MOS transistor is formed by laminating a film, and further, an SiO ₂ film of about 150 nm (to be a mask for patterning the gate electrode) by using a resist film (not shown). Reference numeral 17 denotes a P-type diffusion layer formed at a position adjacent to the N-type source layer 12 in order to take the potential of the P-type body layer 14. 4 × 10 ¹⁵ / c at an acceleration voltage of about 60 KeV for boron ions
It is formed by implantation with an implantation amount of m ² .

Although not shown in the drawings, the entire surface is formed of a TEOS film, a BPSG film, etc.
After the formation of the interlayer insulating film to the extent, a metal wiring layer which contacts the high-concentration N-type source / drain layer 12 is formed, whereby the N-channel MOS transistor is completed. Although a description is omitted, a P-channel MOS transistor is similarly formed.

As described above, in the structure of the present invention, since the P-type body layer 14 or the N-type body layer (not shown) is formed only under the gate electrode 16, the structure of the conventional structure (shown in FIG. 7) is obtained. Thus, the junction capacitance can be reduced as compared with the case where the P-type body layer 53 wraps the high-concentration source layer 54, and high-speed operation becomes possible.

Further, in the above structure, since the P-type body layer 14 or the N-type body layer is formed by ion implantation, miniaturization becomes possible as compared with a conventional diffusion-formed one.

Further, according to the above manufacturing method, when forming the low-concentration N-type drain layer 10, two types of N-type impurities having different diffusion coefficients and a diffusion coefficient of one of the N-type impurities are used. Since it is formed utilizing the difference in diffusion coefficient with one type of P-type impurity having a diffusion coefficient substantially equal to or higher than that of the first embodiment, the manufacturing process is simple.

In addition, since the low-concentration layer serving as the drift region is formed shallow at least below the gate electrode and deep near the drain region, a high breakdown voltage and a reduction in on-resistance can be achieved.

Further, in the present invention, the P-type body layer or the N-type body layer
Since the mold body layer is formed only below the gate electrode, the junction capacitance can be reduced as compared with a conventional structure in which a P-type body layer or an N-type body layer wraps a high concentration source layer.

Further, the spread of the depletion layer of the drain layer is suppressed by the action of the impurity ions for canceling which are implanted when forming the shallow layer (first N- layer) constituting the low concentration drain layer. Can be.

Further, since high-temperature heat treatment after the formation of the gate electrode is not required, it is possible to mount the gate electrode together with the miniaturization process.

[0042]

According to the present invention, the low-concentration layer serving as the drift region is formed to be shallow at least below the gate electrode and deep near the drain layer, so that a high breakdown voltage and a low on-resistance can be achieved. .

In forming the drift region,
At least two types of impurities having the same conductivity type and different diffusion coefficients, and at least one type of impurity of the opposite conductivity type having a diffusion coefficient substantially equal to or higher than the diffusion coefficient of the at least one type of impurity; The manufacturing process is simplified because of the use of the difference between the diffusion coefficients of the above.

Further, according to the present invention, since the P-type body layer or the N-type body layer is formed only under the gate electrode, the P-type body layer or the N-type body layer wraps the high concentration source layer as in the conventional structure. Thus, the junction capacitance can be reduced.

Further, the expansion of the depletion layer of the drain layer is suppressed by the action of the impurity ions for canceling which are implanted when forming the shallow layer (first N− layer) constituting the low concentration drain layer. Can be.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 6 is a concentration distribution diagram of various ions for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 7 is a sectional view showing a conventional semiconductor device.

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Masamo Aoyama 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. F-term (reference) 5F040 DA12 DA22 DC01 EB01 EC01 EC07 EC13 ED09 EE05 EF13 EF18 EK01 EM02 EM03

Claims (12)

[Claims] 1. A high-concentration source / drain layer of high conductivity formed in a semiconductor layer of one conductivity type, a gate electrode formed on a channel layer located between the source / drain layers, and a vicinity of the source layer. A semiconductor layer having a one-conductivity-type body layer formed on the substrate and a low-concentration reverse-conduction-type drain layer formed between the channel layer and the drain layer; A semiconductor device, which is formed shallow under an electrode and deep near the drain layer, and wherein the one conductivity type body layer is formed only under the gate electrode. 2. A gate electrode formed on a semiconductor layer of one conductivity type via a gate oxide film; a source layer of a high concentration opposite conductivity type formed adjacent to one end of the gate electrode; A high-concentration reverse-conductivity-type drain layer formed apart from the other end of the gate electrode; and a one-conductivity-type drain layer formed between the reverse-conductivity-type source layer and the reverse-conductivity-type drain layer below the gate electrode. A body layer, and a low-concentration reverse-conductivity-type drain layer that is formed at a shallow depth below the gate electrode and deeply near the drain layer, from below the gate electrode to the high-concentration reverse-conductivity-type drain layer. 2. The semiconductor device according to claim 1, wherein: 3. The semiconductor device according to claim 1, wherein said body layer has substantially the same width as said gate electrode. 4. The semiconductor device according to claim 1, wherein said body layer is an impurity region formed by ion implantation. 5. The low-concentration reverse conductivity type drain layer is a low-concentration impurity region formed by canceling phosphorus ions with boron ions.
3. The semiconductor device according to claim 1. 6. The low-concentration reverse-conductivity-type drain layer is a low-concentration impurity region formed by canceling phosphorus ions with boron ions, and the high-concentration reverse-conductivity-type drain layer mainly contains arsenic. 2. The semiconductor device according to claim 1, wherein the semiconductor device is an impurity region. 7. A high-concentration source / drain layer of high conductivity formed in a semiconductor layer of one conductivity type; a gate electrode formed on a channel layer located between the source / drain layers; A method of manufacturing a semiconductor device having a one-conductivity-type body layer formed on the substrate and a low-concentration opposite-conductivity-type drain layer formed between the channel layer and the drain layer. Implanting one-conductivity-type impurity ions into the layer to form a one-conductivity-type body layer adjacent to the opposite-conductivity-type source layer from below one end of the gate electrode. Production method. 8. A method for forming a low-concentration reverse-conductivity-type layer through a post-process in a one-conductivity-type semiconductor layer, so that two layers having different diffusion coefficients are used.
Implanting different types of impurity ions of the opposite conductivity type, selectively oxidizing a certain region on the semiconductor layer to form a selective oxide film, and using a mask formed on the semiconductor layer on the drain formation region. One conductivity type impurity ions are implanted into the semiconductor layer in the source formation region, and the one conductivity type impurity ions are
By diffusing with the opposite types of impurity ions,
Forming a low-concentration reverse-conductivity-type layer at each of a relatively deep position and a relatively surface layer in the semiconductor layer; and implanting a reverse-conductivity-type impurity ion into the semiconductor layer to form a gate electrode formed in a later step. Forming a high-concentration reverse-conductivity-type source layer adjacent to one end and forming a high-concentration reverse-conductivity-type drain layer at a position separated from the other end of the gate electrode; Implanting a conductivity type impurity ion to form a body layer of one conductivity type from below one end of the gate electrode so as to be adjacent to the source layer of the opposite conductivity type, and via a gate oxide film on the semiconductor layer Forming a gate electrode. 9. The low-concentration reverse-conductivity-type drain layer includes two types of reverse-conductivity-type impurities having different diffusion coefficients and a diffusion coefficient of one of the two reverse-conductivity-type impurities. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the semiconductor device is formed using a difference in diffusion coefficient between the first conductivity type impurity having a diffusion coefficient substantially equal to or higher than that of the first conductivity type impurity. 10. The method according to claim 8, wherein the two types of impurities of the opposite conductivity type are phosphorus and arsenic. 11. The method according to claim 8, wherein the two types of impurities of the opposite conductivity type are phosphorus and arsenic, and the one type of impurity is boron. 12. The method according to claim 8, wherein the step of implanting one conductivity type impurity ions into the semiconductor layer to form a body region is a step by ion implantation.