JP2002343884A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device comprising well structure capable of independently driving a plurality of a high breakdown voltage transistors by different voltages with the improvement of the density of a well area and to provide its manufacturing method. SOLUTION: The semiconductor comprises triple wells consisting of a first well 35 of a first conductive type (P-type) formed at a silicon substrate 21, the second well 29 of a second conductive type (N-type) adjacent to the first well 35, and the third well 41 of the first conductive type (P-type) formed within the second well 29. A high breakdown voltage MOSFET is provided within the respective wells. Respective MOSFETs 100N, 200P and 300N have offset areas in a well surrounding a gate insulated layer 78, respectively. This offset area consists of low density impurity layers 63a and 57a provided under an offset LOCOS layer 65a on the silicon substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including a field-effect transistor having a high breakdown voltage, and a method of manufacturing the same.

[0002]

2. Description of the Related Art With miniaturization and high integration of semiconductor integrated circuits, there is a demand for miniaturization of transistors and higher densities from the viewpoint of well regions. Such a requirement is the same in a semiconductor device including a high breakdown voltage transistor to which a voltage of 10 V or more is applied, for example.

An object of the present invention is to provide a semiconductor device including a well structure in which a well region can be densified and a plurality of high breakdown voltage transistors can be independently driven at different voltages, and a method of manufacturing the same. is there.

[0004]

A semiconductor device according to the present invention comprises a first well of a first conductivity type formed on a semiconductor substrate and a first well formed on the semiconductor substrate and adjacent to the first well. A second well of two conductivity type, a third well of first conductivity type formed in the second well, and a field effect transistor formed in each of the wells;
The field effect transistor has an offset region in a semiconductor substrate around a gate insulating layer, and the offset region is located on a LOCOS (Local Ox) on the semiconductor substrate.
It is composed of a low-concentration impurity layer provided below an (Idification Of Silicon) layer.

In the semiconductor device of the present invention, each of the field effect transistors (for example, MOSFETs) has a LOC.
OS offset structure, that is, L on the semiconductor substrate
By having a structure having an offset region formed of a low-concentration impurity layer below the OCOS layer, a MOSFET with a high drain breakdown voltage and a high breakdown voltage can be configured. That is, by providing an offset region composed of a low-concentration impurity layer below a LOCOS layer for an offset structure (hereinafter, referred to as an “offset LOCOS layer”), the offset region can be formed in a channel compared to a case without the offset LOCOS layer. It can be relatively deep with respect to the area. As a result, the electric field in the vicinity of the drain electrode can be effectively relaxed and the drain withstand voltage can be increased.

Further, according to the semiconductor device of the present invention, the first well of the first conductivity type and the second well of the second conductivity type adjacent to each other on the semiconductor substrate, and further, the first well of the second conductivity type is formed in the second well. With the formed third well of the first conductivity type,
A triple well is configured. According to the triple well, the third well in the second well and the semiconductor substrate are electrically separated. As a result, a well having the same conductivity type as the semiconductor substrate and being electrically separated from the semiconductor substrate can be obtained. Then, the bias condition can be set independently for each well.

Therefore, by forming a high breakdown voltage transistor having a LOCOS offset structure in each well,
For example, the output potential of a high-voltage CMOS (complementary MOS) transistor can be shifted to the positive side and the negative side. Therefore, the semiconductor device of the present invention can be applied to a high power supply voltage of, for example, 10 V or more, more specifically, 20 to 30 V.

Further, according to the semiconductor device of the present invention, since the first well and the second well 21 can be provided adjacent to each other in a self-aligned manner, the integration degree of the well can be increased.

In the semiconductor device according to the present invention, the following aspects can be further taken.

(A) The conductivity type of the well is not particularly limited.
The first conductivity type is P-type and the second conductivity type is N-type, or conversely, the first conductivity type is N-type and the second conductivity type is P-type. Can be.

(B) The third well has a depth approximately equal to the depth of the second well in consideration of the withstand voltage of the field-effect transistor, the punch-through withstand voltage between the semiconductor substrate and the third well, and the like. It can have a depth of 1/2 to 1/3.

(C) The depth of each well is desirably in the following range in consideration of the withstand voltage of the field-effect transistor, the punch-through withstand voltage between the semiconductor substrate and the third well, and the like.

The second well has a depth of 15 to 18 μm.
m, and the third well has a depth of 6 to 8 μm.

(D) It is desirable that the impurity concentration of each well be in the following range in consideration of the threshold voltage and breakdown voltage of the field effect transistor.

The first well has an impurity concentration (surface concentration) of 1 × 10 ^{16 to} 3 × 10 ¹⁶ atoms / cm ³ ,
The second well has an impurity concentration (surface concentration) of 1 ×
10 ^{16 to} 3 × 10 ¹⁶ atoms / cm ³ , and the third well has an impurity concentration (surface concentration) of 1 × 10 ¹⁶ to 3 × 10 ¹⁶ atoms / cm ^3.
It is 10 ¹⁶ atoms / cm ³ .

Here, the surface concentration of impurities means the amount of activated impurities per unit volume on the surface of the semiconductor substrate.

(E) A high-concentration impurity layer constituting a source region or a drain region (hereinafter referred to as a “source / drain region”) of the field effect transistor is surrounded by a low-concentration impurity of the same conductivity type as the impurity layer. It is desirable to provide an impurity layer. By providing such a low-concentration impurity layer, when the field-effect transistor is in an OFF state, the region of the low-concentration impurity layer serves as a depletion layer, so that the drain breakdown voltage can be increased.

(F) It is desirable that the low-concentration impurity layer described in (E) and the channel stopper layer provided below the LOCOS layer on the semiconductor substrate be provided continuously. As described above, the LO for the element isolation region, etc.
Since the low-concentration impurity layer formed below the COS layer and the channel stopper layer are continuous, the conductivity type of the well, particularly the P-type well, under the LOCOS layer is prevented from being inverted, and current leakage occurs. Can be reliably suppressed.

(G) The gate insulating layer of the field effect transistor preferably has a thickness of 60 to 80 nm in consideration of the breakdown voltage of the field effect transistor.

The method for manufacturing a semiconductor device according to the present invention can include the following steps (a) to (h).

(A) a step of selectively forming an oxidation-resistant layer having a masking effect on oxidation on a semiconductor substrate; (b)
By introducing an impurity of the second conductivity type into the semiconductor substrate using the oxidation-resistant layer as a mask, a second conductive type impurity is introduced into the semiconductor substrate.
(C) forming a LOCOS layer on the second well by selectively oxidizing the second well region using the oxidation-resistant layer as a mask;
(D) removing the oxidation-resistant layer; and (e) removing the LOC.
Forming a first well adjacent to the second well in the semiconductor substrate by introducing a first conductivity type impurity into the semiconductor substrate using the OS layer as a mask; (f)
Removing the LOCOS layer; (g) forming a third well in the second well by introducing a first conductivity type impurity into a portion of the second well;
And (h) forming a field effect transistor in each of the first, second and third wells,
In the step (h), (h-1) a LOCOS layer having a predetermined pattern is formed on the semiconductor substrate after introducing N-type and P-type impurities into a predetermined region of the semiconductor substrate. Forming n-type and p-type low-concentration impurity layers in a predetermined region below the layer;
A part of the S layer is formed at least around the gate insulating layer of the field effect transistor; (h-2) a step of forming a gate electrode; (h-3) a high concentration impurity forming a source region or a drain region Forming a layer.

According to this manufacturing method, the well structure of the semiconductor device according to the present invention can be obtained in a self-aligned manner.
A preferred embodiment of this manufacturing method is the same as that of the semiconductor device described above, and a description thereof will be omitted.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

(Manufacturing Process) First, an example of a method for manufacturing a semiconductor device according to the present invention will be described. 1 to 1
FIG. 7 is a sectional view schematically showing a method for manufacturing a semiconductor device according to the embodiment of the present invention.

(Formation of Well) First, as shown in FIG. 1, a P-type silicon substrate 21 is thermally oxidized to form a silicon oxide layer 23 having a thickness of about 40 nm on the surface of the P-type silicon substrate 21. Is done. Thereafter, a silicon nitride layer 25 as an oxidation-resistant layer having a thickness of about 140 to 160 nm is deposited on the silicon oxide layer 23, and a resist layer 27 is formed on the silicon nitride layer 25. This resist layer 27 is patterned so as to be arranged in the region 15 where the P-type first well is formed. Next, using the resist layer 27 as a mask, the silicon nitride layer 25 in the region 13 where the N-type second well is to be formed is etched. Thereafter, using the resist layer 27 and the silicon nitride layer 25 as a mask,
Phosphorus ions 31 are implanted at an acceleration voltage of 0 keV.

Next, as shown in FIG.
7 are removed by etching, the P-type silicon substrate 21 is thermally oxidized using the silicon nitride layer 25 as an oxidation-resistant mask, so that a LOCOS (Local Oxidation Of) having a thickness of about 500 nm is formed on the N-type second well 29.
A Silicon layer 37 is formed. Thereafter, the silicon nitride layer 25 is removed, and boron ions 33 are implanted into the P-type silicon substrate 21 in the region 15 where the P-type first well is to be formed at an acceleration voltage of 60 keV using the LOCOS layer 37 as a mask. Next, the ions implanted into the regions 13 and 15 are diffused (drive-in), so that the P-type first well 3 is formed in the P-type silicon substrate 21.
5 and N-type second wells 29 are formed adjacent to each other in a self-aligned manner.

Thereafter, as shown in FIG. 3, the silicon oxide layer 23 and the LOCOS layer 37 are removed, and a silicon oxide layer 43 is formed on the P-type silicon substrate 21 by thermal oxidation. Next, a patterned resist layer 45 is formed on the silicon oxide layer 43, and the resist layer 45 is used as a mask in the region 11 for forming the P-type third well in the N-type second well 29 at 60 keV. Boron ions 39 are implanted at an accelerating voltage. After removing the resist layer 45,
By diffusing (drive-in) the ions implanted into the region 11 for forming the P-type third well, the P-type third well 41 is formed.

Thus, the P-type silicon substrate 21 has a triple well, that is, a first well 35 of the first conductivity type (P-type in this example) formed on the P-type silicon substrate 21 and a P-type silicon substrate. A second well 29 of the second conductivity type (N-type) formed on the substrate 21 and in contact with the first well 35, and a first conductivity type (N-type) formed in the second well 29 (P-type) third well 41 is formed.

The structure of each of the wells 35, 29, 41 is set in consideration of the breakdown voltage and threshold value of the MOSFET provided in each well 35, 29, 41, the junction breakdown voltage between each well, the punch-through breakdown voltage, and the like. You. Below, MOS
An example of the configuration of a well in a semiconductor device having a withstand voltage of an FET of 10 V or more, particularly 20 to 30 V is shown.

The depth of the well depends on the breakdown voltage of the MOSFET, P
It is set in consideration of the punch-through breakdown voltage between the mold silicon substrate 21 and the third well 41 and the like. For example,
The second well 29 has a depth of 15 to 18 μm, and the third well 41 has a depth of 6 to 8 μm. Since the first well 35 has the same conductivity type as the silicon substrate 21, the depth of the well cannot be specified.

Further, the impurity concentration of the well is
It is set in consideration of the threshold of T and withstand voltage, etc.
You. For example, the first well 35 has an impurity concentration
1 × 10 in surface density¹⁶~ 3 × 10¹⁶atoms / cm^ThreeAnd
The second well 29 has an impurity concentration of 1 × 1 in surface concentration.
0¹⁶~ 3 × 10¹⁶atoms / cm^ThreeAnd the third well 4
1 means that the impurity concentration is 1 × 10¹⁶~ 3 × 10
¹⁶1 × 10¹⁶~ 3 × 10 ¹⁶atoms / cm^ThreeIt is.

The third well 41 is shallower than the second well 29 and takes into consideration the MOSFET breakdown voltage, punch-through breakdown voltage between the P-type silicon substrate 21 and the third well 41, and the like. About 1/2 of the depth of the well 29
It is desirable to have a depth of 1/3.

(Formation of LOCOS Layer, Offset Impurity Layer, Channel Stopper Layer, etc.) Next, as shown in FIG. 4, the silicon oxide layer 43 is removed. After that, the surface of the P-type silicon substrate 21 is thermally oxidized to form the first
Well 35, second well 29 and third well 4
A silicon oxide layer 4 having a thickness of about 40 to 80 nm
7 is formed. Next, a silicon nitride layer is formed on the silicon oxide layer 47, and a resist layer 51 is formed on the silicon nitride layer. By etching the silicon nitride layer using the resist layer 51 as a mask, a patterned silicon nitride layer 49 is formed on the silicon oxide layer 47. This silicon nitride layer 49
Functions as a mask when the low concentration impurity layers 57 and 63 are introduced into the wells in a later step.

Thereafter, as shown in FIG. 5, the resist layer 51 is removed, and a resist layer 53 is formed on the silicon nitride layer 49 and the silicon oxide layer 47. Using this resist layer 53 and silicon nitride layer 49 as a mask, P
By implanting boron ions 55 into the third well 41 of the mold, the second well 29 of the N-type, and the first well 35 of the P-type, a P-type low concentration diffusion layer 57 is formed. This P-type impurity diffusion layer 57 is typically formed in a later step by offset offset layer 57 a in second well 29.
The channel stopper layer 57c is formed in the first and third wells 35 and 41.

Next, as shown in FIG. 6, the resist layer 53 is removed, and a resist layer 61 is formed on the silicon nitride layer 49 and the silicon oxide layer 47. By using the resist layer 61 and the silicon nitride layer 49 as a mask, phosphorus ions 59 are implanted into the third well 41, the second well 29, and the first well 35, thereby forming an N-type low concentration diffusion layer 63. You. The N-type impurity diffusion layer 63 typically becomes an offset impurity layer 63a in the first and third wells 35 and 41 and a channel stopper layer 63c in the second well 29 in a later step. .

Thereafter, as shown in FIG. 7, the resist layer 61 is removed, and the third well 41, the second well 29 and the first well 35 are thermally oxidized using the silicon nitride layer 49 as an oxidation-resistant mask. I do. Thereby, the third well 4
A LOCOS layer 65 having a thickness of about 900 nm is formed on the surfaces of the first, second well 29 and first well 35, and a P-type low concentration diffusion layer 57 (57a, 57b, 57b) is formed under the LOCOS layer 65. 57c) and the N-type low concentration diffusion layer 63 (63a, 63b, 63c) are formed. Thereafter, the silicon nitride layer 49 is removed.

The LOCOS layer 65 formed in this step
Is a portion that constitutes an element isolation region (hereinafter referred to as an “element isolation LOCOS layer 65b”) and a portion around the gate insulating layer that constitutes an offset region (hereinafter, referred to as an “offset LOCOS layer 65b”). 65a ")
And

The P-type low-concentration diffusion layer 57 formed in this step is formed in the N-type second well 29 by an offset impurity layer 57a forming an offset region and a source / drain region.
High concentration impurity layer forming drain region (see FIG. 17)
And a low-concentration impurity layer 57b for reducing the electric field strength. Further, the P-type low-concentration impurity layer 57 includes a channel stopper layer 57c provided below the element isolation LOCOS layer 65b in the P-type first well 35 and the third well 41.

Similarly, the N-type low-concentration diffusion layer 63 is formed in the P-type first and third wells 35 and 41 by the offset impurity layer 63a forming the offset region and the high impurity concentration forming the source / drain region. A low-concentration impurity layer 63 provided outside the high-concentration impurity layer to reduce the electric field intensity;
b. Further, the N-type low concentration impurity layer 63
In the N-type second well 29, the element isolation LOCOS
Including a channel stopper layer 63c provided below the layer 65b.

As will be described in detail later, in each of the wells 35, 29, and 41, the low-concentration impurity layer for relaxing the electric field strength and the channel stopper layer are provided in contact with each other.

(Formation of Gate Insulating Layer) Silicon Oxide Layer 4
7 is removed and the surface of the P-type silicon substrate 21 is thermally oxidized to form a gate insulating layer 7 having a thickness of about 60 to 80 nm.
8 is formed.

(Formation of Channel Region) Next, as shown in FIG. 8, a resist layer 69 is formed on the wafer including the LOCOS layer 65. Using this resist layer 69 as a mask, phosphorus ions 67 are implanted into the N-channel doped regions of the P-type third well 41 and the first well 35 to form a channel region.

Thereafter, as shown in FIG. 9, the resist layer 69 is removed, and a resist layer 71 is formed on the wafer including the LOCOS layer 65. Using this resist layer 71 as a mask, boron ions 73 are implanted into the P-channel doped region of the N-type third well 29 to form a channel region.

(Formation of Gate Electrode) Thereafter, as shown in FIG. 10, a conductive polysilicon layer is deposited on the wafer including the LOCOS layer 65. Next, a resist layer 81 is formed on the polysilicon layer, and the polysilicon layer is etched using the resist layer 81 as a mask, whereby a gate electrode 79 is formed on the silicon oxide layer (gate insulating layer) 48. .

(Formation of Source / Drain Regions)
As shown in FIG. 11, the resist layer 81 is removed, and a resist layer 83 is formed on the wafer including the gate electrode 79. This resist layer 83, gate electrode 79 and LOC
Using the OS layer 65 as a mask, phosphorus ions 85 are implanted, and N
An impurity layer 80N forming source / drain regions of the channel transistor is formed.

Thereafter, as shown in FIG. 12, the resist layer 83 is removed, and a resist layer 87 is formed on the wafer including the gate electrode 79. Using the resist layer 87, the gate electrode 79 and the LOCOS layer 65 as a mask, boron ions 89 are implanted to form a high-concentration impurity layer 80P constituting source / drain regions of a P-channel transistor.

(Formation of interlayer insulating layer and wiring)
As shown in FIG. 13, the resist layer 87 is removed, and a first interlayer insulating layer 91 is deposited on the wafer including the gate electrode 79. A resist layer 93 is formed on interlayer insulating layer 91, and interlayer insulating layer 9 is formed using resist layer 93 as a mask.
By etching 1, contact holes 91 a are formed in interlayer insulating layer 91.

Thereafter, as shown in FIG. 14, the resist layer 93 is removed, a conductive layer such as an aluminum alloy or copper is deposited in the contact hole 91a and on the interlayer insulating layer 91, and the conductive layer is patterned. By doing
A first wiring layer 95 is formed.

Next, as shown in FIG. 15, a second interlayer insulating layer 96 is deposited on the first wiring layer 95 and the first interlayer insulating layer 91, and a resist is formed on the interlayer insulating layer 96. The layer 97 is formed. By etching the second interlayer insulating layer 96 using the resist layer 97 as a mask, a contact hole 97a is formed in the interlayer insulating layer 96.

Thereafter, as shown in FIG. 16, the resist layer 97 is removed, and a second wiring layer made of a conductive layer such as an aluminum alloy or copper is formed in the contact hole 97a and on the second interlayer insulating layer 96. 99 are formed.

Next, as shown in FIG. 17, a passivation layer is formed on the second wiring layer 99 and the second interlayer insulating layer 96. In this embodiment mode, a layer in which the silicon oxide layer 101 is deposited as the passivation layer and the silicon nitride layer 103 is deposited over the silicon oxide layer 101 can be used.

Through the above steps, the semiconductor device according to the present embodiment is manufactured.

(Semiconductor Device) Hereinafter, this semiconductor device will be described. FIG. 17 schematically shows a cross section of a semiconductor device formed by the manufacturing method according to the present embodiment. FIG. 18 shows the second N-channel MOSFET 3 shown in FIG.
The main part including 00N and P-channel MOSFET 200P is shown in an enlarged manner. FIG. 18 includes a portion not shown in FIG. FIG. 19 is a plan view of a silicon substrate of the second N-channel MOSFET 300N and the P-channel MOSFET 200P shown in FIGS. FIG. 19 shows a state where the insulating layer on the silicon substrate is removed, and shows the conductivity type of the impurity layer formed on the silicon substrate.

In this semiconductor device, a P-type first well 35 and an N-type second well 29 are formed in contact with each other, and a P-type third well 41 is formed as an N-type second well. 2
9. In the first well 35, the first well
Is formed, a P-channel MOSFET 200P is formed in the second well 29, and a second N-channel MOSFET 200P is formed in the third well 41.
OSFET 300N is formed. And each MO
The SFETs 100N, 200P, and 300N have element isolation L
It is separated by the OCOS layer 65b.

Each MOSFET has a LOCOS offset structure. That is, in each MOSFET, an offset region is provided between the gate electrode and the high-concentration impurity layer forming the source / drain region. This offset region is formed of a low-concentration impurity layer below the offset LOCOS layer provided in a predetermined region on the silicon substrate.

The N channel MOSFET and the P
The configuration of the channel MOSFET will be described.

First, the second N-channel MOSFET 30
0N will be described. This N-channel MOSFET3
00N is LOCO as shown in FIGS.
It has an S offset structure. N-channel MOSFET3
00N is a gate insulating layer 78 provided on the P-type third well 41, a gate electrode 79 formed on the gate insulating layer 78, and an offset LOCOS layer provided around the gate insulating layer 78. 65a and this offset L
An offset impurity layer 63a formed of an N-type low-concentration impurity layer formed below the OCOS layer 65a;
N-type high concentration impurity layers 80N, 80N constituting source / drain regions provided outside OCOS layer 65a.
And

Next, the P-channel MOSFET 200P will be described. This P-channel MOSFET 200P
Has a LOCOS offset structure, as shown in FIGS. P-channel MOSFET 200P
Are a gate insulating layer 78 provided on the N-type second well 29, a gate electrode 79 formed on the gate insulating layer 78, and an offset LOCOS layer 65a provided around the gate insulating layer 78. And this offset LOCO
An offset impurity layer 57a formed of a P-type low-concentration impurity layer formed below the S layer 65a;
P-type high-concentration impurity layers 80P, 80P constituting source / drain regions provided outside the S layer 65a.

First N-channel MOSFET 100N
The basic structure is the second N-channel MOSFET 30
Since it is the same as 0, its detailed description is omitted.

Each MOSFET 100N, 200N
The P, 300N gate insulating layer 78 depends on, for example, the withstand voltage required for the MOSFET.
More specifically, when a voltage of 10 to 30 V is applied, the film preferably has a thickness of 60 to 80 nm.

The N-channel MOSFET 300N and the P-channel MOSFET 200P are provided with an element isolation LOCOS.
It is electrically separated by the layer 65b. Element isolation L
The OCOS layer 65b is provided on the boundary between the P-type third well 41 and the N-type second well 29. Then, in the third well 41 of the P type, the element isolation L
A channel stopper layer 57c made of a P-type low-concentration impurity layer is formed below the OCOS layer 65b. In the N-type second well 29, an element isolation LOCOS layer 65b is formed.
Below this is formed a channel stopper layer 63c made of an N-type low concentration impurity layer.

Further, in the third well 41,
Between the N-type high concentration impurity layer 80N constituting the source / drain region and the P-type channel stopper layer 57c,
An N-type low concentration impurity layer 63b is provided. Similarly, in the second well 29, a P-type low-concentration impurity layer 57b is provided between the P-type high-concentration impurity layer 80P constituting the source / drain region and the N-type channel stopper layer 63c. Is provided.

Then, in the third well 41,
The N-type low-concentration impurity layer 63b and the P-type channel stopper layer 57c are formed continuously. Similarly, in the second well 29, the P-type low concentration impurity layer 57b
And the N-type channel stopper layer 63c are formed continuously.

Element isolation LOC for isolating each MOSFET
By providing low concentration impurity layers 63b and 57b adjacent to the high concentration impurity layers 80N and 80P constituting the source / drain regions below the OS layer 65b, the MOS
When the FET is in the OFF state, the low-concentration impurity layer 63
The regions b and 57b serve as a depletion layer, and the drain breakdown voltage can be increased.

In the P-type third well 41, the low-concentration impurity layer 63b formed below the element isolation LOCOS layer 65b and the channel stopper layer 57c are continuous, so that the element isolation LOCOS layer Inversion of the conductivity type of the third well 41 under 65b is prevented, and current leakage can be suppressed. That is, if the low-concentration impurity layer 63b and the channel stopper layer 57c are separated from each other, a P-type impurity (boron or the like) contained in the P-type third well 41 in a region where the low-concentration impurity layer and the channel stopper layer are not present Is composed of a silicon oxide layer.
Absorbed by the OCOS layer 65b, and conversely,
N-type impurities (such as phosphorus) from the layer 65b to the third well 4
It is released into 1. As a result, in a region where the low-concentration impurity layer and the channel stopper layer are not present, a phenomenon in which the conductivity type is reversed due to a relative shortage of the P-type impurity easily occurs.

This phenomenon occurs because the P-type third well formed by counter-doping a P-type impurity such as boron in the N-type second well 29 having a high N-type impurity concentration such as phosphorus.
This is remarkable in the well 41 of the first embodiment, and does not cause a problem in the second well 29 of the N type and the first well 35 of the P type which is not doped with the counter. In addition, this phenomenon
Although there is almost no problem with a low-breakdown-voltage MOSFET that constitutes a logic circuit or the like, a problem easily occurs with the high-breakdown-voltage MOSFET of this embodiment.

In this example, the high-concentration impurity layers 8 forming the source / drain regions are also formed in the second well 29.
A P-type low-concentration impurity layer 57b is provided between 0P and the channel stopper layer 63c.

In the semiconductor device shown in FIG. 18, a contact layer 80CP made of a P-type high-concentration impurity layer is provided in each of the first and third wells 35 and 41. Is provided with a contact layer 80CN made of an N-type high concentration impurity layer. In addition,
The contact layers 80CP and 80CN are not shown in FIG. These contact layers 80CP or 80CP
CN includes a high-concentration impurity layer 80N or 80P forming source / drain regions, respectively, and a LOCOS layer 65C.
Are separated from each other.

The LOCOS layer 6 on the third well 41
Below 5C, an N-type low-concentration impurity layer 63b is provided adjacent to the N-type high-concentration impurity layer 80N, and a P-type low-concentration impurity layer 57C is provided adjacent to the contact layer 80CP. . And an N-type low concentration impurity layer 63b;
The P-type low-concentration impurity layer 57C is continuous. The advantage that these low-concentration impurity layers 63b and 57C are continuous is that the element isolation LOCO
This is similar to the advantage that the low-concentration impurity layer 57b and the channel stopper layer 63c are continuous below the S layer 65b.

Similarly, the LOC on the second well 29
Under the OS layer 65C, a P-type low-concentration impurity layer 57b is provided adjacent to the P-type high-concentration impurity layer 80P, and an N-type low-concentration impurity layer 63C is adjacent to the contact layer 80CN. Is provided.

(Operation / Effect) In this embodiment, each MO
Since the SFET has the LOCOS offset structure, a MOSFET with a high withstand voltage and a high withstand voltage can be configured. That is, the offset impurity layer 63 made of a low-concentration impurity layer is provided below the offset LOCOS layer 65a.
a, 57a, the offset LOCOS
The offset impurity layers 63a and 57
a can be made relatively deep with respect to the channel region. As a result, when the MOSFET is in the OFF state, a deep depletion layer can be formed by the offset impurity layers 63b and 57b. As a result, the electric field in the vicinity of the drain electrode can be reduced and the drain withstand voltage can be increased.

According to the semiconductor device of the above embodiment, P
A twin well consisting of an N-type second well 29 and a P-type first well 35 adjacent to each other is formed in the silicon substrate 21, and a P-type third well is formed in the N-type second well 29. Are formed to form a triple well. By doing so, the third well 41 in the second well 29 and the P-type silicon substrate 21 are electrically separated. Therefore, the bias conditions can be set independently for each well.

The voltage applied to each of the third well 41 and the second well 29 can be set independently of the voltage of the silicon substrate. Therefore, LOCOS is added to each well.
By forming a high breakdown voltage transistor having an offset structure, for example, as shown in FIG.
(Complementary MOS) The output potential of the transistor can be shifted to the positive side and the negative side with respect to the substrate potential. for that reason,
For example, even a high power supply voltage of 10 V or more, particularly 20 to 30 V can be applied to the MOS transistor of the present embodiment.

According to the above-described embodiment, the P-type first well 35 and the N-type second well 29 can be provided adjacent to each other in a self-aligned manner. Can be enhanced.

Then, in order to perform the ion implantation of the impurity when forming the first well 35 and the third well 41 in another step, the surface concentration of the impurity in each well may be set independently. it can.

Further, the high breakdown voltage transistor of the present embodiment can be formed on the same chip as a semiconductor device forming a logic circuit.

The present invention is not limited to the above embodiment,
Various aspects can be taken within the scope of the invention. For example, in the above embodiment, the first conductivity type is P-type and the second conductivity type is N-type. However, the opposite conductivity type may be used.
Further, the layer structure or the planar structure of the semiconductor device may have a structure different from that of the above embodiment depending on the design of the device.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the embodiment of the present invention, which is a step subsequent to the step of FIG. 1;

FIG. 3 is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the embodiment of the present invention, which is a step subsequent to the step in FIG. 2;

FIG. 4 is a cross-sectional view showing a step subsequent to the step shown in FIG. 3, illustrating the method for manufacturing a semiconductor device according to the embodiment of the present invention;

FIG. 5 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention, which is a step subsequent to the step in FIG. 4;

FIG. 6 is a cross-sectional view showing a step subsequent to the step shown in FIG. 5, illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 7 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention, which is a step subsequent to the step in FIG. 6;

FIG. 8 is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the embodiment of the present invention, which is a step subsequent to the step in FIG. 7;

FIG. 9 is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the embodiment of the present invention, which is a step subsequent to the step in FIG. 8;

FIG. 10 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention, which is a step subsequent to the step in FIG. 9;

FIG. 11 is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the embodiment of the present invention, which is a step subsequent to the step in FIG. 10;

FIG. 12 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention, which is a step subsequent to the step in FIG. 11;

FIG. 13 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention, which is a step subsequent to the step in FIG. 12;

FIG. 14 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention, which is a step subsequent to the step in FIG. 13;

FIG. 15 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention, which is a step subsequent to the step in FIG. 14;

FIG. 16 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention, which is a step subsequent to the step in FIG. 15;

FIG. 17 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention, which is a step subsequent to the step in FIG. 16;

FIG. 18 is an enlarged cross-sectional view showing a main part of the semiconductor device according to the embodiment of the present invention;

FIG. 19 is an enlarged plan view showing a main part of the semiconductor device according to the embodiment of the present invention;

FIG. 20 is a diagram showing an equivalent circuit of a high withstand voltage CMOS to which the semiconductor device according to the embodiment of the present invention is applied;

[Explanation of symbols]

Reference Signs List 11 Area for forming P-type third well 13 Area for forming N-type second well 15 Area for forming P-type first well 21 P-type silicon substrate 23 Silicon oxide layer 25 Silicon nitride layer 29 Second well 35 First well 37 LOCOS layer 41 Third well 57 P-type low-concentration impurity layer 57a Offset impurity layer 57b Low-concentration impurity layer 57c Channel stopper layer 63 N-type low-concentration impurity layer 63a Offset impurity layer 63b Low-concentration impurity layer 63c Channel stopper layer 65 LOCOS layer 65a Offset LOCOS layer 65b Isolation LOCOS layer 79 Gate electrode 80N, 80P High-concentration impurity layer for source / drain regions 91 First interlayer insulating layer 95 First wiring Layer 96 Second interlayer insulating layer 99 Second wiring layer

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F032 AA14 AC01 BA05 BB06 CA17 CA24 CA25 5F048 AA05 AC01 AC03 BA01 BB05 BB16 BC02 BC06 BC20 BD04 BE02 BE03 BE05 BE06 BE09 BF11 BF16 BG12 BH07 DA25

Claims (18)

[Claims] A first well of a first conductivity type formed in a semiconductor substrate; a second well of a second conductivity type formed in the semiconductor substrate and adjacent to the first well; A third well of the first conductivity type formed in the two wells, a field effect transistor formed in each of the wells,
Wherein the field effect transistor has an offset region in the semiconductor substrate around the gate insulating layer, the offset region comprises a low concentration impurity layer provided below the LOCOS layer on the semiconductor substrate, Semiconductor device. 2. The semiconductor device according to claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type. 3. The semiconductor device according to claim 1, wherein the first conductivity type is N-type, and the second conductivity type is P-type. 4. The semiconductor device according to claim 1, wherein the third well has a depth of about １ ／ to ３ of a depth of the second well. 5. The semiconductor device according to claim 1, wherein the second well has a depth of 15 to 18 μm, and the third well has a depth of 6 to 8 μm. 6. The method according to claim 1, wherein the first well has an impurity concentration of 1 × 10 ^{16 to} 3 ×.
10 ¹⁶ atoms / cm ³ , and the second well has an impurity concentration of 1 × 10 ^{16 to} 3 ×
10 ¹⁶ atoms / cm ³ , and the third well has an impurity concentration of 1 × 10 ^{16 to} 3 ×
A semiconductor device having 10 ¹⁶ atoms / cm ³ . 7. The low-concentration impurity layer having the same conductivity type as the impurity layer around the high-concentration impurity layer forming the source region or the drain region of the field-effect transistor. Semiconductor device. 8. The semiconductor device according to claim 7, wherein the low-concentration impurity layer and a LOCOS on the semiconductor substrate are provided.
A semiconductor device provided continuously with a channel stopper layer provided below the layer. 9. The semiconductor device according to claim 1, wherein the gate insulating layer of the field-effect transistor has a thickness of 60 to 80 nm. 10. A method for manufacturing a semiconductor device, comprising the following steps (a) to (h). (A) selectively forming an oxidation-resistant layer having a masking effect on oxidation on a semiconductor substrate; and (b) introducing a second conductivity type impurity into the semiconductor substrate using the oxidation-resistant layer as a mask. Forming a second well in the semiconductor substrate, (c) selectively oxidizing a surface region of the second well using the oxidation-resistant layer as a mask, thereby forming a LOCOS layer on the second well. (D) removing the oxidation-resistant layer; (e) introducing a first conductivity type impurity into the semiconductor substrate using the LOCOS layer as a mask, thereby forming the second well in the semiconductor substrate. Forming a first well adjacent to the second well; (f) removing the LOCOS layer; and (g) introducing a first conductivity type impurity into a portion of the second well to form the second well. In the well (H) forming a field-effect transistor in each of the first, second, and third wells. In the step (h), (h-1) After introducing N-type and P-type impurities into a predetermined region of the semiconductor substrate, a LOCOS layer having a predetermined pattern is formed on the semiconductor substrate, whereby the LOCOS
Forming N-type and P-type low-concentration impurity layers in a predetermined region below the layer, and forming a part of the LOCOS layer at least around a gate insulating layer of the field-effect transistor; (h-2) A) forming a gate electrode; and (h-3) forming a high-concentration impurity layer forming a source region or a drain region. 11. The method for manufacturing a semiconductor device according to claim 10, wherein the first conductivity type is P-type and the second conductivity type is N-type. 12. The method according to claim 10, wherein the first conductivity type is N-type and the second conductivity type is P-type. 13. The method of manufacturing a semiconductor device according to claim 10, wherein the third well has a depth of about ２〜 to ３ of a depth of the first well. . 14. The semiconductor device according to claim 10, wherein the second well has a depth of 15 to 18 μm, and the third well has a depth of 6 to 8 μm. Production method. 15. The method according to claim 10, wherein the first well has an impurity concentration of 1 × 10 ^{16 to} 3 ×.
10 ¹⁶ atoms / cm ³ , and the second well has an impurity concentration of 1 × 10 ^{16 to} 3 ×
10 ¹⁶ atoms / cm ³ , and the third well has an impurity concentration of 1 × 10 ^{16 to} 3 ×
A method for manufacturing a semiconductor device, which is 10 ¹⁶ atoms / cm ³ . 16. The low-concentration impurity layer of the same conductivity type as the impurity layer around the high-concentration impurity layer forming the source region or the drain region of the field-effect transistor. Manufacturing method of a semiconductor device. 17. The semiconductor device according to claim 16, wherein the low-concentration impurity layer and a LOCOS on the semiconductor substrate are provided.
A method for manufacturing a semiconductor device, wherein a channel stopper layer provided below a layer is provided continuously. 18. The method according to claim 10, wherein the gate insulating layer of the field-effect transistor has a thickness of 60 to 80 nm.