JP3101516B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having MOS transistors having different gate oxide film thicknesses, and to reduce the number of steps required for manufacturing the semiconductor device. The present invention relates to a method for manufacturing a semiconductor device capable of reducing a leak current in an inversion region.

[0002]

2. Description of the Related Art With an increase in demand for TFT-type liquid crystal-related products in recent years, development and manufacture of LCD driving LSIs have become extremely active in the semiconductor industry. Since this LCD driving LSI is composed of an output driver part operating at a high power supply voltage of 21 V and a logic circuit part operating at a standard power supply voltage of 5 V, the reliability of the breakdown voltage surface of the gate oxide film is taken into consideration. The gate oxide film in the output driver portion is formed thicker than the logic circuit portion.

A method of manufacturing a conventional semiconductor device will be described below with reference to FIGS. In addition,
Although the conventional semiconductor device has a CMOS structure,
For simplicity of explanation, only the N channel side is shown. First, in FIG. 11, a SiN film (3) is formed on the entire surface of a P-type silicon substrate (1) via a pad oxide film (2).
Next, in FIG. 12, by selectively etching the SiN film (3) using the resist film (4) as a mask, the first SiN film (3A) and the second SiN film (3
Form B). Thereafter, in FIG. 13, boron ions (11B +) are added to the silicon substrate (1) using them as a mask.
Is ion-implanted. At this time, on the P channel side (not shown), a step of covering with a resist film is performed, and the above-described ion implantation is performed.

In FIG. 14, selective oxidation is performed using the first SiN film (3A) and the second SiN film (3B) as an oxidation-resistant mask to form a LOCOS oxide film (5). At this time, the ion-implanted boron is deposited on the substrate (1).
And a channel stopper layer (6) is formed under the LOCOS oxide film (5) in the N-channel region.
Thereafter, through a step of removing the SiN film and the pad oxide film (2), a sacrificial oxide film (7) is formed in FIG.
Cover the channel side (not shown) with a resist film (8)
First channel ion implantation with boron ions (11B +) is performed.

Next, in FIG. 16, a resist film (9) is formed so as to expose the second MOS transistor formation region and cover the first MOS transistor formation region, and form the resist film (9). Is used as a mask to perform a second ion implantation with phosphorus ions (31P +). This is an ion implantation step required to adjust the threshold (Vth) of the second MOS transistor.

Next, the sacrificial oxide film (7) is removed, and FIG.
Then, a thick gate oxide film (10) of about 600 ° is formed by thermal oxidation. Next, in FIG.
A resist film (11) having an opening is formed on the MOS transistor formation region, and the gate oxide film (10) on the region is selectively removed by etching. Then, in FIG. 19, the resist film (11) is removed,
A second gate oxidation step is performed to form a thin gate oxide film (10B) of about 240 ° on the first MOS transistor formation region, and to form a gate oxide film (10) on the second MOS transistor formation region. 700 film thickness
Thicken to about Å. Next, in FIG. 20, a gate electrode (12) made of polysilicon or the like is formed on the gate oxide film (10, 10B), and the gate electrode (1) is formed.
Using the mask 2) as a mask, phosphorus ions (31P +) or arsenic ions (75As +) are ion-implanted into the silicon substrate (1) to form a source layer (13) and a drain layer (14).

By the above steps, the first MOS transistor having a gate oxide film (10B) of about 240 ° and the second MOS transistor having a gate oxide film (10) of about 700 °
MOS transistors are formed, and the former is used for a logic circuit portion of an LCD driving LSI, and the latter is used for an output driver portion.

[0008]

However, in the conventional manufacturing method, two types of M having different gate oxide film thicknesses are used.
In order to set the threshold value of the OS transistor, two channel ion implantation steps and the accompanying two mask alignment steps have to be performed, resulting in a problem that the number of steps is large.

Further, in the conventional manufacturing method, in order to form gate oxide films having different thicknesses, gate oxidation is performed twice after the channel ion implantation. For this reason, the diffusion of boron implanted in the first time increases the surface concentration of the channel, and the amount of phosphorus ions implanted in the second ion implantation is increased in order to compensate for this and secure an appropriate threshold value. I had to. As a result, there is also a problem that the leak current between the source and the drain in the weak inversion region (Weak Inversion Region) of the second MOS transistor having a thick gate oxide film increases.

The present invention has been made in view of the above problems, and has as its object to provide a method of manufacturing a semiconductor device which can reduce the number of steps and improve the weak inversion characteristics of a MOS transistor. And

[0011]

A method of manufacturing a semiconductor device according to the present invention comprises a first MOS transistor and a first M transistor.
Forming a first and second SiN films separated from each other on a semiconductor substrate of one conductivity type in a method of manufacturing a semiconductor device including a second MOS transistor having a gate oxide film thicker than an OS transistor; , The second Si
A step of forming a resist film so as to cover the N film, and a step of injecting one conductivity type impurity into the LOCOS oxide film forming region of the substrate at an acceleration voltage such that the first and second SiN films function as a mask. 1 ion implantation step and first Si
Second Si penetrating through the N film and coated with the resist film
A second ion implantation step of implanting an impurity of one conductivity type into the first MOS transistor formation region at an acceleration voltage that does not penetrate the N film, and a first and second S after the removal of the resist film;
forming a LOCOS oxide film by performing thermal oxidation using the iN film as an oxidation resistant mask;
forming a thick gate oxide film after removing the iN film;
A third ion implantation step of implanting an impurity of one conductivity type into the first and second transistor formation regions of the substrate using the LOCOS oxide film as a mask;
Selectively removing the gate oxide film on the MOS transistor formation region, and forming the second gate oxide film on the first MOS transistor formation region to be thinner than the second MOS transistor formation region. And a step.

[0012]

According to the present invention, first, in the second ion implantation step, only the first MOS transistor is implanted, and then, in the third ion implantation step, both transistors are implanted. Thus, the threshold value is controlled. That is, the first MOS transistor is controlled only by the third ion implantation, while the second MOS transistor is controlled by the threshold in the implantation amount obtained by adding the second and third ion implantations. Done. However, in the second ion implantation step, the same resist film as that in the first ion implantation step for forming the channel stopper layer is used, so that the number of mask alignment steps can be reduced by one compared with the related art.

Further, according to the present invention, since there is only one gate oxidation step after the third ion implantation step, the amount of heat treatment after channel ion implantation can be reduced as compared with the conventional example. The diffusion of boron can be minimized. Therefore, unlike the related art, there is no need for counter implantation of phosphorus ions into the second MOS transistor.
This reduces the total channel implant and also reduces N
Since there is no type impurity, the leak current in the weak inversion region can be reduced.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device according to one embodiment of the present invention will be described below with reference to the drawings. Although the semiconductor device according to this embodiment has a CMOS structure in actuality, only the N-channel side is shown for simplicity of explanation.
First, in FIG. 1, Si is formed on a P-type silicon substrate (11) through a pad oxide film (12) by a low pressure CVD method.
An N film (13) (silicon nitride film) is formed. Next, in FIG. 2, the resist film (14) is used as a mask to form SiN.
By selectively etching the film (13), the first
The second SiN film (13B) and the second SiN film (13B) are formed.

Next, referring to FIG. 3, a resist film (14)
Then, a resist film (15) having a thickness of about 1 μm is formed again so as to cover the second SiN film (13B). At this time, since the P channel side (not shown) is also covered with the resist film at the same time, the number of mask alignment steps does not change in the steps so far as compared with the conventional example. A feature of the present invention is that two ion implantation steps described below are performed.

That is, in the first ion implantation step, boron ions (11B +) are applied to the substrate (11) at an accelerating voltage at which the first and second SiN films (13A, 13B) function as a mask, for example, 40 KeV. A first injection layer (16) is formed by injecting into the LOCOS oxide film formation region. This ion implantation is for forming the channel stopper layer (19), and the implantation amount is 5E15 / cm 2 (5E15
Represents 5 times 10 to the 15th power. The same applies hereinafter. ). In the subsequent second ion implantation step, the first SiN film (13A) is penetrated and the resist film (15) is formed.
Boron ions (11B +) are implanted into the first MOS transistor formation region of the substrate (11) at an acceleration voltage that does not penetrate the second SiN film (13B) covered with, for example, 140 KeV, and the second implanted layer ( 17) is formed. This ion implantation is for controlling the threshold value of the first MOS transistor having a small thickness to be formed later, and the implantation amount is 4E12 / cm2.

Next, in FIG. 4, a resist film (15)
Is removed, the first and second SiN films (13A, 1A) are removed.
Using 3B) as a mask, wet oxidation is performed at about 1000 ° C. to form a 8000 ° LOCOS oxide film (18). At this time, the first and second ion-implanted layers (1
6, 17) are diffused, a channel stopper layer (19) under the LOCOS oxide film (18) and a channel-doped diffusion layer (20) in the channel region of the first MOS transistor.
Are formed integrally.

Next, in FIG. 5, the first and second Si
After removing the N films (13A, 13B) and the pad oxide film (12), sacrificial oxidation (dummy oxidation) is performed. After removing the sacrificial oxide film, thermal oxidation is further performed at 950 ° C.
A thick gate oxide film (21) of about Å is formed. Next, in FIG. 6, a resist film (22) covering the P channel side is formed, and boron ions (11B +) are implanted into the first and second MOS transistor formation regions of the substrate (11). An implantation step is performed to form a third implantation layer (23). This ion implantation is performed at an accelerating voltage of 14
This is performed under the conditions of 0 KeV and an injection amount of 1.5E12 / cm2. Thus, the threshold value of the second MOS transistor is determined by the main ion implantation, and the threshold value of the first MOS transistor is determined by the sum of the main ion implantation and the second ion implantation. become.

Next, in FIG. 7, the thick gate oxide film (21) on the first MOS transistor formation region is selectively removed. In this step, a resist film (25) having an opening (24) is formed on the first MOS transistor formation region, and the gate oxide film (21) is formed by a diluted HF solution.
Are selectively removed by etching. Then, as shown in FIG. 8, after removing the resist film (25), a second gate oxidation step is performed to form a thinner gate oxide on the first MOS transistor formation region than on the second MOS transistor formation region. A film (26) is formed. In this gate oxidation step, a thin gate oxide film (26) of about 240 ° is formed by thermal oxidation at about 900 ° C., and the thick gate oxide film (21) is further thickened to about 700 ° in this oxidation step. Therefore, finally, for the first MOS transistor, a thin gate oxide film (2
6) is formed, and for the second MOS transistor, a thick gate oxide film (21) of about 700 ° is formed.

Thereafter, in FIG. 9, a gate electrode (27) made of polysilicon or the like is formed on each of the gate oxide films (21, 22) by a conventional method. A resist film (28) for covering the P channel side is formed, and phosphorus ions (31P +) or arsenic ions (75As +) are ion-implanted using the resist film (28) and the gate electrode (27) as a mask to form a source layer (29). And forming a drain layer (30).

By the above steps, a first MOS transistor having a gate oxide film (26) of about 240 °,
Second M having a gate oxide film (21) of about 700 °
An OS transistor is formed, and the former is an LCD driving LS
The latter can be used for the output driver part for the logic circuit part of I. Here, a method of controlling the threshold values of the first and second MOS transistors will be described with reference to FIG. FIG. 10 is a diagram showing the relationship between the threshold value and the boron ion implantation amount. Since the thickness of the gate oxide film is different between the first MOS transistor and the second MOS transistor, as shown in the figure, the threshold value of the second MOS transistor is higher for the same implantation amount, Also, the slope with respect to the injection amount is large.

Therefore, in the present embodiment, first, the second
In the ion implantation step, 4E12 / cm2 is implanted only into the first MOS transistor, and then in the third ion implantation step, 1.5E12 / cm2 is implanted into both transistors, so that the threshold voltage is reduced. Controlling. That is,
In the second MOS transistor, a desired threshold value of about 1.0 V is obtained at an implantation amount of 1.5E12 / cm 2, while in the first MOS transistor,
5.5E12 / cm that is obtained by adding the third ion implantation
At an implant dose of two, a substantially equal threshold of about 0.9 V is obtained. In the second ion implantation step, the same resist film (15) as in the first ion implantation step for forming the channel stopper layer (19) is used as it is. One less.

Further, according to the present embodiment, after the third ion implantation step, there is only one gate oxidation step.
The amount of heat treatment after channel ion implantation can be reduced as compared with the conventional example, and as a result, unlike the conventional example, the counter implantation of phosphorus ions into the second MOS transistor is not required. In FIG. 10, as indicated by the dashed line, in the conventional example, the threshold value was too high, so that counter injection was required. As a result, the total ion implantation amount is reduced, and the concentration on the channel surface can be set relatively high, so that the leakage current in the weak inversion region can be significantly reduced.

[0024]

As described above, according to the present invention,
In a method of manufacturing a semiconductor device including a first MOS transistor and a second MOS transistor having a gate oxide film thickness larger than that of the first MOS transistor, a threshold value of each transistor is controlled to a desired value. The number of times of mask alignment required in the ion implantation process for the semiconductor device can be reduced as compared with the related art, which can contribute to the rationalization of the manufacturing process. Further, according to the present invention, the weak inversion characteristics of the second MOS transistor can be improved. In particular, by applying the present invention to the manufacture of an LCD driving LSI having two power supplies of a low voltage system and a high voltage system, it is possible to contribute to rationalization of the manufacturing process and lower power consumption.

[Brief description of the drawings]

FIG. 1 is a first sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 2 is a second sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 3 is a third sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 4 is a fourth sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 5 is a fifth sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 6 is a sixth sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention.

FIG. 7 is a seventh sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 8 is an eighth sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 9 is a ninth sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention.

FIG. 10 is a diagram showing a relationship between a threshold value of a MOS transistor and an ion implantation amount.

FIG. 11 is a first sectional view illustrating a method for manufacturing a semiconductor device according to a conventional example.

FIG. 12 is a second cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 13 is a third sectional view for explaining the method of manufacturing the semiconductor device according to the conventional example.

FIG. 14 is a fourth sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 15 is a fifth sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 16 is a sixth sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 17 is a seventh sectional view illustrating the method of manufacturing the semiconductor device according to the conventional example.

FIG. 18 is an eighth sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 19 is a ninth cross-sectional view illustrating the method of manufacturing the semiconductor device according to the conventional example.

FIG. 20 is a tenth sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/336 H01L 21/8234 H01L 27/088 H01L 29/78

Claims (1)

(57) [Claims] A first MOS transistor and a first MOS transistor;
A method of manufacturing a semiconductor device comprising a second MOS transistor having a gate oxide film thicker than an OS transistor, comprising: forming first and second SiN films separated from each other on a semiconductor substrate of one conductivity type; Forming a resist film so as to cover the second SiN film; and LOCOS oxide film forming region of the substrate by applying an impurity of one conductivity type at an acceleration voltage such that the first and second SiN films function as a mask. A first ion implantation step of implanting one conductivity type impurity at an acceleration voltage that penetrates the first SiN film and does not penetrate the second SiN film covered with the resist film The second to implant into the region
LOCOS by removing the resist film and performing thermal oxidation using the first and second SiN films as oxidation resistant masks.
Forming an oxide film, forming a thick gate oxide film after removing the first and second SiN films, forming a thick gate oxide film, and using the LOCOS oxide film as a mask to remove impurities of one conductivity type from the substrate. A third ion implantation step of implanting into the first and second transistor formation regions, a step of selectively removing a gate oxide film on the first MOS transistor formation region, and a step of: , The second MOS
A second gate oxidation step of forming a thinner gate oxide film on the transistor formation region.