JP2001110910A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the number of processes where a MOS transistor and a capacitive element are formed on the same semiconductor substrate. SOLUTION: First ions are implanted into a P-type semiconductor substrate 111 penetrating through first polysilicon layers 115a and 115b and a first and a second oxide films 113 and 114 using a photoresist layer 116 as a mask. By this setup, P-type layers 117a and 117b are formed on the surface of the P-type semiconductor substrate 111. At this point, the P-type layer 117b is used for controlling the threshold voltage of a MOS transistor. Then, as shown in Figure 2 (a), N-type impurity ions are implanted with an accelerating energy using the same photoresist layer 116 as a mask, so as to penetrate through the first polysilicon layer 115b and the first oxide film 113 but not to penetrate through the second oxide film 114, and the lower electrode 118 of a capacitive element is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device.
The present invention relates to a technique for reducing the number of steps when a transistor, particularly a MOS transistor having a high source / drain withstand voltage and a high gate withstand voltage (hereinafter, referred to as a high withstand voltage transistor) and a capacitor are formed over the same semiconductor substrate.

[0002]

2. Description of the Related Art Capacitors are widely used as delay circuit elements, capacitors for storing information in DRAMs, and the like. Therefore, in an integrated circuit, it is necessary to integrate a MOS transistor and a capacitor on the same chip.

Here, the gate oxide film of a MOS transistor needs to be thick in order to ensure a withstand voltage. In particular, in a driving IC such as an LCD or an LED, a driving circuit portion operating at several tens of volts or more is formed of a high-breakdown-voltage transistor, and requires a film thickness of about 100 nm (nanometer).

On the other hand, in order to increase the capacitance value per unit area, it is desirable that the capacitance oxide film be as thin as possible. Therefore, it is necessary to form a thin oxide film and a thick oxide film on a semiconductor substrate.

The manufacturing process of a semiconductor device having such a capacitor and a MOS transistor is generally as follows. 1) Formation of a thin oxide film and a thick oxide film. 2) Cover the thin oxide film with a first photoresist. 3) First ion implantation for controlling the MOS threshold through the thick oxide film. 4) Cover the thick oxide film with a second photoresist. 5) Second ion implantation for forming the lower electrode of the capacitor through the thin oxide film.

[0006]

However, according to the above-mentioned manufacturing method, there is a problem that one mask step is required for each of the first and second ion implantations. Therefore, an object of the present invention is to reduce the number of manufacturing steps by enabling the first and second ion implantations to be performed in one mask step.

[0007]

According to a first aspect of the present invention, there is provided a first oxide film disposed on a first conductive type semiconductor substrate and the first oxide film. A method of manufacturing a semiconductor device, comprising: a thicker second oxide film; a capacitive element using the first oxide film as a capacitive oxide film; and a MOS transistor using the second oxide film as a gate oxide film. In, in different regions on the semiconductor substrate,
Forming the first oxide film and the second oxide film;
A first ion implantation step of implanting a first conductivity type impurity into the substrate by penetrating the first and second oxide films, and a second ion implantation step of penetrating only the first oxide film to form a second conductivity type impurity A second ion implantation step of implanting the first impurity into the substrate, wherein a second conductivity type impurity in which the first conductivity type impurity is compensated is provided on the substrate surface under the first oxide film. The method is characterized in that a lower electrode of the capacitive element composed of a layer is formed.

According to this means, for the second ion implantation, the second ion implantation penetrates only the first oxide film by utilizing the thickness difference between the first oxide film and the second oxide film. Since the lower electrode of the capacitor is formed by introducing the impurity of the conductivity type and compensating the impurity of the first conductivity type, the threshold control of the MOS transistor and the capacitance element can be performed in one mask process. Can be formed.

According to a second aspect of the present invention, there is provided a semiconductor device comprising: a first oxide film disposed on a first conductive type semiconductor substrate; a second oxide film thicker than the first oxide film; In a method of manufacturing a semiconductor device comprising: a capacitance element using the oxide film as a capacitance oxide film; and a MOS transistor using the second oxide film as a gate oxide film, in a different region on the semiconductor substrate, A step of forming a first oxide film and a second oxide film, and a selective oxidation method using a first polysilicon layer as a buffer film in a region between the first oxide film and the second oxide film. Forming a field oxide film and leaving the first polysilicon layer on the first oxide film and the second oxide film, and removing the first, second oxide film and the first polysilicon layer. Penetrate and inject first conductivity type impurities into the substrate A first ion implantation step, and a second ion implantation step of penetrating the first oxide film and the first polysilicon layer and implanting a second conductivity type impurity into the substrate. Forming, on the surface of the substrate under the first oxide film, a lower electrode of the capacitive element comprising an impurity layer of the second conductivity type in which the impurity of the first conductivity type is compensated, and then forming a second polysilicon layer; Is deposited on the entire surface, and the first
And forming a top electrode of the capacitive element and a gate electrode of the MOS transistor by etching the second polysilicon layer.

According to this means, in addition to the fact that the threshold value of the MOS transistor can be controlled and the lower electrode of the capacitive element can be formed in one masking step, the first mask used as a buffer film during selective oxidation can be formed. Since the polysilicon film is left as it is and is used as an upper electrode of the capacitor and a part of the gate electrode of the MOS transistor, the entire manufacturing process including selective oxidation is shortened.

According to a third aspect of the present invention, in the second aspect, a part of the upper electrode and the gate electrode extend on the field oxide film, and the extended part is a second polysilicon layer. It is characterized by being formed by.

According to this means, since the upper electrode and the gate electrode portion extending on the field oxide film are formed of a single layer of the second polysilicon layer, the step caused by the field oxide film is flattened. In addition, when forming the upper layer wiring, the processing accuracy can be improved.

[0013]

Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS.

As shown in FIG. 1A, a field oxide film (locos oxide film) 112 is formed on a P-type semiconductor substrate 111 by a selective oxidation method, and further a first oxide film (thin oxide film) 13 is formed. And second oxide film (thick oxide film) 11
4 are formed. In addition, the first polysilicon layers 115a and 115b used as the buffer films during the selective oxidation are left on the first oxide film (thin oxide film) 13 and the second oxide film (thick oxide film) 114 as they are.

Here, a field oxidation step is performed, in which a first oxide film (thin oxide film) 113 and a second oxide film (thick oxide film) are formed.
Either of the steps of the formation step 114 may be performed first.

Next, as shown in FIG. 1B, a region where the first oxide film (thin oxide film) 113 and the second oxide film (thick oxide film) 114 are formed is exposed. A photoresist layer 116 is formed.

Then, as shown in FIG. 1C, using the photoresist layer 116 as a mask, the first polysilicon layers 115a and 115b, the first oxide film (thin oxide film) 11
The first ion implantation is performed through the third and second oxide films (thick oxide film) 114. Here, when the first polysilicon layers 115a and 115b are not present, p energy is accelerated so as to penetrate the first oxide film (thin oxide film) 113 and the second oxide film (thick oxide film) 114. Type impurities are ion-implanted (first ion implantation). Thus, p-type layers 117a and 117b are formed on the surface of P-type semiconductor substrate 111. Here, the p-type layer 117b is used to control the threshold voltage of the MOS transistor.

Next, as shown in FIG. 2A, using the same photoresist layer 116 as a mask, the first polysilicon layer 115b and the first oxide film 113 are penetrated, and the second oxide film 114 is formed. With acceleration energy that does not penetrate, n
Type impurities are ion-implanted (second ion implantation). As a result, the n-type impurity is injected while being superposed on the p-type layer 117b.
17b is completely compensated and the lower electrode n
A mold layer 118 is formed.

In this way, with one mask,
It becomes possible to control the threshold value of the MOS transistor and to form the lower electrode of the capacitor.

Thereafter, as shown in FIG. 2B, a second polysilicon layer 119 is deposited and patterned to form an upper electrode 120 of the capacitor and a gate electrode 121 of the MOS transistor. . The upper electrode 120 on the first oxide film 113 and the M on the second oxide film 114
The gate electrode 121 of the OS transistor is composed of the first polysilicon layers 115a and 115b and the second polysilicon layer 1
There are nineteen laminated structures. On the other hand, the field oxide film 112
Since the portions of the upper electrode 120a and the gate electrode 121a extending upward are formed of a single layer of the second polysilicon layer 119, the step due to the presence of the field oxide film 112 is flattened, and the upper wiring is formed. When processing, the processing accuracy can be improved.

[0021]

Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to FIGS. This manufacturing method relates to a method of forming a capacitor and an N-channel high withstand voltage transistor on the same semiconductor substrate.

As shown in FIG. 3, a thick oxide film (second oxide film) 2 having a thickness of about 1000 ° is first formed on the surface of a P-type silicon substrate 1 by a thermal oxidation method. Then, a photoresist layer 3 is applied and formed on the thick gate oxide film 2, and the photoresist 3 is exposed and developed to provide an opening 3a (first opening) in the photoresist 3, and through this opening 3a,
By implanting phosphorus ions ( ³¹ P +),
An N-type layer 4a (first N-type layer) to be a low-concentration source / drain layer is formed later. The ion implantation amount at this time is
7 × 10 ¹² / cm ^2, the acceleration energy is 160 KeV.

The N-type layer 4a is formed at a predetermined distance from the surface of the silicon substrate 1 to form a source / drain layer. An opening 3b (second opening) is further formed in the photoresist 3. Opening 3b
, Phosphorus ions ( ³¹ P +) are simultaneously implanted,
An N-type layer 4b (second N-type layer) is formed.

Then, as shown in FIG. 4, using this photoresist layer 3 as it is, etching is performed by an etchant such as diluted HF to remove the thick oxide film 2 exposed in the openings 3a and 3b.

Next, as shown in FIG. 5, after removing the photoresist layer 3, the whole surface is oxidized by a thermal oxidation method to
A thin oxide film 5 having a thickness of about 0 ° is formed on the N-type layers 4a and 4b from which the thick oxide film 2 has been removed. Due to this oxidation, the thick oxide film 2 becomes even thicker.

Next, as shown in FIG. 6, a first polysilicon layer 6 and a silicon nitride film (Si 3 N 4) 7
It is formed by a CVD method. The first polysilicon layer 6 has a thickness of about 500 ° to 1000 ° and a silicon nitride film 7.
Has a thickness of about 700 ° to 1000 °. here,
The first polysilicon layer 6 is a buffer layer at the time of LOCOS oxidation, and suppresses bird's beak. The silicon nitride film 7 is an oxidation-resistant film at the time of LOCOS oxidation.

Then, the first polysilicon layer 6 / silicon nitride film 7 other than the MOS transistor formation region is removed by dry etching, and thermal oxidation (LOCOS oxidation step) is performed at a temperature of about 1000 ° C., as shown in FIG. As described above, the field oxide film (L
An OCOS oxide film 8 is formed. Here, the first polysilicon layer 6 may be used as a part of a gate electrode to be formed later and a part of an upper electrode of a capacitor without being removed. Thus, the step of removing first polysilicon layer 6 can be omitted.

FIG. 8 shows a high breakdown voltage MOS transistor.
The transistor formation area is covered with a photoresist layer 9 and
Area for forming a quantum device and a normal MOS transistor
(Not shown) and boron ion (¹¹B +) ion implantation
You. Boron ion (¹¹B +) is superimposed on the N-type layer 4b.
Injected. The ion implantation amount at this time is 1.4 × 10
¹³/ Cm^TwoAnd the acceleration energy is 160 KeV.

Next, the photoresist layer 9 is removed and 110
Thermal diffusion is performed at 0 ° C. for about 3 hours. Then, as shown in FIG. 9, N-type layer 4b is compensated by boron, and P-well region 10 is formed. N-type layer 4a
Are further deeply diffused into the N-type source layer 11 and the N-type drain layer 12 of the N-channel high breakdown voltage transistor.

Next, as shown in FIG. 10, a photoresist layer 13 is formed. The photoresist layer 13 has an opening 1
3a and 13b are formed. The opening 13a is formed on the thick oxide film 2, and the opening 13b is formed on the thin oxide film 5. Then, the opening 13a, a boron ion ⁽¹¹ B +) from 13b by ion implantation. Thus, p-type injection layers 14a and 14b are formed on the surface of P-type silicon substrate 1. The p-type injection layer 14 a is for controlling a threshold voltage, and is formed in a part of the channel region 15.

Thereafter, as shown in FIG. 11, using the same photoresist layer 13 as a mask, the acceleration energy is set so as to penetrate through the first polysilicon layer 6 and the thin oxide film 5 but not through the thick oxide film 2. An n-type impurity is ion-implanted. As a result, the n-type impurity is injected while being superimposed on the p-type injection layer 14b, and by adjusting the injection amount, the p-type layer 14b is completely compensated and the n-type layer 16 as the lower electrode is formed. Is done.

Next, as shown in FIG. 12, the photoresist layer 13 is removed, a second polysilicon layer 17 is deposited by LPCVD, and phosphorus doping is performed. Then, FIG.
As shown in (1), patterning is performed to form the upper electrode 18 of the capacitive element and the gate electrode 19 of the high voltage MOS transistor. Here, the upper electrode 18 on the thin oxide film 5 and the gate electrode 19 of the MOS transistor on the thick oxide film 2
Are the first polysilicon layer 6 and the second polysilicon layer 1
7 is obtained. On the other hand, since the portion 18a of the upper electrode extending on the field oxide film 8 is formed of a single layer of the second polysilicon layer 17, the step due to the presence of the field oxide film 8 is flattened, and the upper layer is further formed. Processing accuracy can be improved when forming wiring.

Next, by ion implantation of arsenic ions ⁽⁷⁵ As +), to form the N + -type source layer 20, N + -type drain layer 21 of the high voltage transistor.

[0034]

As described above, according to the present invention,
With one mask process, it becomes possible to control the threshold value of the MOS transistor and to form the lower electrode of the capacitor.

According to the present invention, the first polysilicon film used as the buffer film during the selective oxidation is left as it is and is used as the upper electrode of the capacitor element and a part of the gate electrode of the MOS transistor. The entire manufacturing process including oxidation is shortened.

Further, according to the present invention, since the upper electrode and the gate electrode portion extending on the field oxide film are formed of a single layer of the second polysilicon layer, the step caused by the field oxide film is reduced. Processing accuracy can be improved when flattening and forming an upper layer wiring.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 7 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 8 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating a semiconductor device according to an example of the present invention.

FIG. 10 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 11 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 12 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 13 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/8242 29/94 (72) Inventor Shinya Enomoto 3000 Chiyako, Ojiya-city, Niigata Prefecture Niigata Sanyo Electronics Co., Ltd. In-house (72) Inventor Takayasu Katagiri 3,000 Chiya Ko, Ojiya-shi, Niigata F-term (reference) in Niigata Sanyo Electronics Co., Ltd. BG12 DA09 5F083 GA28 JA02 JA32 NA02 PR05 PR36 PR38 PR47 PR48

Claims (3)

[Claims] A first oxide film disposed on a first conductive type semiconductor substrate; a second oxide film thicker than the first oxide film;
A capacitor using the first oxide film as a capacitor oxide film and an MO using the second oxide film as a gate oxide film
Forming a first oxide film and a second oxide film in different regions on the semiconductor substrate; and forming the first and second oxide films in different regions on the semiconductor substrate. A first ion implantation step of penetrating and implanting a first conductivity type impurity into the substrate; and a second ion implantation step of penetrating only the first oxide film and implanting a second conductivity type impurity into the substrate. Ion implantation step of forming a lower electrode of the capacitive element comprising a second conductivity type impurity layer in which the first conductivity type impurity is compensated on the substrate surface below the first oxide film. A method for manufacturing a semiconductor device, comprising: 2. A first oxide film disposed on a first conductivity type semiconductor substrate and a second oxide film thicker than the first oxide film.
A capacitor using the first oxide film as a capacitor oxide film and an MO using the second oxide film as a gate oxide film
Forming a first oxide film and a second oxide film in different regions on the semiconductor substrate; and forming the first oxide film and the second oxide film in different regions on the semiconductor substrate. In the region between the oxide films, the first
Forming a field oxide film by a selective oxidation method using the polysilicon layer as a buffer film and leaving the first polysilicon layer on the first oxide film and the second oxide film; A first ion implantation step of implanting a first conductivity type impurity into the substrate through the second oxide film and the first polysilicon layer; and the first oxide film and the first polysilicon layer. A second ion implantation step of implanting a second conductivity type impurity into the substrate by penetrating the first conductivity type impurity into the substrate surface under the first oxide film. Forming a lower electrode of the capacitive element comprising a compensated second conductivity type impurity layer; thereafter, depositing a second polysilicon layer over the entire surface and etching the first and second polysilicon layers. By the upper electrode of the capacitive element, Forming a gate electrode of the MOS transistor. 3. A part of the upper electrode and the gate electrode extends on the field oxide film, and the extended part is a second electrode.
3. The method of manufacturing a semiconductor device according to claim 2, wherein the semiconductor device is formed of a polysilicon layer.