KR910008978B1 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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KR910008978B1
KR910008978B1 KR1019880016531A KR880016531A KR910008978B1 KR 910008978 B1 KR910008978 B1 KR 910008978B1 KR 1019880016531 A KR1019880016531 A KR 1019880016531A KR 880016531 A KR880016531 A KR 880016531A KR 910008978 B1 KR910008978 B1 KR 910008978B1
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semiconductor device
film
nitride film
oxide film
manufacturing
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KR1019880016531A
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KR900010947A (en
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김병렬
최수한
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삼성전자 주식회사
안시환
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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Abstract

A method for mfg. a semiconductor device is characterized by forming the oxide film (22) and the nitride film (24) on the substrate (20), forming the photosensitive pattern (26) on the film (24) and etching the protruded film (24) to form the rent (28), forming the ion-inserted region (30) with the electroconductive impurity, removing the pattern (26) and forming the field oxdn. film (32) and the channel stopper region (34), re-forming the photosensitive pattern (38) and re-ion inserting, and removing the pattern (38), the nitride film (24) and the oxide film (22) in order.

Description

반도체 장치의 제조방법Manufacturing Method of Semiconductor Device

제1a-c도는 종래방법에 따른 제조공정도.1a-c is a manufacturing process diagram according to the conventional method.

제2a-e도는 본 발명에 따른 제조공정도.2a-e is a manufacturing process diagram according to the present invention.

제3도는 본 발명에 따른 또다른 실시예.3 is another embodiment according to the present invention.

본 발명은 반도체 장치의 제조방법에 관한 것으로, 특히 소자분리영역을 최소화하여 소자의 크기를 크게 줄일 수 있는 반도체 장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of greatly reducing device size by minimizing device isolation regions.

최근 반도체 메모리장치는 점점 더 고밀도화 되어가는 추세에 있고, 이와같은 고집적화 경향으로 인하여 반도체 소자와 소자간을 분리시키는 소자 분리기술(Isolation Technology)에 많은 연구 개발이 이루어지고 있다.Recently, semiconductor memory devices are becoming more and more dense, and due to such high integration trends, many research and developments have been made in isolation technology for separating semiconductor devices from devices.

종래에 주로 사용하여 왔던 상기 소자간의 소자분리 방법은 LOCOS(Local Oxidation of Silicon) 방법을 사용한 분리법이었다.The device isolation method between the devices, which has been mainly used in the past, was a separation method using a local oxide of silicon (LOCOS) method.

즉, 제1a도에 나타낸 바와같이 반도체 기판(1)상에 얇은 산화막(2)을 형성하고, 상기 산화막(2) 상부에 질화막(3)을 도포한 후 감광막(4)을 상기 질화막(3)의 상부에 도포하였다. 그후 소자간의 분리를 위한 영역을 형성하기 위해 사진식각방법으로 상기 질화막(3)의 일부를 에칭하여 창(5)을 형성한 후 상기 반도체기판(1)의 도전형과 동일도전형의 불순물을 고농도로 이온주입하여 이온주입영역(6)을 형성하였다. 그후 고온의 로에서 산화공정을 하여 제1b도에 도시한 바와같이 두꺼운 필드산화막(7)을 형성하였다. 이때 상기 필드산화막(7)의 성장은 산화마스크로 사용되는 질화막(3)이 없는 부분에서 급속히 성장하며, 동시에 상기 이온주입한 불순물도 확산되어 채널스토퍼영역(8)이 형성되었다. 그후 질화막(3)과 얇은 산화막(2)을 순차적으로 제거하면 제1c도와 같게 되었다.That is, as shown in FIG. 1A, a thin oxide film 2 is formed on the semiconductor substrate 1, the nitride film 3 is coated on the oxide film 2, and then the photosensitive film 4 is applied to the nitride film 3. It was applied to the top of the. After that, a portion of the nitride film 3 is etched to form a window 5 by a photolithography method to form a region for separation between the elements, and then a high concentration of impurities having the same conductivity type as that of the semiconductor substrate 1 is formed. Ion implantation was carried out to form the ion implantation region 6. Thereafter, an oxidation process was performed in a high temperature furnace to form a thick field oxide film 7 as shown in FIG. 1B. At this time, the field oxide film 7 grows rapidly at the portion where the nitride film 3 used as the oxide mask is absent, and at the same time, the ion implanted impurities are also diffused to form the channel stopper region 8. Subsequently, the nitride film 3 and the thin oxide film 2 were sequentially removed to be the same as that of FIG. 1C.

따라서 제1c도에 나타난 바와같이 트랜지스터 또는 캐패시터등이 형성되는 반도체 소자영역(9a)(9b)사이가 필드산화막(7)과 채널스토퍼영역(8)에 의해 분리되었다.Accordingly, as shown in FIG. 1C, the field oxide film 7 and the channel stopper region 8 are separated between the semiconductor element regions 9a and 9b in which the transistors, capacitors, and the like are formed.

그러나 상기와 같은 종래의 LOCOS방법에 의하여 필드산화막을 성장하면 장시간의 고온공정시 채널스토퍼 영역을 형성할 다량의 불순물이 상기 필드산화막으로 침투되었다.However, when the field oxide film is grown by the conventional LOCOS method as described above, a large amount of impurities penetrate into the field oxide film to form the channel stopper region during a long temperature process.

따라서 상기 채널스토퍼 영역과 필드산화막 사이의 경계면에서 불순물의 농도가 낮아지므로 반도체 소자 영역사이에 펀치드루우 현상이 발생되어 소자분리영역을 축소하기 어려운 문제점이 있었다.Therefore, since the impurity concentration is lowered at the interface between the channel stopper region and the field oxide film, a punch draw phenomenon occurs between the semiconductor device regions, thereby making it difficult to reduce the device isolation region.

또한, 반도체 소자영역 사이에 발생되는 펀치드루우 현상을 방지하게 위하여 더 많은양의 불순물을 주입할 경우 채널스토퍼 하부영역의 불순물의 농도가 매우 높아 채널스토퍼 영역과 반도체 소자영역사이의 접합 브레이크다운전압(Junction Breakdown Voltage)이 매우 낮아지게 되어 반도체 소자가 파괴되는 문제점이 있었다.In addition, when a large amount of impurities are injected to prevent the punch draw phenomenon between the semiconductor device regions, the impurity concentration in the lower region of the channel stopper is very high, and the junction breakdown voltage between the channel stopper region and the semiconductor device region is very high. (Junction Breakdown Voltage) is very low, there was a problem that the semiconductor device is broken.

따라서 본 발명의 목적은 반도체 소자 영역간의 펀치드루우 전압을 높혀 소자분리영역을 축소가능하게 함으로서 반도체 소자의 집적도를 높일수 있는 반도체 장치의 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device which can increase the degree of integration of a semiconductor device by increasing the punch draw voltage between the semiconductor device areas so that the device isolation region can be reduced.

본 발명의 또다른 목적은 반도체 소자영역과 채널스토퍼 영역사이의 접합브레이크다운 전압을 높혀 소자분리 특성이 우수한 반도체 장치의 제조방법을 제공함에 있다.Another object of the present invention is to provide a method of manufacturing a semiconductor device having excellent device isolation characteristics by increasing the junction breakdown voltage between the semiconductor device region and the channel stopper region.

상술한 목적을 달성하기 위하여 본 발명은 반도체 기판상에 산화막과 질화막을 순차적으로 형성하는 제1공정과, 상기 질화막 상부에 감광막패턴을 형성하여 노출된 질화막을 식각하여 창을 형성한 후 상기 반도체기판의 도전형과 동일한 도전형의 불순물을 이온주입하여 이온주입영역을 형성하는 제2공정과, 상기 감광막패턴을 제거한 후 필드산화막을 성장함과 동시에 채널스토퍼영역을 형성하는 제3공정과, 상기 질화막 상부에 재차 감광막패턴을 형성한 후 재차 이온주입하는 제4공정과, 상기 감광막패턴, 질화막과 산화막을 순차적으로 제거하는 제5공정으로 이루어짐을 특징으로 한다.In order to achieve the above object, the present invention provides a first step of sequentially forming an oxide film and a nitride film on a semiconductor substrate, and forming a window by forming a photosensitive film pattern on the nitride film to form a window, and then forming the window. A second step of forming an ion implantation region by ion implantation of an impurity of the same conductivity type as in the conductivity type of the semiconductor substrate, a third process of growing a field oxide film after removing the photoresist pattern, and simultaneously forming a channel stopper region, and an upper portion of the nitride film And a fourth step of ion implanting again after the photoresist pattern is formed again, and a fifth step of sequentially removing the photoresist pattern, the nitride film, and the oxide film.

이하 본 발명을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제2a-e도는 본 발명에 따른 일실시예이다. 제2a도는 p형 반도체 기판(20) 상부에 통상의 열산화방법이나 CVD 방법으로 100-1000Å정도의 산화막(22)을 형성한 후 상기 산화막(22) 상부에 LPCVD(Low Pressure CVD) 방법에 의해 1000-3000Å정도의 질화막(24)을 형성한 도면이다.Figures 2a-e is one embodiment according to the present invention. FIG. 2A shows an oxide film 22 having a thickness of about 100 to 1000 kPa formed on a p-type semiconductor substrate 20 by a conventional thermal oxidation method or a CVD method, and then a low pressure CVD (LPCVD) method on the oxide film 22. It is a figure which formed the nitride film 24 about 1000-3000 micrometers.

제2b도는 상기 질화막(24) 상부에 식각마스크로 이용될 감광막패턴(26)을 형성하고 노출된 질화막을 건식식각하여 창(28)을 형성한 후 이온주입 방법으로 보론 또는 BF2이온등 p형 불순물을 30KeV정도의 에너지로 도우즈 3.0x1013ions/cm2를 주입하여 이온주입영역(30)을 형성한 도면이다. 상기 공정에서 감광막패턴(26)이 있을때 이온주입하는 것을 보였으나 상기 감광막패턴(26)을 제거한 후 이온주입을 할 수 있음을 알아야 할 것이다.FIG. 2b is a photoresist pattern 26 to be used as an etch mask on the nitride film 24, and the exposed nitride film is dry-etched to form a window 28, followed by p-type impurities such as boron or BF 2 ions. Is implanted with a dose of 3.0x10 13 ions / cm 2 at an energy of about 30 KeV to form the ion implantation region 30. Although the ion implantation was shown when the photoresist pattern 26 is present in the process, it should be noted that ion implantation may be performed after removing the photoresist pattern 26.

제2c도는 상기 감광막패턴(26)을 제거하고 1000℃에서 3시간 정도의 고온공정에 의해 2000-10000Å정도의 필드산화막(32)를 성장시키면 이온주입영역(30)이 확산되어 채널스토퍼영역(34)를 형성한 도면이다. 이때 상기 장시간의 고온공정시 이온주입영역(30)의 보론 또는 BF2이온의 불순물이 필드산화막(32)의 내부로 침투하게 되므로 형성되는 채널스토퍼영역(34)중 필드산화막(32)과 경계를 이루는 부분의 불순물 농도가 낮아지게 된다.FIG. 2C illustrates that the ion implantation region 30 diffuses when the photoresist pattern 26 is removed and the field oxide layer 32 of about 2000-10000 kPa is grown by a high temperature process at 1000 ° C. for about 3 hours. ). At this time, the boron of the ion implantation region 30 or the BF 2 ion impurities penetrate into the field oxide layer 32 during the long time high temperature process, thereby forming a boundary with the field oxide layer 32 in the channel stopper region 34. The impurity concentration of the portion is lowered.

제2d도는 상기 질화막(24) 상부에 감광막패턴(38)을 형성한 후 재차 보론 또는 BF2이온등의 불순물을 180KeV정도의 에너지로 도우즈 3.0x1012ions/cm2를 주입한 도면이다. 상기 공정에서 감광막패턴(38)을 형성하는 것은 반도체 소자영역(36a)(36b)에 상기 불순물이 주입되는 것을 방지하기 위함이여, 이때 주입된 불순물은 필드산화막(32)과 경계를 이루는 채널스토퍼영역(34) 상부의 불순물 농도를 높힌다. 또한 상기 공정후 감광막패턴(38), 질화막(24)과 산화막(22)을 순차적으로 제거하면 제2e도와 같게된다.FIG. 2D is a view in which the doze 3.0 × 10 12 ions / cm 2 is implanted with impurities such as boron or BF 2 ions and energy of about 180 KeV again after the photoresist pattern 38 is formed on the nitride film 24. The formation of the photoresist pattern 38 in the process is to prevent the impurities from being injected into the semiconductor device regions 36a and 36b. In this case, the implanted impurities are formed in the channel stopper region bordering the field oxide layer 32. (34) Increase the impurity concentration at the top. In addition, if the photoresist pattern 38, the nitride film 24, and the oxide film 22 are sequentially removed after the process, the result is as shown in FIG. 2E.

제3도는 본 발명에 또 다른 일실시예의 일부공정을 나타낸 도면이다. 상기 제2a-c도의 공정후 제2c도의 질화막(24)을 인산조(H3PO4)등을 이용하여 제거하고, 산화막(22)과 필드산화막(32)의 전면에 보론 또는 BF2이온등의 불순물을 180KeV이상의 에너지를 이용하여 도우즈 3.0x1012ions/cm2로 이온주입을 하면 제3도와 같다. 상기 공정에서 상기 산화막(22)의 상부에 이온주입마스크가 없으므로 반도체 소자영역(36a)(36b)으로 주입된 불순물이 후의 공정에서 형성되는 반도체 소자의 하부에 위치하도록 180KeV정도의 고에너지를 이용하여 이온주입을 한다. 그 후 상기 산화막(22)을 제거하면 제2e도와 같게 된다. 지금까지 본 발명의 일실시예를 p형 반도체 기판을 사용하여 나타내었으나 N형 반도체 기판을 이용하여도 본 발명의 사상에 어긋나지 않음을 알아야 한다.3 is a view showing a part of the process of another embodiment of the present invention. After the process of FIGS. 2A-C, the nitride film 24 of FIG. 2C is removed by using a phosphate tank (H 3 PO 4 ), and the like, such as boron or BF 2 ions, on the entire surface of the oxide film 22 and the field oxide film 32. When impurities are implanted at a dose of 3.0x10 12 ions / cm 2 using energy of 180KeV or more, it is shown in FIG. 3. In the process, since there is no ion implantation mask on the oxide film 22, the high energy of about 180 KeV is used so that the impurity injected into the semiconductor device regions 36a and 36b is located below the semiconductor device formed in the subsequent process. Ion implantation. After that, the oxide film 22 is removed, which is the same as the second e. Although one embodiment of the present invention has been shown using a p-type semiconductor substrate, it should be understood that an N-type semiconductor substrate does not contradict the spirit of the present invention.

상술한 바와같이 채널스토퍼영역중 불순물 농도가 낮은 상부에 재차 이온주입을 하여 상기 채널스토퍼영역중 하부의 불순물 농도를 높이지 않고 상부의 불순물 농도를 높힐 수가 있다.As described above, ion implantation is again performed in the upper portion of the channel stopper region having a low impurity concentration, thereby increasing the impurity concentration in the upper portion without increasing the impurity concentration in the lower portion of the channel stopper region.

따라서 상술한 바와같이 본 발명을 필드산화막을 형성하기 전에 적은양의 불순물을 주입함으로써 반도체 기판과 반도체 소자영역사이의 접합브레이크다운 전압이 높아지는 잇점이 있다.Therefore, as described above, the junction breakdown voltage between the semiconductor substrate and the semiconductor element region is increased by injecting a small amount of impurities before forming the field oxide film.

또한 본 발명은 필드산화막 형성후에 재차 주입된 불순물은 저온에서 확산되므로 필드산화막과 경계를 이루는 채널스토퍼영역 상부의 불순물 농도가 높아지게 되어 상기 경계면을 통한 펀치드루우 전압이 높아지게 되며, 따라서 소자분리 간격을 줄일 수 있는 잇점이 있다.In addition, in the present invention, since the impurities implanted again after the formation of the field oxide film are diffused at a low temperature, the impurity concentration of the upper part of the channel stopper region bordering the field oxide film is increased, thereby increasing the punch draw voltage through the interface, thus increasing the device isolation interval. There is an advantage to reduce.

또한 본 발명은 재차주입된 불순물이 저온에서만 확산이 되기때문에 상기 불순물의 측면확산이 줄어들게 되어 반도체 장치의 동작특성이 좋아지는 잇점이 있다.In addition, the present invention has the advantage that the lateral diffusion of the impurity is reduced because the impurity re-injected is diffused only at a low temperature to improve the operating characteristics of the semiconductor device.

또한 본 발명은 이온주입 마스크없이 재차 불순물을 주입할때, 상기 불순물을 반도체 소자영역 하부깊이 주입되어 잡음면역 특성이 좋아지는 잇점이 있다.In addition, the present invention has the advantage that when the impurity is injected again without the ion implantation mask, the impurity is implanted deeply below the semiconductor device region to improve the noise immunity characteristics.

Claims (5)

반도체 장치의 제조공정에 있어서, 반도체 기판(20)상에 산화막(22)과 질화막(24)을 순차적으로 형성하는 제1공정과, 상기 질화막(24)상부에 감광막패턴(26)을 형성하여 노출된 질화막을 식각하여 창(28)을 형성한 후 상기 반도체 기판의 도전형과 동일한 도전형의 불순물을 이온주입하여 이온주입영역(30)을 형성하는 제2공정과, 상기 감광막패턴(26)을 제거한 후 필드산화막(32)을 성장함과 동시에 채널스토퍼영역(34)을 형성하는 제3공정과, 상기 질화막(24)상부에 재차 감광막패턴(38)을 형성한 후 재차 불순물을 이온주입하는 제4공정과, 상기 감광막패턴(38), 질화막(24)와 산화막(22)을 순차적으로 제거하는 제5공정으로 이루어짐을 특징으로 하는 반도체 장치의 제조방법.In the manufacturing process of a semiconductor device, a first step of sequentially forming an oxide film 22 and a nitride film 24 on a semiconductor substrate 20, and forming a photosensitive film pattern 26 on the nitride film 24 exposed And etching the formed nitride film to form the window 28, and then implanting impurities of the same conductivity type as those of the semiconductor substrate to form the ion implantation region 30, and the photoresist pattern 26 A third step of growing the field oxide film 32 and removing the channel stopper region 34 and removing the photoresist pattern 38 on the nitride film 24 and ion implanting impurities again. And a fifth step of sequentially removing the photosensitive film pattern (38), the nitride film (24) and the oxide film (22). 제1항에 있어서, 제2공정의 불순물 주입에너지가 10KeV-100KeV임을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the impurity implantation energy of the second process is 10 KeV-100 KeV. 제1항에 있어서, 제3공정의 필드산화막(32)의 두께가 2000-10000Å임을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the thickness of the field oxide film (32) in the third step is 2000-10000 kPa. 제1항에 있어서, 제4공정의 불순물 주입에너지가 50KeV-1MeV인 반도체 장치의 제조공정.The semiconductor device manufacturing process according to claim 1, wherein the impurity implantation energy of the fourth process is 50 KeV-1MeV. 제1항에 있어서, 제4공정이 제3공정후 질화막(24)을 제거한 후 이온주입함을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the fourth step is ion implanted after removing the nitride film (24) after the third step.
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