JPS58200554A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a dielectric, and to reduce wiring capacitance in an element isolation region by implanting a substance, which combines with silicon and forms the dielectric, in a semiconductor substrate through an ion implantation method. CONSTITUTION:An element isolation groove is formed to the P type Si substrate 1 to which an N<+> buried diffusion layer 2 and an epitaxial growth layer 3 are formed, an SiO2 film 6 is deposited, the surface of the epitaxial layer 3 is exposed through etching, oxygen is injected only into the element isolation region 4 through ion implantation while using a resist pattern 7 as a mask, and silicon oxide 8 is formed. The resist pattern 7 is removed, and an element is formed through a conventional method. Capacitance between wiring 12 and the substrate 1 can be reduced effectively by increasing the energy of ion implantation and implanting oxygen up to a deep section. Nitrogen, etc. may be used as an the substances to be implanted.

Description

[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor device.

As one of the new element isolation methods, the element isolation method with a single isolation groove width, which aims to simplify the process and flatten the step, is a method for interconnection of the element isolation region 4, as shown in Fig. 1. This has the disadvantage of increasing capacity and delay time of the circuit. As a solution to this problem, methods of thermally oxidizing the element isolation region 4 or depositing an oxide film have been proposed, but these methods have drawbacks such as complicating the process and creating steps.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the above-mentioned conventional problems and does not increase wiring capacitance in an element isolation region.

As mentioned above, the device isolation method with a constant groove width is excellent in terms of process simplification and device flattening, but on the other hand, it increases the wiring capacitance on the device isolation region and increases the circuit delay time. There was an increasing drawback.

An effective way to reduce interconnect capacitance is to form a dielectric under the interconnect, but this requires thermal oxidation of this area or accumulation of dielectric, which complicates the process. ,
Further, problems such as unevenness and disconnection of wiring occur.

The present invention provides a substance that combines with silicon to form a dielectric,
Since the dielectric is formed by injecting, for example, oxygen, nitrogen, etc. into the semiconductor substrate using ion implantation, the interconnect capacitance can be reduced without causing these problems.

Embodiments of the present invention will be described below with reference to FIGS. 1 to 5. In this example, a bipolar transistor is formed on a silicon semiconductor by a constant groove width element isolation technique, and the present invention is applied thereto.

First, a P-type Si substrate 1 on which an N0 buried diffusion layer 2 and an epitaxial surface layer 3 are formed is etched by well-known lithography using a device isolation mask with a constant groove width, and etched in a nearly vertical direction. Form an element isolation trench. (Figure 1) Next, using the well-known CVD method,
A 5iOz film 6 is deposited on the entire surface. At this time, unless the groove width is too wide, 5iOz6 is deposited almost flatly.

(Figure 2) S i Ch N! = 6 is uniformly etched to expose the surface of the epitaxial layer 3. (FIG. 3) Using the resist pattern 7 as a mask, ion implantation is performed to implant, for example, oxygen only into the element isolation region 4, and a silicon oxide 8 is formed in the region to be implanted. (FIG. 4) The resist pattern 7 is removed, and elements are then formed using a conventional method. (Fig. 5) The wiring 12 is formed passing over the silicon oxide; however, by increasing the energy of ion implantation and implanting oxygen deeply, the capacitance between the wiring 12 and the substrate 1 can be increased. can be effectively reduced. The substance to be injected is not limited to oxygen, but may also be nitrogen, for example.

As mentioned above, the additional steps to reduce the wiring capacitance on the element isolation region 4 are only the steps explained in FIG.
, and since the purpose of the phosphorography in this step is to mask the element region 5 for ion implantation, high accuracy is not required, so the step is not complicated.

As a method other than forming a dielectric, a method has been proposed in which a dielectric is deposited in the element isolation region by thermal oxidation instead of implanting ions, but the manufacturing process is The present invention is much more preferable since it is complicated and has problems such as the formation of steps.

Further, in the above embodiment, the structure of the element isolation region 4 is as follows.
Even in the case of a semiconductor device having a structure in which a trench is dug in a semiconductor substrate, oxidized, and then filled with polycrystalline silicon, the present invention can be applied, and the wiring 12 and The capacitance between the substrates 1 can be effectively reduced. (Fig. 6) In each of the above examples, the area where ions are implanted is
Since there is only an element isolation region, even if crystal defects occur due to ion implantation, element characteristics are not affected.

[Brief explanation of the drawing]

FIG. 1 to FIG. 6 are process diagrams showing an example. DESCRIPTION OF SYMBOLS 1... Si substrate, 2... Impurity buried layer, 3... Epitaxial growth layer, 4... Element isolation region, 5...
Element formation region, 6...StO, film, 7...resist film, 8...oxygen implantation layer, 9...base, lO...
Emitter, 11... Passivation film, 12...
Arrangement, 13...Dielectric material y 1 Figure 2

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device, comprising the steps of implanting ions into a desired portion of a semiconductor substrate to make the region to be implanted an insulator, and forming a wiring passing over the region to be implanted.