JP2763105B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a process of forming a groove in an element isolation region to perform element isolation.

(Prior Art) Element isolation technology in a semiconductor integrated circuit is very important in terms of integration degree and characteristics. Conventionally, in a pn junction isolation generally performed in a bipolar integrated circuit, there is a problem that an area of an isolation region is large and a parasitic capacitance is large.

On the other hand, a trench isolation (trench isolation) structure in which a groove is formed in a semiconductor substrate and a dielectric layer is embedded in the groove has recently been proposed. In this isolation structure, it is necessary to form an impurity-added layer for preventing inversion at the bottom of the groove to prevent leakage between elements and reduction in breakdown voltage. In addition, when an impurity-added layer is formed at the bottom of the groove, addition of an impurity to the side wall of the groove adversely affects the device characteristics.

4 (a) to 4 (c) show a manufacturing process of a conventional groove separation structure in consideration of such points. Using a wafer in which an n-type layer 63 is epitaxially grown on a p-type Si substrate 61 via an n ⁺ -type buried layer 62, a thermal oxidation is first performed to form a SiO ₂ film 64, on which a Si ₃ N ₄ film is formed by CVD. A film 65 is deposited. Further on this, CVD
The SiO ₂ film 66 is thickly deposited by using the above method, and an opening for forming a groove is formed in the SiO ₂ film 66 using a photoresist mask (not shown). Then, using the SiO ₂ film 66 as a mask, the underlying substrate is selectively etched by reactive ion etching to form a groove 67 ((a)). During the reactive ion etching, the polymer adheres to the inside of the groove 67, and is removed by etching with an NH ₄ F aqueous solution. Next, 25 is applied to the inner surface of the groove 67 by thermal oxidation.
A SiO ₂ film 68 having a thickness of about 0 ° is formed, and thereafter, the polycrystalline silicon film is selectively left on the side walls of the groove 67 by depositing the polycrystalline silicon film and etching the entire surface by reactive ion etching. Then, a p ⁺ -type layer 70 as an inversion prevention layer is formed at the bottom of the groove 67 by ion implantation of boron ((b)). In this ion implantation step, the Si ₃ N ₄ film 65 serves as a mask on the flat surface on the top of the groove, and the polycrystalline silicon film 69 serves as a mask on the side surface of the groove 67, and the p ⁺ type layer is selectively formed only on the bottom of the groove 67. 70 will be formed. After that, the Si ₃ N ₄ film 65 and the polycrystalline silicon film 69 are removed, and the entire surface of the substrate including the groove 67 is removed by thermal oxidation.
After covering with the O ₂ film 71, a polycrystalline silicon layer 72 is buried in the groove 67 as a dielectric layer ((c)). The surface of the buried polycrystalline silicon layer 72 is covered with a thermal oxide film to complete element isolation.

In this conventional method, in order to form the groove 67 and selectively perform ion implantation at the bottom thereof, it is necessary to form SiO ₂ on the substrate as described above.
A stacked mask of the film 64 and the Si ₃ N ₄ film 65 is required, and the SiO ₂ film 68
Is indispensable. However, when the groove 67 is formed by the reactive ion etching method, sharp corners with small curvature are formed at the top and bottom of the groove, and the Si on the side wall of the groove is formed.
In the thermal oxidation process for forming the O ₂ film 68, a large strain is concentrated on these corners due to the difference in viscosity and coefficient of thermal expansion between the SiO ₂ film and the Si ₃ N ₄ film. Since the concentration of the strain causes dislocation, it is difficult to form the SiO ₂ film 68 on the side surface of the groove 67 by thermal oxidation to a sufficient thickness of, for example, about 1000 °. Therefore, as described above, the SiO ₂ film 68 is set to about 250 °, and a polycrystalline silicon film 69 is selectively formed on the side surface.
The process is called. This complicates the process.

Instead of using the Si ₃ N ₄ film 65 in the above conventional example, it is conceivable to use a thick SiO ₂ film by CVD in this portion. In this way, stress concentration is reduced to some extent, but not enough. Since the thermal oxide film grows under the thick CVD SiO ₂ film, it also induces dislocation generation in the thermal oxidation process.

Further, in the conventional method, a polymer removal step using an NH ₄ F solution is included as a post-treatment after the formation of the groove. At this time, the SiO ₂ film is subjected to side etching, and the corner surface of the substrate is exposed.
Then, in the subsequent ion implantation step, unnecessary p
A mold inversion layer is formed, which causes an increase in leak current and a decrease in breakdown voltage of the element.

(Problems to be Solved by the Invention) As described above, in the conventional groove separation method, in the mask material forming step in the ion implantation step of forming an inversion prevention layer at the groove bottom, strain is concentrated at the groove corner and dislocation occurs. In order to suppress this, there is a problem that an impurity is unavoidably introduced into the trench side wall, resulting in an increase in leak current and a decrease in breakdown voltage of the device.

An object of the present invention is to provide a method of manufacturing a semiconductor device which solves such a problem.

[Constitution of the Invention] (Means for Solving the Problems) In the present invention, after a groove is formed by selective etching in an element isolation region of a semiconductor substrate, the entire surface of the substrate including the groove is
A film serving as a mask material is deposited under the condition that the film is thinner at the bottom of the groove and thicker at the upper portion, and impurities are selectively ion-implanted only at the bottom of the groove by utilizing the difference in film thickness of the film to form an impurity-added layer. Thereafter, the mask material is removed, and an insulating film is formed on the entire surface of the substrate by thermal oxidation or the like. A dielectric layer is buried in the trench to complete the trench isolation structure.

(Operation) In the present invention, selective ion implantation is performed at the bottom of the groove by utilizing a difference in film thickness of a single-layer mask material formed in one process for a mask effect. Such a mask material can be formed, for example, by depositing an SiO ₂ film by normal pressure CVD. When a SiO ₂ film is formed by normal pressure CVD, when the substrate flat surface is about 5000 mm, at the groove bottom with a depth of 4 to 6 μm
It is about 1000Å. By forming such a mask material, a thermal oxidation step for preventing ion implantation into the side surface of the groove is not required, and therefore, concentration of distortion at the corner is also eliminated. When the high-temperature thermal oxidation process becomes unnecessary in the element separation process,
It is possible to prevent the impurity distribution of the impurity diffusion layer such as the high-concentration buried layer that has already been formed. This enables the epitaxial layer to be thinner, which is advantageous for speeding up.
Further, a special step of forming an ion implantation resistant mask on the side surface of the groove is not required, and the step is simplified.

(Example) Hereinafter, an example of the present invention will be described.

1 (a) to 1 (d) show an element isolation step of one embodiment. A wafer is formed by epitaxially growing an n-type layer 13 serving as a collector layer on a p-type Si substrate 11 via an n ⁺ -type buried layer 12, and a thin SiO ₂ film 14 is formed on the surface by thermal oxidation ((a)). ). A thick SiO ₂ film 15 is deposited on the surface by CVD, an opening is formed in the element isolation region by forming and etching a photoresist mask, and the underlying substrate is exposed,
An element isolation groove 16 having a depth of about 4 μm and a width of about 1.4 μm reaching the p-type Si substrate 11 is formed by reactive ion etching ((b)). CVDS used as mask material after formation of groove 16
The iO ₂ film 15 and the thermal oxide film 14 are removed by etching with an NH ₄ F aqueous solution, and at the same time, the polymer adhered in the groove 16 is also removed with this aqueous solution. Then, a substrate temperature of 400 ° C is applied over the entire exposed substrate.
Then, an SiO ₂ film 17 is deposited by normal pressure CVD ((c)). Assuming that the thickness of the SiO ₂ film 17 obtained at this time on the flat surface above the groove of the substrate is d ₁ = 5000 °, d ₂ =
5,000Å, d ₃ = 2000 下部 at the bottom, d ₄ = at the bottom
It is about 1000Å. Note that a thin thermal oxide film may be formed over the entire surface of the substrate under the normal pressure CDV-SiO ₂ film. Next, this SiO ₂
Boron is selectively ion-implanted into the bottom of the groove 16 by utilizing the thickness difference of the film 17 to form the p ⁺ -type layer 18. For example, dose
Only at the bottom of groove 16 under conditions of 10 ¹⁴ / cm ² and acceleration voltage of 40 keV
The p ⁺ type layer 18 can be formed. Thereafter, the SiO ₂ film 17 is removed, and a SiO ₂ film 19 is formed on the entire surface again by thermal oxidation. Then, the polycrystalline silicon layer 10 is embedded in the trench ((d)). The polycrystalline silicon layer is used as the buried dielectric because using the same material as the substrate is effective in preventing the occurrence of unnecessary distortion due to the difference in thermal expansion coefficient.

Thereafter, although not shown, an SiO ₂ film is formed on the surface of the polycrystalline silicon layer 10 inside the trench, and the insulation separation is completed. In each element region separated by the groove, a transistor having the n-type layer 13 as a collector is formed according to a normal process, and a bipolar integrated circuit is obtained.

According to this embodiment, the mask for ion implantation at the time of ion implantation at the bottom of the groove is a single layer of normal pressure CVD-SiO ₂ film, and the strain is not concentrated on the corner of the groove unlike the conventional method.
Therefore, the generation of dislocations is suppressed, and there is no unnecessary introduction of impurities into the trench side walls. Further, as a result of the reduction in the number of heat steps, re-diffusion of impurities in the buried diffusion layer is prevented, and for example, a thinner epitaxial layer which is advantageous in increasing the speed in a bipolar integrated circuit can be realized. As a result, a high-performance semiconductor integrated circuit having excellent characteristics such as high-frequency characteristics and junction characteristics can be obtained. Further, the element isolation process is simpler than the conventional method.

In the above-described embodiment, normal pressure CVD is used as a film forming method to make the film thinner at the bottom of the groove. However, another method that produces the same film thickness difference in one process can be used. For example,
By flowing a silane gas and oxygen to deposit an SiO ₂ film by CVD, a film that becomes thinner at the groove bottom can be formed. Specifically, for example, a desired film can be obtained even when a SiO ₂ film is deposited by low-pressure CVD at a substrate temperature of 400 ° C. and a pressure of 0.1 torr. Further, a film that becomes thinner at the groove bottom can also be formed by sputtering. For example, substrate temperature 200
Temperature, pressure 3 × 10 ^-1 pa, power 6kW, SiO ₂ film or Al
By depositing the film by sputtering, a film that becomes thinner at the groove bottom can be obtained.

2 (a) to 2 (f) are cross-sectional views showing manufacturing steps of another embodiment of the present invention. In this embodiment, an allowance for preventing the occurrence of dislocation due to the corner of the element isolation groove is further taken into consideration in the previous embodiment. First, second
As shown in FIG. 2A, an n ⁺ -type buried layer is formed on a p-type Si substrate 21.
An n-type epitaxial layer 23 serving as a collector layer is formed via 22. Subsequently, the surface is oxidized to form a SiO ₂ film 24, and a Si ₃ N ₄ film 25 is further formed thereon by a CVD method. Hereinafter, the substrate 21, the n ⁺ -type buried layer 22, and the n-type epitaxial layer 23 will be referred to as a base substrate 20. Thereafter, after patterning the Si ₃ N ₄ film 25, an SiO ₂ film 26 is deposited on the entire surface by a CVD method as shown in FIG. 2 (b). Subsequently, the SiO ₂ films 26 and 24 are partially opened to expose the surface of the base substrate 20. After that, using the remaining CVD-SiO ₂ film 26 as a mask, the underlying substrate 20 is etched by RIE through the opening to form an element isolation groove 27. The depth of this groove 27 is n ⁺
This depth is sufficient to penetrate the mold burying layer 22 and reach the substrate 21. At the bottom of the groove 27, boron is ion-implanted for the purpose of preventing inversion. In this state, the groove formed in the base substrate 20 is
The top corner portion 28a and the bottom corner portion 28b of 27 are steep.

Next, the CVD-SiO ₂ film 26 of the mask material and the SiO ₂ film 24 thereunder
Was removed by etching with NH ₄ F aqueous solution, and patterned Si
₃ N ₄ to expose the surface of the film 25 and the underlying substrate 20.

Next, as shown in FIG. 2 (c), a polycrystalline silicon film 29 as a first film is formed on the entire surface of the base substrate 20 including the groove 27.
Is deposited by a CVD method. The polycrystalline silicon film 29 formed by this CVD method has a portion 29a of the upper corner 28a of the groove 27.
Is thinner, and the portion 29b of the lower corner 28b of the groove 27 becomes thicker. Therefore, the trench 27 covered with the polycrystalline silicon film 29
Has a round shape at four corners.

Next, as shown in FIG. 2 (d), the polycrystalline silicon film 29 is etched and removed by an isotropic etching method such as a CDE method to expose the surfaces of the base substrate 20 and the grooves 27. At this time, in the upper corner portion 28a of the groove 27, the substrate etching is started early because the thickness of the polycrystalline silicon film 29 is small. Thereby, the upper corner portion 30a of the element isolation groove 27 can be rounded. On the other hand, since the polycrystalline silicon film 29b at the bottom corner 28b of the groove 27 is thick, substrate etching is started with a delay. This allows the bottom corner
30b can be rounded. Even if the polycrystalline silicon film 29 is etched to leave a part of the polycrystalline silicon film 29 at the bottom corner portion 30b, a similar rounded shape can be obtained.

Next, as shown in FIG. 2 (e), an SiO ₂ film 32 is deposited on the entire exposed substrate by a normal pressure CVD method. As a result, a mask material thick at the top of the groove 27 and thin at the bottom is obtained.
Then, utilizing the difference in the thickness of the SiO ₂ film 32, boron is selectively ion-implanted into the bottom of the groove 27 to form the p ⁺ -type layer 34. Thereafter, the SiO ₂ film 32 is removed while leaving the polycrystalline silicon film at the bottom corners 30a and 30b of the groove 27.

Then, as shown in FIG. 2 (f), the second coating SiO 2 is formed on the entire surface of the base substrate 20 including the groove 27 by a thermal oxidation method using the Si ₃ N ₄ film 25 as an oxidation resistant mask. _Two films 36 are formed. At this time, the corner portion 30 of the groove 27
Since both a and 30b are rounded, the oxide film thickness at this portion becomes equal to that at the substrate surface, the groove side surface and the groove bottom surface. Therefore, the distortion at the corner of the groove can be reduced, and the occurrence of dislocation can be prevented. Further, this oxidation can be performed at a temperature of 965 ° C. or less.

Next, a polycrystalline silicon film 38 is deposited on the surface of the substrate including the groove 27, and after the polycrystalline silicon film 38 is completely buried in the groove 27, the polycrystalline silicon film 38 in the flat portion is removed by etch-back and left only in the groove portion. . Thereafter, an SiO ₂ film (not shown) of about 500 ° is formed on the surface of the polycrystalline silicon film 38 in the groove portion by a thermal oxidation method, and then the Si ₃ N ₄ film 25 and the underlying SiO ₂ film 2 are formed.
4 is removed by etching to complete the isolation.

Thus, according to this embodiment, the corner portions of the element isolation trenches 27 can be effectively rounded by the formation and etching steps of the polycrystalline silicon film 29, thereby distorting the corner portions concentrated in the subsequent heat treatment step. Can be alleviated. Therefore, the thermal oxide film (SiO ₂ film 36) in the trench isolation can be formed at a low temperature, and the occurrence of dislocations and the dripping of impurities in the buried layer can be prevented. This effect leads to improvement in high frequency characteristics and junction characteristics in a bipolar semiconductor device or the like.

The present invention is not limited to the embodiments described above. For example, the first
The film of the film is not limited to the polycrystalline silicon film, but any film can be formed uniformly on the side surface of the groove and the etching rate is equal to or slower than that of the substrate. obtain. The first coating having a thickness of about several hundreds of mm is sufficiently effective in rounding the groove corner. Further, since the groove corner is sufficiently rounded, the thickness of the SiO ₂ film formed by the thermal oxidation method using the Si ₃ N ₄ film as a mask can be selected from a wide range from several tens of degrees to about 1 μm. Therefore, the present invention is also applicable to the manufacture of trench capacitors for DRAM. Instead of the SiO ₂ film by the thermal oxidation method, it is also possible to use a CVD0SiO ₂ film that can be formed at a low temperature.

In the embodiment, the case where a sharp corner portion is formed at the bottom of the groove is described as an example.However, even when the bottom of the groove is already rounded during Si etching, the corner portion at the top of the groove is also described. The present invention is effective if attention is paid to.

In the above embodiments, the element isolation of the bipolar integrated circuit has been described. However, the present invention can be applied to a MOS integrated circuit.

FIG. 3 is a final sectional view in an embodiment in which the present invention is applied to a MOS type trench transistor. If this is simply explained according to the manufacturing process, an n ⁺ -type layer is formed on the p-type Si substrate 51.
After forming a mask material 52 and depositing a mask material, a groove 56 is formed by photolithography and etching, and the mask material is removed. Next, an SiO ₂ film is formed thick at the substrate surface and the groove side surface and thin at the groove bottom, for example, by normal pressure CVD, and ion implantation is performed using the SiO ₂ film as a mask to form an n ⁺ type layer 55. This SiO ₂ film is removed. Next, an SiO ₂ film 54 serving as a gate insulating film is formed by thermal oxidation, and an n ⁺ type polycrystalline silicon film is formed.
Deposit 54 to complete the transistor.

By combining this transistor with a trench capacitor, a micro-sized dRAM can be obtained.

Although the embodiments of the present invention have been described above, the present invention can be variously modified and implemented without departing from the spirit thereof.

[Effects of the Invention] As described above, according to the present invention, it is possible to suppress the concentration of strain in the groove separation step and the diffusion of impurities to the groove side surfaces, and to provide a semiconductor device having a groove separation structure having excellent characteristics in a simple step. Obtainable.

[Brief description of the drawings]

1 (a) to 1 (d) are views for explaining an element isolation step of one embodiment of the present invention, and FIGS. 2 (a) to 2 (f) are illustrations of an element isolation step of another embodiment. FIG. 3 is a diagram for explaining still another embodiment, and FIGS.
(C) is a diagram for explaining a conventional element isolation step. 11 ...... p-type Si substrate, 12 ...... n ⁺ -type buried layer, 13 ...... n-type layer, 14 ...... SiO ₂ film (thermal oxidation), 15 ...... SiO ₂ film (CVD), 1
6 ... groove, 17 ... SiO ₂ film (normal pressure CVD), 18 ... p ⁺ type layer, 19
…… SiO ₂ film (thermal oxidation), 10… Polycrystalline silicon film, 21…
... p-type Si substrate, 22 ... n ⁺ type layer, 23 ... n-type layer, 24 ... Si
O ₂ film (thermal oxidation), 25 ... Si ₃ N ₄ film, 26… SiO ₂ film (CV
D), 27 ... groove, 28a, 28b ... corner, 29 ... polycrystalline silicon film, 32 ... SiO ₂ film (CVD), 34 ... p ⁺ type layer, 36 ...
... SiO ₂ film (thermal oxidation), 38 ... Polycrystalline silicon film.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-59-124141 (JP, A) JP-A-60-18930 (JP, A) JP-A-63-111643 (JP, A) (58) Field (Int.Cl. ⁶ , DB name) H01L 21/76-21/765

Claims (3)

(57) [Claims] 1. A step of depositing a deposited film of SiO ₂ on a semiconductor substrate having a groove formed in an element isolation region so as to be thick at the top of the groove and thin at the bottom of the groove by normal pressure, low pressure CVD or sputtering. Selectively forming an impurity-added layer on the substrate surface at the bottom of the groove by ion-implanting an impurity and utilizing the thickness difference of the deposited film; and forming an element isolation structure by filling the groove. And a method for manufacturing a semiconductor device. 2. A step of depositing a deposition film made of Al on a semiconductor substrate having a groove formed in an element isolation region so as to be thick at the top of the groove and thin at the bottom of the groove by a sputtering method, and by ion-implanting impurities. Selectively forming an impurity-added layer on the substrate surface at the bottom of the groove by utilizing a thickness difference of the deposited film;
Forming a device isolation structure by filling the trench after removing the deposited film. 3. A step of forming a film on the substrate surface so as to be thinner at an upper corner of the groove and thicker at a lower corner thereof before the step of depositing the deposited film, and etching all or a part of the film. 3. The method for manufacturing a semiconductor device according to claim 1, further comprising: exposing a surface of said substrate by removing.