JPH05283520A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a high speed bipolar LSI by preventing a channel stopper from expanding beyond the bottom face of a trench in trench isolation (isolation by filling trenches) and by reducing the parasitic capacitance. CONSTITUTION:An n-type buried layer 2a, n-type epitaxial layer 3, silicon oxide film 4 and silicon nitride film 5 are formed on a p-type silicon substrate 1 in this order. A trench is formed such that it reaches the p-type silicon substrate 1. A normal pressure CVD silicon oxide film 6 is formed, and then ion implantation is performed to form a p-type channel stopper 7. The normal pressure CVD silicon oxide film 6 and the silicon oxide film 4a on the surface are etched, and thermal oxidation is performed to form a silicon oxide film 4b. Polysilicon 8 is deposited, which is then flattened by etching back. Thermal oxidation is performed to form a silicon oxide film 9 on the surface, and the silicon nitride film 5 is removed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming trench isolation (groove filling isolation).

[0002]

2. Description of the Related Art A conventional trench isolation will be described with reference to FIGS. 3 (a) and 3 (b).

First, as shown in FIG. 3 (a), an N type buried layer 2a is formed on a P type silicon substrate 1, and then an N type epitaxial layer 3 is grown. Next, the silicon oxide film 4,
A silicon nitride film 5 and a silicon oxide film 4c are sequentially formed. Next, using the photoresist (not shown) as a mask, the silicon oxide film 4c, the silicon nitride film 5, and the silicon oxide film 4 are etched. Next, after removing the photoresist, silicon is etched using the silicon oxide film 4c as a mask to form a trench reaching the P-type silicon substrate 1. Next, a silicon oxide film 4a is formed on the groove surface by thermal oxidation.

Next, as shown in FIG. 3B, boron ions are implanted using the silicon oxide film 4c as a mask to form a P-type channel stopper 7.

[0005]

In the conventional ton wrench isolation, it is unavoidable that boron is spread not only to the bottom surface of the groove but also to the side surface thereof. A PN junction is formed on the side surface of the groove to increase the collector-substrate capacitance, which deteriorates the performance of the bipolar transistor.

If the side surface of the groove is vertically raised, boron does not spread on the side surface, but it becomes difficult to fill the polysilicon in a later step, and "porosity" (cavity) easily occurs.

Further, when a diffusion layer having the same conductivity type as the channel stopper is formed in the vicinity of the groove, there is a problem in that the diffusion layer is electrically connected to the substrate unless a certain distance is provided from the groove.

[0008]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a groove on one main surface of a semiconductor substrate, and a step of forming a groove on the bottom surface of the groove by atmospheric pressure CVD to form another area on the other surface. Includes a step of depositing an insulating film so as to be thick, and a step of forming an impurity layer just below the bottom surface of the groove by ion implantation using the insulating film as a mask.

[0009]

EXAMPLE FIG. 1A shows a first example of the present invention.
This will be described with reference to (b) and.

First, as shown in FIG. 1 (a), an N type buried layer 2a having a depth of 2 to 3 μm is formed on a P type silicon substrate 1, and then an N type epitaxial layer having a thickness of 0.8 to 1.5 μm. Grow three. Next, a silicon oxide film 4 having a thickness of 30 to 60 nm, a silicon nitride film 5 having a thickness of 50 to 150 nm,
A silicon oxide film (not shown) having a thickness of 300 to 500 nm is sequentially formed. Next, using the photoresist (not shown) as a mask, the silicon oxide film (not shown), the silicon nitride film 5, and the silicon oxide film 4 are etched.
At this time, the width of the opening is 1.2 μm. Next, after removing the photoresist, silicon is etched using a silicon oxide film (not shown) on the surface as a mask to form a trench reaching the P-type silicon substrate 1. Next, after removing the silicon oxide film (not shown) on the surface, a silicon oxide film 4a is formed on the groove surface by thermal oxidation.

Next, the silicon oxide film 6 is formed by the atmospheric pressure CVD (chemical vapor deposition) method. Since the mean free path of the molecule is small under normal pressure, the film thickness growing on the side surface and the bottom surface becomes smaller as the groove becomes deeper. Therefore, the growth temperature,
By selecting the gas flow rate and the opening width and depth of the groove, the silicon oxide film grown on the bottom surface of the groove and its vicinity can be made sufficiently thin.

Next, using the atmospheric pressure CVD silicon oxide film 6 as a mask, boron is ion-implanted at an acceleration energy of 50 to 70 keV and an implantation dose (dose) of 5 × 10 ¹³ to 2 × 10 ¹⁴ cm ^-2 to form a P-type channel stopper 7. Form.

Next, as shown in FIG. 1B, the atmospheric pressure CVD silicon oxide film 6 and the silicon oxide film 4a on the surface of the groove are wet-etched using hydrofluoric acid. Next, thermal oxidation is performed using the silicon nitride film 5 as a mask to form a silicon oxide film 4b having a thickness of 100 to 200 nm only inside the groove. Next, a polysilicon 8 having a thickness of 1.5 to 2.0 μm is deposited and then etched back by RIE (reactive ion etching) to leave only the polysilicon 8 embedded inside the groove.

Next, thermal oxidation is performed using the silicon nitride film 5 as a mask to form a silicon oxide film 9 having a thickness of 100 to 200 nm on the surface of the embedded polysilicon 8. Finally, the silicon nitride film 5 is removed to complete the trench isolation.

Next, as a second embodiment of the present invention, a semiconductor integrated circuit in which bipolar transistors and MOSFETs are mixed will be described with reference to FIG.

After forming the N type buried layer 2a and the P type buried layer 2b on the P type silicon substrate 1, an N type epitaxial layer (not shown) is grown. Next, the N well 3a is formed in the epitaxial layer on the N type buried layer 2a, and the P type buried layer 2 is formed.
A P well 3b is formed in the epitaxial layer above b.
Next, a groove is formed in the contact portion between the N well 3a and the P well 3b. After that, in the same manner as in the first embodiment, the P-type channel stopper 7 is formed only on the bottom surface of the groove, the gate electrode 10 is formed on the silicon oxide film 4 serving as the gate oxide film, and then the P-type source. The drain 11 is formed.

In this embodiment, even if the P-type source / drain 11 collides with the groove, the P-type silicon substrate 1 is not electrically connected. P
Margin between the source / drain 11 and the groove
Since it is not necessary to provide the device, the size of the MOSFET can be reduced.

[0018]

Since impurities are not introduced into the side surface of the groove,
No PN junction is formed on the side surface of the groove. Therefore, the collector-collector capacitance and the collector-substrate capacitance, which slow down the operation speed of the bipolar LSI, can be significantly reduced.

Basic transistor size 7 μm × 5 μm,
When the thickness of the N-type epitaxial layer is 1.0 μm, the thickness of the N-type buried layer is 2.0 μm, the depth of the groove is 5.0 μm, and the specific resistance of the P-type silicon substrate is 10Ω, it is about 20 fF.
However, in the present invention, it is reduced to half. The frequency of the ring oscillator is improved by about 10%.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in process order.

FIG. 2 is a sectional view showing a second embodiment of the present invention.

FIG. 3 is a sectional view showing a conventional method for forming trench isolation.

[Explanation of symbols]

 1 P-type silicon substrate 2a N-type buried layer 2b P-type buried layer 3 N-type epitaxial layer 3a N well 3b P well 4, 4a, 4b, 4c Silicon oxide film 5 Silicon nitride film 6 Normal pressure CVD silicon oxide film 7 P-type channel stopper 8 Polysilicon 9 Silicon oxide film 10 Gate electrode 11 P-type source / drain

Claims (3)

[Claims] 1. A step of forming a groove on one main surface of a semiconductor substrate, a step of depositing an insulating film by a normal pressure CVD method so that the bottom surface of the groove is thin and other areas are thick. And a step of forming an impurity layer just below the bottom surface of the groove by ion implantation using the insulating film as a mask. 2. A step of forming an N-type buried layer on one main surface of a P-type silicon substrate and then growing an N-type epitaxial layer, and penetrating the N-type epitaxial layer and the N-type buried layer. To form a groove reaching the P-type silicon substrate, a step of depositing an insulating film by a normal pressure CVD method so that the bottom surface of the groove is thin and other areas are thick, and the insulating film is used as a mask. A step of forming an impurity layer just below the bottom surface of the groove by ion implantation. 3. A P-type silicon substrate is provided with N on a part of its main surface.
A step of growing an N type epitaxial layer after forming the type buried layer and the P type buried layer, and forming an N well in the N type epitaxial layer on the N type buried layer, Forming a P-well in the N-type epitaxial layer on the buried layer, forming a groove reaching the P-type silicon substrate in an isolation region between the N-well and the P-well, and using an atmospheric pressure CVD method. A step of depositing an insulating film so that it is thin on the bottom surface of the groove and thick in other regions, and a step of forming an impurity layer just below the bottom surface of the groove by ion implantation using the insulating film as a mask. A method of manufacturing a semiconductor device including.