KR20010004674A - Manufacturing method for semiconductor device - Google Patents

Manufacturing method for semiconductor device Download PDF

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KR20010004674A
KR20010004674A KR1019990025377A KR19990025377A KR20010004674A KR 20010004674 A KR20010004674 A KR 20010004674A KR 1019990025377 A KR1019990025377 A KR 1019990025377A KR 19990025377 A KR19990025377 A KR 19990025377A KR 20010004674 A KR20010004674 A KR 20010004674A
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South Korea
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device isolation
trench
film
field stop
region
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KR1019990025377A
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Korean (ko)
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최형석
이병렬
이승철
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김영환
현대전자산업 주식회사
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Priority to KR1019990025377A priority Critical patent/KR20010004674A/en
Publication of KR20010004674A publication Critical patent/KR20010004674A/en

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    • E—FIXED CONSTRUCTIONS
    • E04—BUILDING
    • E04H—BUILDINGS OR LIKE STRUCTURES FOR PARTICULAR PURPOSES; SWIMMING OR SPLASH BATHS OR POOLS; MASTS; FENCING; TENTS OR CANOPIES, IN GENERAL
    • E04H9/00—Buildings, groups of buildings or shelters adapted to withstand or provide protection against abnormal external influences, e.g. war-like action, earthquake or extreme climate
    • E04H9/02—Buildings, groups of buildings or shelters adapted to withstand or provide protection against abnormal external influences, e.g. war-like action, earthquake or extreme climate withstanding earthquake or sinking of ground
    • E04H9/028—Earthquake withstanding shelters
    • E04H9/029—Earthquake withstanding shelters arranged inside of buildings

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Abstract

PURPOSE: A semiconductor device manufacturing method is provided to be capable of prohibiting degradation of the characteristic due to diffusion of impurity during a subsequent annealing process, by forming a field stop implant region only in a device region. CONSTITUTION: A semiconductor device manufacturing method includes the following steps. A pad insulating film(13) laminating an active region on a semiconductor substrate(11) is first patterned. The semiconductor substrate is then etched using the pad insulating film as a mask, thus forming a trench. Next, the first device separation film(21) filling the trench to a given depth is formed. A field stop implant region(23) is formed only in the device region using the pad insulating film and the first device separation film as an etch barrier. The second device separation film filling the trench is formed, and the first and second device separation films are thermal-treated so that they can be made dense.

Description

반도체소자의 제조방법{Manufacturing method for semiconductor device}Manufacturing method for semiconductor device

본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 필드스톱임플란트를 형성하는데 있어서 패드절연막을 트렌치 형성공정후 일정두께 매립하는 제1소자분리막을 형성하고 필드스톱임플란트공정을 실시함으로써 트렌치 저부에만 필드스톱임플란트영역을 형성할 수 있도록 하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, in forming a field stop implant, a field stop implant is formed by forming a first device isolation film that fills a pad thickness after a trench forming process and performing a field stop implant process. The present invention relates to a technique for forming an implant region.

일반적으로, 소자분리기술이란 집적소자를 구성하는 개별소자를 전기적 및 구조적으로 서로 분리시켜, 각 소자가 인접한 소자의 간섭을 받지 않고 독자적으로 그 주어진 기능을 수행할 수 있도록 하는데 필요한 기능을 집적 소자 제조시 부여하는 기술이다.In general, device isolation technology is an integrated device fabrication that is necessary to separate the individual devices constituting the integrated device from each other electrically and structurally, so that each device can perform its own function independently without interference from adjacent devices. It is a skill given to the city.

고집적화 또는 고밀도라는 관점에서 소자의 집적도를 높이기 위해서는 개개의 소자의 디맨젼을 축소하는 것도 필요한 동시에 소자와 소자 사이에 존재하는 소자분리영역의 폭 및 면적을 축소하는 것도 필요하다.In order to increase the integration of devices in terms of high integration or high density, it is necessary to reduce the dimensions of individual devices, and at the same time, it is necessary to reduce the width and area of the device isolation region existing between the devices.

그리고, 상기 소자분리영역으로 인하여 소자의 특성이 열화되거나 형성공정에 장애를 주어서도 안된다.In addition, the device isolation region does not deteriorate device characteristics or impede the formation process.

종래기술에 따른 반도체소자의 제조방법은, 웰을 형성하기 위한 웰 임플란트 공정을 실시하여 웰을 형성하고 반도체기판 상부에 활성영역을 도포하고 비활성영역인 소자분리영역을 노출시키는 패드절연막을 형성한 다음, 이를 마스크로하여 상기 반도체기판에 필드스톱임플란트를 실시함으로써 필드스톱임플란트영역을 형성한다.In the method of manufacturing a semiconductor device according to the related art, a well implant process for forming a well is performed to form a well, a pad insulating film is formed on the semiconductor substrate, and an active region is coated on the semiconductor substrate, and a device isolation region is exposed. By using this as a mask, a field stop implant is formed on the semiconductor substrate to form a field stop implant region.

그리고, 상기 소자분리영역을 필드산화시켜 필드산화막을 형성하고 후속공정으로 상기 패드절연막을 제거하고 평탄화식각함으로써 소자분리막을 형성한다.In addition, the device isolation region is field oxidized to form a field oxide film, and in a subsequent process, the pad insulation layer is removed and planarized to form a device isolation film.

후속공정으로 딥 임플란트 ( deep implant ) 와 문턱전압 임플란트를 진행하여 웰을 형성한다.In a subsequent process, a deep implant and a threshold voltage implant are performed to form a well.

상기한 바와같이 필드스톱임플란트 공정에서 이온주입을 웰 지역의 활성영역과 소자분리영역에 마스크없이 실시하게 되는데 후속 공정변수에 따라 Rp 점이 변화하게 되어 소자분리막 하부에 정확하게 형성되지 못하는 문제점을 발생시킬 수 있다.As described above, ion implantation is performed in the field stop implant process without a mask in the active region and the device isolation region of the well region, and the Rp point is changed according to the subsequent process variables, which may cause a problem that cannot be formed accurately under the device isolation layer. have.

특히 소자분리 펀치쓰루우 ( ISO punchthrow ) 가 중요해지는 소자분리산화막 ( ISO ) 간의 간격이 0.20 ㎛ 이하급 소집적소자에서는 정확한 필드스톱임플란트영역을 조절하는 것이 중요하게 된다.In particular, it is important to precisely adjust the field stop implant area in small-integrated devices having an interval of 0.20 µm or less, in which device isolation oxide (ISO), in which device isolation punch-through is important, is important.

한편, 활성영역의 높은 도펀트 농도는 접합누설전류를 크게 하는 이유가 된다. 특히 필드스톱임플란트영역을 형성하는 도펀트의 임플란트 Rp 점이 접합 형성시 반도체기판 쪽의 공핍층 ( depletion ) 폭안에 형성되는 경우 접합누설전류 특성을 크게 열화시킬 수 있다.On the other hand, the high dopant concentration in the active region is the reason for increasing the junction leakage current. In particular, when the implant Rp point of the dopant forming the field stop implant region is formed within the depletion width of the semiconductor substrate side when forming the junction, the junction leakage current property may be greatly deteriorated.

상기한 바와같이 종래기술과 같은 반도체소자의 제조방법은, 예정된 농도로 예정된 위치, 즉 소자분리영역 하측에 필드스톱임플란트영역을 형성하는데 있어서, 상기 필드스톱임플란트영역의 도펀트 농도가 활성영역에도 비슷한 농도로 형성되어 소자의 특성을 열화시키고 그에 따른 소자의 오동작을 유발시키는 문제점이 있다.As described above, in the method of manufacturing a semiconductor device as in the prior art, in forming a field stop implant region at a predetermined position, i.e., under a device isolation region, at a predetermined concentration, the dopant concentration of the field stop implant region is similar to the active region. Formed to deteriorate the characteristics of the device and thereby cause malfunction of the device.

한편, 소자분리막을 트렌치형으로 형성하는 경우는, 패드절연막을 마스크로하여 반도체기판을 식각하여 트렌치를 형성한다는 차이점이 있을뿐 같은 문제점이 유발된다.On the other hand, when the device isolation film is formed in a trench type, there is a difference in that the trench is formed by etching the semiconductor substrate using the pad insulating film as a mask, which causes the same problem.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 패드절연막 및 트렌치가 형성된 반도체기판에 소자분리막을 일정두께 형성하고 상기 패드절연막을 마스크로하여 상기 소자분리막인 형성되는 트렌치 하부에 불순물을 임플란트함으로써 소자분리영역 하부에만 필드스톱임플란트영역을 형성할 수 있도록 하여 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, a device isolation film is formed to a predetermined thickness on a semiconductor substrate on which a pad insulating film and a trench are formed, and an impurity is implanted in a lower portion of the trench formed as the device isolation film by using the pad insulating film as a mask. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of forming a field stop implant region only under the device isolation region, thereby improving the characteristics and reliability of the semiconductor device.

도 1a 및 도 1b 는 본 발명의 실시예에 따른 반도체소자의 제조방법을 도시한 단면도.1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 2 는 본 발명과 종래기술에 따른 접합 누설전류 곡선을 도시한 그래??프도.Figure 2 is a graph showing a junction leakage current curve according to the present invention and the prior art.

〈 도면의 주요부분에 대한 부호의 설명 〉<Description of reference numerals for the main parts of the drawings>

11 : 반도체기판 13 : 패드산화막11 semiconductor substrate 13 pad oxide film

15 : 패드질화막 17 : 트렌치15 pad nitride film 17 trench

19 : 희생산화막 21 : 제1소자분리막19: sacrificial oxide film 21: the first device isolation film

23 : 필드스톱임플란트영역 ( field stop implant regoin )23: field stop implant regoin

이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 제조방법은,In order to achieve the above object, a semiconductor device manufacturing method according to the present invention,

반도체기판 상의 활성영역을 도포하는 패드절연막을 패터닝하는 공정과,Patterning a pad insulating film for applying an active region on the semiconductor substrate;

상기 패드절연막을 마스크로하여 상기 반도체기판을 식각해 트렌치를 형성하는 공정과,Forming a trench by etching the semiconductor substrate using the pad insulating layer as a mask;

상기 트렌치를 일정깊이 매립하는 제1소자분리막을 형성하는 공정과,Forming a first device isolation film to fill the trench with a predetermined depth;

상기 패드절연막과 제1소자분리막을 식각장벽으로 하여 상기 트렌치 하부에만 필드스톱임플란트하여 필드스톱임플란트영역을 형성하는 공정과,Forming a field stop implant region by using the pad insulating layer and the first device isolation layer as an etch barrier to field stop implants only in the lower portion of the trench;

상기 트렌치를 매립하는 제2소자분리막을 형성하고 상기 제1,2소자분리막을 열처리하여 치밀화시키는 공정을 포함하는 것을 특징으로한다.And forming a second device isolation film to fill the trench, and densifying the first and second device isolation films by heat treatment.

한편, 이상의 목적을 달성하기 위한 본 발명의 원리는 다음과 같다.On the other hand, the principle of the present invention for achieving the above object is as follows.

웰 형성공정에서의 필드스톱임플란트를 따로 분리하여 얕은 트렌치를 형성하고 이를 매립하는 제1소자분리막을 일정두께 형성한 다음, 상기 트렌치의 하부에만 국부적으로 불순물을 임플란트하여 필드스톱임플란트영역을 확실하고 용이하게 형성할 수 있도록 하며 접합의 기판 쪽 공핍영역 농도를 낮추어 도펀트에 의한 결함 발생을 감소시켜 접합누설전류를 감소시킬 수 있도록 하는 것이다.In the well forming process, the field stop implants are separated separately to form shallow trenches, and the first device isolation layer filling the trenches is formed to have a predetermined thickness, and then impurities are locally implanted only in the lower portion of the trenches to reliably and easily form the field stop implant regions. In order to reduce the defects caused by the dopants by reducing the concentration of the depletion region on the substrate side of the junction, it is possible to reduce the junction leakage current.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1a 및 도 1b 는 본 발명의 실시예에 따른 반도체소자의 제조방법을 도시한 단면도이다.1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

먼저, 반도체기판(11) 상부에 패드절연막을 형성하되, 산화막(13)과 질화막(15)의 적층구조로 형성한다.First, a pad insulating film is formed on the semiconductor substrate 11, but a laminate structure of an oxide film 13 and a nitride film 15 is formed.

그리고, 소자분리마스크(도시안됨)를 이용한 식각공정으로 상기 적층구조를 식각하여 상기 반도체기판(11)의 활성영역을 정의하는 소자분리영역을 노출시킨다.In addition, the layer structure is etched by an etching process using a device isolation mask (not shown) to expose a device isolation region defining an active region of the semiconductor substrate 11.

그리고, 상기 패터닝된 적층구조를 마스크로하여 상기 반도체기판(11)을 식각하여 트렌치(17)를 형성한다.The semiconductor substrate 11 is etched using the patterned stacked structure as a mask to form a trench 17.

그리고, 상기 트렌치(17) 표면에 형성된 결함을 제거하기 위하여 상기 트렌치(17) 표면을 산화시켜 희생산화막(19)을 일정두께 형성한다. (도 1a)The sacrificial oxide film 19 is formed to a predetermined thickness by oxidizing the surface of the trench 17 to remove defects formed on the surface of the trench 17. (FIG. 1A)

그 다음, 상기 희생산화막(19)을 제거하여 상기 트렌치(17) 표면의 결함을 제거하고 상기 트렌치(17)를 매립하는 제1소자분리막(21)을 일정두께 형성하되, 본 발명에 따른 소자분리막 간(間) 간격의 1/5 ∼ 1/6 두께로 형성한다.Then, the sacrificial oxide film 19 is removed to remove defects on the surface of the trench 17 and form a first thickness of the first device isolation film 21 filling the trench 17, but the device isolation film according to the present invention. It is formed at a thickness of 1/5 to 1/6 of the interspace.

그리고, 마스크없이 상기 패드절연막(13,15) 및 제1소자분리막(21)을 마스크로하여 상기 트렌치(23) 하부의 반도체기판(11)에 불순물을 임플란트함으로써 필드스톱임플란트영역(23)을 형성한다. 이때, 상기 임플란트 공정은 트렌치 표면으로부터 500 ∼ 1000 Å 깊이까지 1.0 e12/㎠ ∼ 1.0 e15/㎠ 의 도우즈 ( dose ) 를 주입한다.The field stop implant region 23 is formed by implanting impurities into the semiconductor substrate 11 under the trench 23 using the pad insulating layers 13 and 15 and the first device isolation layer 21 as a mask without a mask. do. In this case, the implant process injects doses of 1.0 e12 / cm 2 to 1.0 e15 / cm 2 from the trench surface to a depth of 500 to 1000 mm 3.

후속공정으로, 상기 트렌치(17)를 매립하는 제2소자분리막(도시안됨)을 상기 제1소자분리막(21) 상부에 형성하고, 상기 제1,2소자분리막을 고온에서 열처리하여 치밀한 구조로 형성한 다음, 패드절연막 제거공정과 평탄화식각공정을 실시하여 소자분리막을 완성하고 웰마스크(도시안됨)를 이용한 임플란트공정으로 웰 임플란트, ?? 임플란트 및 채널의 문턱전압 임플란트 등의 공정을 진행하여 웰을 형성한다. (도 1b)In a subsequent process, a second device isolation film (not shown) filling the trench 17 is formed on the first device isolation film 21, and the first and second device isolation films are heat-treated at a high temperature to form a compact structure. Then, the pad isolation layer removal process and the planar etching process are performed to complete the device isolation layer, and the well implant, the implant process using a well mask (not shown). Processes such as the implant and threshold voltage implants of the channel are performed to form wells. (FIG. 1B)

본 발명의 다른 실시예는 제1소자분리막을 형성하고 열처리공정으로 제1소자분리막을 치밀한 구조로 형성한 다음, 필드스톱임플란트공정을 실시하여 필드스톱임플란트영역을 형성한 다음, 제2소자분리막을 형성할 수도 있다.According to another embodiment of the present invention, the first device isolation film is formed, the first device isolation film is formed in a compact structure by a heat treatment process, and then the field stop implant process is performed to form a field stop implant region. It may be formed.

한편, 두종류 이상의 웰을 사용하는 경우 각각 다른 형의 도펀트를 주입하기 위해 마스크를 사용할 수도 있다.In the case of using two or more types of wells, masks may be used to inject different types of dopants.

참고로, 도 2 는 종래기술과 본 발명에 따른 반도체소자의 누설전류를 도시한 그래프도로서, 전압에 따른 전류특성을 도시하되 본 발명의 경우 종래보다 많은 전압이 인가될때 종래와 같은 수준의 누설전류가 발생되어 본 발명의 전류특성이 우수함을 도시한다.For reference, Figure 2 is a graph showing the leakage current of the semiconductor device according to the prior art and the present invention, showing the current characteristics according to the voltage, but in the case of the present invention when more voltage is applied than the conventional level of leakage An electric current is generated, which shows that the current characteristics of the present invention are excellent.

그리고, 도시되지않았으나, 본 발명에 따르면 반도체소자의 도핑 등고선에 따른 소자분리영역과 활성영역의 도핑농도가 각각 4.0 ∼ 4.5 e17/㎠ 과 3.5 e17/㎠ 로 차이를 갖는다.Although not shown, according to the present invention, the doping concentrations of the device isolation region and the active region according to the doping contour of the semiconductor device differ from 4.0 to 4.5 e17 / cm 2 and 3.5 e17 / cm 2, respectively.

그러나, 종래기술에 따른 반도체소자의 도핑 등고선에 따르면 소자분리영역과 활성영역의 도핑농도가 각각 4.0 ∼ 4.5 e17/㎠ 정도를 유지하고 있어 소자의 특성을 열화시키기 용이한 등고선을 가지고 있음을 알수 있다.However, according to the doping contour of the semiconductor device according to the prior art, it can be seen that the doping concentrations of the device isolation region and the active region are maintained at about 4.0 to 4.5 e17 / cm 2, respectively, so that the characteristics of the device are easily deteriorated. .

이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 제조방법은, 트렌치를 형성하고 이를 매립하는 제1소자분리막을 일정두께 형성한 다음, 필드스톱임플란트 공정을 실시하여 소자분리 영역인 트렌치 하부에만 필드스톱임플란트영역을 형성함으로써 필드스톱임플란트영역의 불순물이 활성영역으로 확산되는 현상을 억제할 수 있어 소자의 특성 변화를 방지하고 그에 따른 반도체소자의 특성을 향상시킬 수 있는 효과를 제공한다.As described above, in the method of fabricating a semiconductor device according to the present invention, a trench is formed and a first device isolation film filling the same is formed to a predetermined thickness, and then a field stop implant process is performed to perform field stop only on the lower portion of the trench as the device isolation region. By forming the implant region, the phenomenon in which impurities in the field stop implant region are diffused into the active region can be suppressed, thereby providing an effect of preventing the characteristic change of the device and thereby improving the characteristics of the semiconductor device.

Claims (5)

반도체기판 상의 활성영역을 도포하는 패드절연막을 패터닝하는 공정과,Patterning a pad insulating film for applying an active region on the semiconductor substrate; 상기 패드절연막을 마스크로하여 상기 반도체기판을 식각해 트렌치를 형성하는 공정과,Forming a trench by etching the semiconductor substrate using the pad insulating layer as a mask; 상기 트렌치를 일정깊이 매립하는 제1소자분리막을 형성하는 공정과,Forming a first device isolation film to fill the trench with a predetermined depth; 상기 패드절연막과 제1소자분리막을 식각장벽으로 하여 상기 트렌치 하부에만 필드스톱임플란트하여 필드스톱임플란트영역을 형성하는 공정과,Forming a field stop implant region by using the pad insulating layer and the first device isolation layer as an etch barrier to field stop implants only in the lower portion of the trench; 상기 트렌치를 매립하는 제2소자분리막을 형성하고 상기 제1,2소자분리막을 열처리하여 치밀화시키는 공정을 포함하는 반도체소자의 제조방법.And forming a second device isolation film to fill the trench, and densifying the first and second device isolation films by heat treatment. 제 1 항에 있어서,The method of claim 1, 상기 패드절연막은 산화막과 질화막의 적층구조로 형성하는 것을 특징으로하는 반도체소자의 제조방법.The pad insulating film is a semiconductor device manufacturing method, characterized in that formed in a laminated structure of an oxide film and a nitride film. 제 1 항에 있어서,The method of claim 1, 상기 제1소자분리막은 소자분리영역 간(間)의 거리의 1/5 ∼ 1/6 두께로 형성하는 것을 특징으로하는 반도체소자의 제조방법.And the first device isolation film is formed at a thickness of 1/5 to 1/6 of the distance between device isolation regions. 제 1 항에 있어서,The method of claim 1, 상기 필드스톱임플란트공정은 트렌치 표면으로부터 500 ∼ 1000 Å 깊이까지 1.0 e12/㎠ ∼ 1.0 e15/㎠ 의 도우즈 ( dose ) 를 주입하는 것을 특징으로하는 반도체소자의 제조방법.The field stop implant process is a method for manufacturing a semiconductor device, characterized in that to inject a dose (1.0 e12 / cm2 to 1.0 e15 / cm2) from the trench surface to a depth of 500 ~ 1000 Å. 제 1 항에 있어서,The method of claim 1, 상기 필드스톱임플란트공정후 열처리공정으로 제1소자분리막을 치밀화시키고 후속공정을 실시하는 것을 특징으로하는 반도체소자의 제조방법.The method of manufacturing a semiconductor device, characterized in that the first device isolation film is densified by a heat treatment step after the field stop implant process and a subsequent step is performed.
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