JPH01310557A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To remove damage to the surface of a groove, which is caused by Si etching, to eliminate an increase in a collector-substrate parasitic capacity and to contrive the improvement of the operating speed of an element by a method wherein a sacrificial oxide film is provided and after boron ions are implanted in the film, the film is removed. CONSTITUTION:A groove 5 is formed by Si etching and thereafter, the bottom surface and side surface of the groove 5 are sacrificially oxidized and boron ions are implanted beyond this sacrificial oxide film (thermal oxide film) 6. Then, when the film 6 is removed, a thermal oxide film 8 is again formed on the bottom surface and the surface of the groove 5 and moreover, the groove 5 is filled with a poly Si layer 9 to form element isolation regions. Thereby, the contact of a p-type channel stopper layer 7 with an n-type buried layer can be avoided and a collector-substrate parasitic capacity that obstructs the high-speed operation of an element is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing semiconductor integrated circuits, and more particularly to a method for trench isolation.

2. Description of the Related Art A conventional method of trench isolation in a bipolar integrated circuit will be described with reference to FIGS. 2a-2d.

As shown in FIG. 2B, the P-type silicon substrate 11
After forming a medium KN type buried layer 12 and further growing an N type epitaxial layer 13, a CVD oxide film 14 is grown. Next, after patterning the CVD oxide film 14, the silicon substrate is anisotropically etched using this as a mask to form a groove 15.

Furthermore, as shown in FIG. 2, boron ions are implanted using the CVD oxide film 14 as a mask to form a P-type channel stopper layer 16 at the bottom of the groove 15.

Next, as shown in FIG. 2C, after removing the CVD oxide film 14, a thermal oxide film 17 is formed, polysilicon 18 is grown, and an etching process for planarization is performed to form the grooves 16.
fill in. Finally, as shown in FIG. 2d, the upper part of the trench 16 is selectively oxidized to grow a selective oxide film 19, thereby forming an element isolation region.

By forming the grooves as described above, element isolation with a high degree of integration is possible.

Problems to be Solved by the Invention However, in such a conventional manufacturing method, when a P-type channel stopper layer is formed by boron ion implantation, some boron is also introduced into the side surfaces of the groove, and the P-type channel stopper layer and N The mold burying layer comes into contact with each other, leading to an increase in parasitic capacitance between the collector and the substrate in the bipolar integrated circuit, which leads to a reduction in operating speed. Also, use silicone when forming grooves.

Damage caused by tinging remains until the end, causing element isolation leaks and the like.

Means for Solving the Problems In order to solve the above-mentioned problems, in the manufacturing method of the present invention, after forming a trench by silicon etching, the bottom and side surfaces of the trench are sacrificially oxidized, and the sacrificial oxide film is removed. Boron ions are then implanted. Next, when the sacrificial oxide film is removed, the bottom and surface of the trench are oxidized again, and the trench is further filled with polysilicon to form an element isolation region.

According to the method for manufacturing a semiconductor integrated circuit of the present invention, damage caused by silicon etching on the groove surface can be removed by removing the sacrificial oxide film, and boron ion implantation when forming the P-type channel stopper layer can be removed. Since the implantation is performed through the oxide film, boron ion implantation into the side surfaces of the trench can be suppressed.

Embodiment FIGS. 1A to 1E are cross-sectional views showing step-by-step cross-sectional views of a method of manufacturing element isolation of a bipolar integrated circuit as an example of the manufacturing method of the present invention.

First, in FIG. 1a [as shown, KN in the P-type silicon substrate 1]
After forming a type buried layer 2 and growing an N-type epitaxial layer 3, a CvD oxide film 4 is grown. Then l,
After patterning the /D oxide film 4, the groove 6 is formed by anisotropically etching the silicon substrate using this as a mask.

Further, as shown in FIG. 1, after forming a thermal oxide film 6 on the bottom and side surfaces of the trench 6, boron ions are implanted using the CVD oxide film 4 as a mask, and P is injected into the bottom surface of the trench 6.
A mold channel nutsopa layer 7 is formed. At this time, the side surface of the trench 5 has a small angle with respect to the ion implantation, and the thermal oxide film 6
Because it is coated with

Thereafter, as shown in FIG. 1C, the CVD oxide film 4 and the thermal oxide film 6 are removed by etching, and the damage caused to the inner surface of the trench 6 during silicon etching is removed.

Next, as shown in FIG. 1d, after forming a thermal oxide film 8 again, the trench 5 is filled by growing a nine layer of polysilicon and planarizing etching. Finally, as shown in FIG. 1e, the upper part of the trench 6 is selectively oxidized to grow a selective oxide film 10, thereby forming an element isolation region.

As described in detail, according to the method for manufacturing a semiconductor integrated circuit of the present invention, contact between the Pi channel stopper layer and the N-type buried layer can be avoided, and parasitic capacitance between the collector and the substrate that impedes high-speed operation of the device can be avoided. Can be reduced. Furthermore, since damage caused during etching for forming the grooves is removed, it is possible to realize element isolation with low leakage characteristics and high reliability.

[Brief explanation of the drawing]

1A and 1B are cross-sectional structural diagrams in the order of steps for element isolation of a bipolar integrated circuit according to an embodiment of the present invention, and FIGS. 1... P-type silicon substrate, 2... N-type buried layer, 3... N-type epitaxial layer, 4
...C'l/D oxide film, 6...Silicon groove, 6...Thermal oxide film, 7...P-type channel stopper layer, 8... ...Thermal oxide film, 9...
...Polysilicon, 1o...Locos film, 1
1...P-type silicon substrate, 12...N-type buried layer, 13...N-type epitaxial layer,
14. River... CvD oxide film, 16... Silicon groove, 16... P-type channel stopper layer, 17
...-thermal oxide film, 18...polysilicon,
19...LOG OS film. Name of agent: Patent attorney Toshio Nakao and 1 other person1-
Figure 2
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Claims (1)

[Claims] A step of forming a first insulating film on a semiconductor substrate, a step of selectively etching away the first insulating film, and a step of selectively etching the semiconductor substrate using the remaining first insulating film as a mask. a step of thermally oxidizing the inner surface of the formed trench; a step of forming an impurity layer under the bottom surface of the trench using the first insulating film as a mask; a step of etching away a thermal oxide film on the film and the inner surface of the trench; a step of forming a second insulating film on the semiconductor substrate and the inner surface of the trench; a step of burying the trench with a semiconductor film; 1. A method of manufacturing a semiconductor integrated circuit, comprising the step of selectively thermally oxidizing the upper part of a trench filled with.