JP3207561B2 - Semiconductor integrated circuit and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a method of manufacturing the same, and more particularly, to a structure of a high frequency bipolar transistor and a method of forming the same.

[0002]

2. Description of the Related Art Conventionally, a lateral (horizontal) PNP transistor is most often used as a high-frequency PNP transistor. FIG. 6 shows a cross-sectional structure of a conventional lateral PNP transistor.

Here, 40 is a P-type substrate, 41 is an N-type buried layer, 42 is a P-type epitaxial layer, 43 is an N-type well for a base region, 44 is a field insulating film for element isolation, and 45 is a substrate surface. Thin oxide film formed on a part of
6 is a polysilicon sidewall defining an emitter opening, 47 is a base electrode contact region (N-type diffusion region), and 48 is a collector region (P ⁺ Diffusion region), 49 is an emitter region (P ⁺ A diffusion region), 50 is an interlayer insulating film (including an insulating film on the side wall of the emitter opening), 51 is a base electrode,
52 is a collector electrode and 53 is an emitter electrode.

The above-mentioned lateral PNP transistor has a structure in which the collector surrounds the emitter in order to efficiently collect holes injected from the emitter, but between the collector and the base by the base junction on the side opposite to the emitter side of the collector. The challenge was how to reduce the parasitic capacitance.

Also, holes injected from the bottom of the emitter become base currents and cause a reduction in the current amplification factor hfe. Therefore, in order to reduce the base-emitter parasitic capacitance due to the base-emitter junction, the area of the emitter bottom is reduced. It was also an issue to make it smaller. Further, it has been a problem to reduce the parasitic capacitance between the base and the substrate in order to improve the high frequency characteristics.

In order to solve the above problems, a collector as small as possible by diffusion from polysilicon also serving as an electrode,
A method of using a self-alignment technique for forming an emitter to minimize the parasitic capacitance between the collector and base and the parasitic capacitance between the base and emitter of the lateral PNP transistor and improve the frequency characteristics has been used.

However, this method improves the characteristics when the current is small, but is unsuitable when a large current is required. The reason is that the current that can flow in the lateral PNP transistor is basically limited by the area of the side surface of the emitter diffusion.

[0008]

As described above, the conventional method using the self-alignment technique to improve the frequency characteristics of the lateral PNP transistor has a problem that it is not suitable for a transistor having a large current capacity. .

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has a lateral transistor bipolar transistor having a small parasitic capacitance between a collector and a base, excellent frequency characteristics, and a large current capacity. It is an object to provide an integrated circuit and a method for manufacturing the same.

[0010]

According to the present invention, there is provided a semiconductor integrated circuit, comprising: a semiconductor substrate of a first conductivity type; a first semiconductor region of a second conductivity type formed on a surface of the semiconductor substrate; A first groove formed in a direction substantially perpendicular to the surface of the semiconductor region for isolating the first semiconductor region into a plurality of regions; and a first groove in the first semiconductor region. A second semiconductor region of the first conductivity type formed in contact with
The semiconductor device is characterized by comprising a third semiconductor region of the first conductivity type formed opposite to the second semiconductor region in the first semiconductor region.

Further, according to a method of manufacturing a semiconductor integrated circuit of the present invention, a step of forming a buried layer of a first conductivity type in a semiconductor substrate of a first conductivity type, and a step of epitaxially growing the buried layer on the semiconductor substrate and the buried layer, Forming a two-conductivity-type first semiconductor region, forming a first insulating film on the first semiconductor region, and opening a position in the insulating film where a groove is to be formed; A step of introducing a first conductivity type impurity into the first semiconductor region from at least a part of the opening formed in the above step to form a second semiconductor region; Forming a groove reaching the semiconductor substrate from the first semiconductor region, separating the first semiconductor region into a plurality of grooves by using the groove, and forming a second semiconductor region including the second semiconductor region.
A first conductive type semiconductor region opposed to the second semiconductor region;
Forming a conductive type third semiconductor region.

[0012]

In the semiconductor integrated circuit of the present invention, a lateral PNP transistor having a first semiconductor region as a base, a second semiconductor region as a collector, and a third semiconductor region as an emitter is formed. Since the collector is formed in contact with the first trench for element isolation, the collector-base junction surface is only a surface contributing to the currents facing each other, and unnecessary parasitic capacitance between the collector and the base is suppressed. You.

Further, the method of manufacturing a semiconductor integrated circuit according to the present invention makes it possible to realize a bipolar transistor having a sufficient performance within the range of normally achievable miniaturization technology and self-alignment technology.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIGS. 1A to 1D and FIGS. 2A to 2C show a lateral PNP according to a first embodiment of the present invention.
2 shows a cross-sectional structure of a semiconductor wafer in a main step of a transistor manufacturing method.

FIG. 3 shows an example of a plane pattern of a lateral PNP transistor formed by the manufacturing method of FIGS. 1 and 2. The cross-sectional structure along the line BB in FIG. 3 is shown in FIG. Corresponding to Hereinafter, a first embodiment of a method for manufacturing a lateral PNP transistor will be described with reference to FIGS.

First, as shown in FIG. 1A, an N-type buried layer 2 is formed on a P-type semiconductor substrate (for example, a silicon substrate) 1. Next, an N-type epitaxial layer (first semiconductor region) 3 is formed by epitaxial growth on the semiconductor substrate 1 and the N-type buried layer 2.

Next, a first layer is formed on the epitaxial layer 3.
Is formed. At this time, the epitaxial growth layer 3
After oxidizing the surface to form a thermal oxide film 4, a silicon nitride film 5 and a CVD (vapor phase growth) oxide film 6 are sequentially formed.

Next, a resist film is applied on the CVD oxide film 6, exposed, developed, and patterned to form a resist pattern 7. Using the resist pattern 7 as a mask, the CVD oxide film 6, the silicon nitride film 5, and the oxide film 4 are etched to open a position where a groove is to be formed, thereby forming an opening.

Next, after removing the resist pattern 7, as shown in FIG. 1B, a BSG film (boron silicate glass film) 8 is deposited and subjected to a thermal diffusion process at 1000 ° C. for 2 hours. A P-type diffusion layer (second semiconductor region 91 and third semiconductor region 92) is formed on the substrate surface at the bottom of the opening.
To form In this case, N including the second semiconductor region 92
A third semiconductor region 92 is formed between the second semiconductor regions 92 in the type epitaxial layer 3 so as to face the second semiconductor region 92.

Next, as shown in FIG.
By anisotropic ion etching using (reactive ion etching), a first groove 10 and a second groove 11 having a smaller depth are formed on the substrate surface. At this time, a portion to be the second groove 11 is covered with a resist film (not shown),
The substrate surface is etched by about 3 μm. Thereafter, the resist film is peeled off, and the surface of the substrate is etched by about 2 μm.

As a result, the first groove 10 is formed so as to reach the substrate 1, and the N-type region (epitaxial layer 3 and buried layer 2) is separated into a plurality (element isolation) by the groove 10, and the second groove 10 is formed. The trench 11 can be formed so as to reach the N-type buried layer 2 and can be used as a base extraction region of the PNP transistor.

When a vertical NPN transistor is formed at the same time as the lateral PNP transistor, a collector extraction region for the NPN transistor can be formed simultaneously with the formation of the second groove.

Next, as shown in FIG.
After the thermal oxide film 13 is formed in 0 and 11, a P-type diffusion layer 14 for a channel stopper is formed on the substrate surface at the bottom surface of the first groove 10 by implanting boron ions. In this case, the concentration of the N-type buried layer 2 is higher than the concentration of the P-type diffusion layer 14.
Is sufficiently high, the P-type diffusion layer 14 for the channel stopper is not formed on the bottom surface of the second groove 11.

Subsequently, a polysilicon film is deposited on the upper surface of the substrate so as to be thinner (about 150 nm) than the width of the trenches 10 and 11, and anisotropic ion etching is performed so that the polysilicon film 15 is left on the side surfaces of the trenches 10 and 11. I do.

Thereafter, the thermal oxide film 13 at the bottom of the groove is removed by wet etching using ammonium fluoride or the like. As a result, the polysilicon deposited inside the groove in a step described later comes into contact with the substrate 1.

Next, as shown in FIG.
A polysilicon film is deposited to a thickness of about 2 μm on the upper surface of the substrate so as to fill the insides of 0 and 11. Thereafter, the polysilicon film is etched by a surface polishing method until the CVD oxide film 6 is exposed on the surface. Further, after the CVD oxide film 6 is etched with ammonium fluoride or the like, the polysilicon film is flattened again to the surface of the nitride film 5 by a surface polishing method. Thereby, the grooves 10, 11
Polysilicon 16 and 17 buried corresponding to the inside of
Remains. Thereafter, the polysilicons 16 and 17 are doped with an N-type impurity such as phosphorus by ion implantation or the like.

Further, as shown in FIG. 2 (b), a nitride film is deposited to a thickness of about 100 nm, patterned to form a nitride film pattern 18, and oxidized to about 800 nm in the same manner as in a normal selective oxidation method. As a result, the field area 1
The surface of the polysilicon 16 and 17 in the trench and the substrate 9 is oxidized.

After that, as shown in FIG. 2C, an insulating film 20 is deposited on the upper surface of the substrate, a contact hole is opened, an aluminum film is deposited by a sputtering method, and patterning is performed to form a collector electrode. (C) 21, a base electrode (B) 22, and an emitter electrode (E) 23 are formed. Thus, a lateral PNP transistor having a planar pattern as shown in FIG. 3 is formed.

In FIG. 3, reference numeral 91 denotes a collector region;
Is an emitter region, 16 is a polysilicon region in the first groove 10, 21 is a collector electrode, 22 is a base electrode, 2
3 is an emitter electrode.

The lateral PNP transistor formed as shown in FIGS. 2C and 3 includes a P-type semiconductor substrate 1 and an N-type first P-type transistor formed on the surface of the semiconductor substrate.
Formed in a direction substantially perpendicular to the surface of the first semiconductor region (2, 3) and the first semiconductor region (2, 3), and separates the first semiconductor region (2, 3) into a plurality of regions. A first trench 10 for element isolation and the first semiconductor region (2,
3), a P-type second semiconductor region 91 formed in contact with the first groove 10 and the first semiconductor region (2,
In the direction substantially perpendicular to the surface of 3), the depth is smaller than the first groove 10 and deeper than the second semiconductor region 91, and the insulator 13 is formed at least on the inner peripheral surface. A second groove 11 and a P-type third formed in contact with the second groove 11 in the first semiconductor region (2, 3) and opposed to the second semiconductor region 91; The semiconductor device includes a semiconductor region 92 and a conductor 17 buried in the second groove 11 and having a bottom surface in contact with the first semiconductor region (2, 3).

That is, a lateral PNP transistor having the first semiconductor region (2, 3) as a base, the second semiconductor region 91 as a collector, and the third semiconductor region 92 as an emitter is formed. Since the collector 91 is formed in contact with the first groove 10 for element isolation, the collector 91
The base junction surface is only a surface that contributes to the currents facing each other, and unnecessary parasitic capacitance between the collector and the base is suppressed.

Similarly, since the emitter 92 is formed in contact with the second groove 11, the base-emitter junction surface is only a surface contributing to currents facing each other, and unnecessary base-emitter parasitic capacitance is generated. Is suppressed. as a result,
Frequency characteristics and current characteristics are improved as compared with a conventional lateral PNP transistor.

Further, according to the above-described method of manufacturing a bipolar transistor, a bipolar transistor having a sufficient performance within the range of normally achievable miniaturization technology and self-alignment technology can be realized.

FIGS. 4A to 4D and FIGS. 5A to 5C show a lateral PNP according to a second embodiment of the present invention.
2 shows a cross-sectional structure of a semiconductor wafer in a main step of a transistor manufacturing method. Hereinafter, the second method of the above manufacturing method will be described.
An embodiment will be described. First, as shown in FIG. 4A, a step similar to the step described above with reference to FIG. 1A is performed.

That is, an N-type buried layer 2 is formed on a P-type silicon substrate 1, and an N-type epitaxial layer 3 is formed thereon. Next, a thermal oxide film 4, a silicon nitride film 5, and a CVD oxide film 6 are sequentially formed on the epitaxial layer 3. Next, a resist pattern 7 is formed on the CVD oxide film 6. Then, using the resist pattern 7 as a mask, the CVD oxide film 6, the silicon nitride film 5, and the oxide film 4 are opened.

Next, after removing the resist pattern 7, as shown in FIG. 4B, the first groove 10 and a shallower groove than the first groove 10 are formed on the substrate surface by anisotropic ion etching using RIE. The second groove 11 is formed. At this time, the portion to be the second groove 11 is covered with a resist film, and the substrate surface is etched by about 3 μm. Thereafter, the resist film is peeled off, and the surface of the substrate is etched by about 2 μm. As a result, the first groove 10 is formed so as to reach the substrate, the N-type epitaxial layer 3 is element-separated by the first groove 10, and the second groove 11 is formed in the N-type buried layer 2
And can be used to take out the base of the PNP transistor. Thereafter, the grooves 10, 1
In FIG. 1, a thermal oxide film 13 is formed.

Next, as shown in FIG. 4C, boron ions B ⁺ To form a P-type diffusion layer 14 for a channel stopper on the surface of the substrate at the bottom of the first groove 10.
At this time, the second semiconductor region 91a and the third semiconductor region 92a into which boron ions are implanted are also formed on the side surfaces of the grooves 10 and 11 by performing ion implantation at an angle of 7 to 45 degrees with respect to the upper surface of the substrate. I do. In this case, since the concentration of the N-type buried layer 2 is sufficiently higher than the concentration of the P-type diffusion layer 14, the bottom of the second groove 11 has a P-type channel stopper.
The mold diffusion layer 14 is not formed.

Subsequently, a polysilicon film is deposited on the upper surface of the substrate so as to be thinner (about 150 nm) than the width of the grooves 10 and 11 and anisotropic ion etching is performed so that the polysilicon film 15 is left on the side surfaces of the grooves 10 and 11. I do.

Thereafter, as shown in FIG. 4D, the thermal oxide film 13 at the bottom of the groove is removed by wet etching using ammonium fluoride or the like. As a result, the polysilicon deposited inside the groove in a step described later comes into contact with the substrate. Thereafter, as shown in FIGS. 5A to 5C, steps similar to the steps described above with reference to FIGS. 2A to 2C are performed.

That is, as shown in FIG.
A polysilicon film is deposited to a thickness of about 2 μm on the upper surface of the substrate so as to fill the insides of 0 and 11. Thereafter, the polysilicon film is etched by a surface polishing method until the CVD oxide film 6 is exposed on the surface. Further, after the CVD oxide film 6 is etched with ammonium fluoride or the like, the polysilicon film is flattened again to the surface of the nitride film 5 by a surface polishing method. Thereby, the grooves 10, 11
Polysilicon 16 and 17 buried corresponding to the inside of
Remains. Thereafter, the polysilicons 16 and 17 are doped with an N-type impurity such as phosphorus by ion implantation or the like.

Further, as shown in FIG. 5B, a nitride film is deposited to a thickness of about 100 nm, patterned to form a nitride film pattern 18, and oxidized to about 800 nm in the same manner as in a normal selective oxidation method. As a result, the field area 1
The surface of the polysilicon 16 and 17 in the trench and the substrate 9 is oxidized.

Thereafter, as shown in FIG. 5C, an insulating film 20 is deposited on the upper surface of the substrate, a contact hole is opened, an aluminum film is deposited by a sputtering method, and patterning is performed. 21, a base electrode 22, and an emitter electrode 23 are formed. Thus, a transistor having a planar pattern as shown in FIG. 3 is formed. Lateral PN of the second embodiment as described above
According to the P transistor, the lateral PNP of the first embodiment is used.
An effect similar to that of a transistor can be obtained.

In addition, the second semiconductor region (collector) 9
The effect obtained by the fact that the 1a and the third semiconductor region (emitter) 92a are formed by performing ion implantation at an angle to the upper surface of the substrate is obtained. That is, the collector,
Since the effective area of the emitter can be increased along the depth direction of the grooves 10 and 11, more current can flow than in a conventional lateral PNP transistor.

As a result, frequency characteristics and current characteristics are improved as compared with the conventional lateral PNP transistor. Therefore, in order to realize a lateral PNP transistor that allows a certain amount of current to flow, a large number of transistors have conventionally been formed and connected in parallel. However, the lateral PNP transistor of the above embodiment requires only a small number of transistors. The degree of integration of an integrated circuit chip on which is mounted is improved.

In each of the above embodiments, the emitter 9
The structure 2 and the base take-out structure may be the same as those of the related art, and only the collector may be configured as described in the above embodiment. That is, in the above embodiment, the emitter 92 is formed in contact with the second groove 11, but the emitter may be formed with the same structure as that of the related art.

Further, the polysilicon 17 in the second groove 11
Is used to take out the base electrode 22, but the entire inside of the second groove 11 is filled with an insulator, or the base electrode is taken out with the same structure as the conventional one without forming the second groove 11. Alternatively, the number of steps may be reduced.

The first trench 10 for element isolation is filled with an oxide film 13 and polysilicon 16 doped with impurities. However, the present invention is not limited to this, and the first trench 10 has an insulating structure necessary for element isolation. do it.

[0049]

As described above, according to the present invention, a semiconductor integrated circuit having a bipolar transistor having a lateral structure with a collector-base parasitic capacitance as small as possible, good frequency characteristics, and a large current capacity, and the same. A manufacturing method can be realized.

[Brief description of the drawings]

FIG. 1 is a view showing a cross-sectional structure of a semiconductor wafer in a part of main steps of a method for manufacturing a lateral PNP transistor according to a first embodiment of the present invention.

FIG. 2 is a view showing a cross-sectional structure of the semiconductor wafer in a step following the step of FIG. 1;

FIG. 3 is a view showing an example of a plane pattern of a lateral PNP transistor formed by the manufacturing method of FIGS. 1 and 2;

FIG. 4 is a view showing a cross-sectional structure of a semiconductor wafer in a part of main steps of a method for manufacturing a lateral PNP transistor according to a second embodiment of the present invention.

FIG. 5 is a view showing a cross-sectional structure of the semiconductor wafer in a step following the step of FIG. 4;

FIG. 6 is a sectional view showing a part of a conventional lateral PNP transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... N type buried layer, 3 ... N type epitaxial layer (first semiconductor region), 4 ... Thermal oxide film, 5 ...
Silicon nitride film, 6: CVD oxide film, 7: BSG film, 9
1, 91a... P-type diffusion layer (second semiconductor region), 92,
92a: P-type diffusion layer (third semiconductor region), 10: first
Groove 11; second groove 13; thermal oxide film 14; P-type diffusion layer for channel stopper 15; polysilicon film
16, 17 ... polysilicon, 19 ... field area, 2
0: insulating film, 21: collector electrode, 22: base electrode,
23 ... Emitter electrode.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/73-29/737 H01L 21/331

Claims (4)

(57) [Claims] 1. A semiconductor substrate of a first conductivity type, a first semiconductor region of a second conductivity type formed on a surface of the semiconductor substrate, and a direction substantially perpendicular to a surface of the first semiconductor region. A first trench for element isolation for isolating the first semiconductor region into a plurality of regions, and a first trench formed in a direction substantially perpendicular to the surface of the first semiconductor region.
A second groove having an insulator formed on at least an inner peripheral surface thereof
When embedded in the second groove, the bottom surface first semiconductor
A conductor in contact with a region, a second semiconductor region of a first conductivity type formed in contact with the first groove in the first semiconductor region, and a second semiconductor region in the first semiconductor region. opposite the second semiconductor region, the third semiconductor region of the first conductivity type formed in contact with the second groove, provided with a depth of the second groove is the first Shallower than the groove
A semiconductor integrated circuit, which is deeper than the second semiconductor region . 2. The semiconductor integrated circuit according to claim 1, wherein said first semiconductor region is a base, said second semiconductor region is a collector, and said third semiconductor region is an emitter.
A semiconductor integrated circuit, wherein an NP transistor is formed. 3. A step of forming a buried layer of a second conductivity type on a semiconductor substrate of a first conductivity type, and epitaxially growing the buried layer on the semiconductor substrate and the buried layer to form a first semiconductor region of a second conductivity type. Forming a first insulating film on the first semiconductor region, forming a hole in the insulating film at a position where a groove is to be formed, and forming a hole in the insulating film. Introducing a first conductivity type impurity into the first semiconductor region from at least a part of the first semiconductor region to form a second semiconductor region; and forming a groove reaching the semiconductor substrate from the opening. A step of separating the first semiconductor region into a plurality of regions by the groove; and a third region of the first conductivity type facing the second semiconductor region in the second conductivity type semiconductor region including the second semiconductor region. Forming a semiconductor region The method of manufacturing a semiconductor integrated circuit according to claim. 4. A step of forming a buried layer of a second conductivity type on a semiconductor substrate of a first conductivity type, and epitaxially growing the buried layer on the semiconductor substrate and the buried layer to form a first semiconductor region of a second conductivity type. Forming a first insulating film on the first semiconductor region, forming a hole in the insulating film at a position where a groove is to be formed, and forming a hole in the insulating film. Forming a first groove reaching the semiconductor substrate from above and a second groove reaching the buried layer; and forming an insulating film on an inner peripheral surface of the first groove and an inner peripheral surface of the second groove. Forming a second semiconductor region by introducing an impurity of a first conductivity type into a portion of the first semiconductor region that is in contact with the first trench, and forming a first conductive region in a portion that is in contact with the second trench. For forming a third semiconductor region by introducing a type impurity A step of burying an insulator in the first groove to divide the first semiconductor region into a plurality of parts; and a step of burying a conductor in the second groove. Circuit manufacturing method.