JP3142336B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed and high-performance bipolar transistor using a heteroepitaxial technique in a base region and a method of manufacturing the same.

[0002]

2. Description of the Related Art High-performance bipolar transistor devices are:
It is used in various fields such as electronic computers, optical communications, and various analog circuits. Recently, several bipolar transistors incorporating heteroepitaxial technology have been proposed, and the cutoff frequency of the prototyped bipolar transistor is 80G.
Hz (for example, IEEE transon E
lectron Device, vol. ED-38, Feb. 1991, p378, JP-A-2-40923, IEDM'90, p13).

A conventional method for manufacturing a bipolar transistor will be described with reference to FIG. First, a P-type silicon substrate 10
An N-type epitaxial layer 103 is formed on the substrate 1 via an N ⁺ impurity layer 102 (see FIG. 5A). Thereafter, an oxide film 4 is formed as an element isolation using a trench technique and an oxide film selective embedding technique (see FIG. 5A). Next, after a layer 105 made of, for example, SiGe containing boron is epitaxially grown on the surface of the element region, the oxide film 1 is formed on the entire surface.
06 and a nitride film (Si ₃ N ₄ film) 1 serving as an oxidation resistant mask
07, and a nitride film 107 and an oxide film 106
(See FIG. 5A). After that, a polysilicon film 108 is deposited, boron ions are implanted into the polysilicon film 108, and then an oxide film 109 is deposited on the entire surface by using the CVD method. Then, the SiGe layer 105 on the region where the emitter base is to be formed is exposed. Until the CVD oxide film 109 and the polysilicon film 10
8, an opening is provided by opening the nitride film 107 and the oxide film 106 (see FIG. 5A).

Thereafter, an oxide film 110 is formed on the entire surface, and is etched back using anisotropic etching.
The oxide film 110 is left only on the side of the opening (see FIG. 5B). Then, a polysilicon film 111 doped with arsenic at a high concentration is deposited to fill the opening (see FIG. 5C). Thereafter, by performing a heat treatment, arsenic is diffused into the SiGe layer 105 to form an N-type emitter layer on the SiGe layer 105, and the polysilicon film 10
8 is diffused into the N-type epitaxial layer 103 via the SiGe layer 105 to form the external base region 1.
13 are formed on the N-type epitaxial layer 103 (FIG. 5).
(C)). The polysilicon films 108 and 111 are used as a base electrode and an emitter electrode, respectively.

[0005]

In such a conventional manufacturing method, a base layer is formed by a heteroepitaxial technique, and a diffusion layer having a width of 50 nm or less can be formed by a polysilicon emitter technique. Accordingly, a bipolar transistor that can operate at high speed can be obtained. However, in the conventional method, it is difficult to control the shape of the external base diffusion layer 113, which may increase the collector-base capacitance due to the external base diffusion layer, thereby hindering a high speed operation of the bipolar transistor. there were.

The present invention has been made in view of the above problems, and has as its object to provide a high-speed and high-performance semiconductor device and a method of manufacturing the same.

[0007]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising: an element isolation formation area and an inter-electrode isolation formation area on a semiconductor substrate on which a collector layer comprising a first conductivity type semiconductor layer is formed. Forming an element isolation region, an inter-electrode isolation region, and an intrinsic element region by burying a first insulating film in the substrate; and forming a first insulating film on the entire surface of the substrate on which the element isolation region, the inter-electrode isolation region, and the intrinsic element region are formed. Forming a base layer composed of a two-conductivity-type semiconductor layer; and forming a boundary between the intrinsic element region and the first-conductivity-type semiconductor layer and the first insulating film that form the intrinsic element region on the base layer. Forming a second insulating film so as to cover; forming a second conductive type first conductive film that covers the base layer and the second insulating film; and forming the first conductive film. Third Absolute Above Forming a film and then forming an opening on the intrinsic element region; and forming a second conductive type of a first conductive type in the opening with a side wall insulated from the first conductive film. Forming a body film, and then forming a first conductivity type emitter region in the base layer by diffusing a first conductivity type impurity from the second conductor film to the base layer. It is characterized by being.

A semiconductor device according to the present invention comprises a semiconductor substrate having a first conductivity type intrinsic element region and an element isolation region formed thereon, and a second conductivity type semiconductor layer formed on the semiconductor substrate. A base layer; a first insulating film formed on the base layer so as to cover the intrinsic element region and a boundary between the intrinsic element region and the element isolation region; and a first insulating film and the base layer. A first conductive film of a second conductivity type formed so as to cover the first conductive film, a second insulating film formed on the first conductive film, and a bottom surface provided on the intrinsic element region An opening reaching the base layer, a second conductor formed in the opening, and a third insulating film insulating the first conductor and the second conductor in the opening. Formed in the base layer on the bottom surface of the opening. Characterized in that it comprises an emitter region of the first conductivity type that, a.

[0009] The first insulating film may be configured to cover a boundary between the intrinsic element region and the element isolation region via the base layer extending up to the element isolation region.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A reference example of a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 1 and 2 are cross-sectional views showing the steps of manufacturing a semiconductor device manufactured according to this embodiment.

First, a high-concentration impurity layer 2 containing an N-type high-concentration impurity is formed on a P-type silicon substrate 1, and then a trench technology and an oxide film selective burying technology are used to separate the oxide film as an element isolation. A trench region 4 is formed (see FIG. 1A). Next, a thickness of 500
A CVD oxide film 5 of about nm is formed on the entire surface of the substrate, and then a polysilicon film 6 is grown on the entire surface of the substrate with a thickness of about 400 nm. Then, for example, boron is ion-implanted into the polycrystalline silicon film 6 under the conditions of a dose amount of 50 KeV and 1.0 × 10 ¹⁶ cm ⁻² , and then a CVD oxide film 7 is deposited by a CVD method (FIG. 1A )reference). After annealing at, for example, 900 ° C. for about 30 minutes, a metal film 8 made of, for example, aluminum and having a thickness of about 100 nm is formed.
(A)).

Next, the metal film 8, the CVD oxide film 7, the polysilicon film 6, and the CVD oxide film 5 on the region which will be the emitter base region later are differently exposed until the high concentration impurity layer 2 on the substrate 1 is exposed. An opening 9 having an opening width of about 1 μm is formed by using an isotropic etching technique (see FIG. 1A).

Next, the polysilicon film 6 and the high-concentration impurity layer 2 which are respectively exposed on the side and bottom surfaces of the opening are etched off by about 150 nm by isotropic reactive plasma etching. Then, a recess (not shown) having a depth of about 150 nm is formed in the portion of the polysilicon film 6 and the high-concentration impurity layer 2 where the side surface of the opening 9 is exposed.
Thereafter, a CVD oxide film 10 is deposited on the entire surface by using the CVD method, and then the other portions are formed by using reactive ion etching so that the CVD oxide film 10 remains only in the above-described recessed portion formed on the side surface of the opening 9. Is removed by etching (see FIG. 1B).

Next, only on the high-concentration impurity layer 2 exposed at the bottom surface of the opening 9, a single-crystal silicon epitaxial layer 11 doped with N-type lightly (approximately 1.0 × 10 ¹⁶ cm ⁻³ ). Is grown until the thickness thereof becomes substantially equal to the value obtained by adding the depth of the depression to the thickness of the CVD oxide film 5 (see FIG. 1C). That is, the epitaxial layer 11
Is approximately the same height as the upper surface of the CVD oxide film 5.
At this time, since the N-type high concentration impurity layer 2 is connected to a collector contact (not shown), the low concentration epitaxial layer 11 forms a part of the collector. Thereafter, the opening 9 is immersed in, for example, an NH ₄ F solution.
Then, the CVD oxide film 10 left in the recess on the side surface is removed (see FIG. 1C). At this time, a part of the CVD oxide film 7 exposed on the side surface of the opening 9 is also removed. Thereafter, the aluminum film 8 is removed, for example, by immersion in a mixed solution of sulfuric acid and hydrogen peroxide (see FIG. 1C).

Next, only the polysilicon film 6 exposed on the side surface of the opening 9 and the epitaxial layer 11 exposed on the bottom surface of the opening 9 are selectively epitaxially grown to a high concentration (about 100 nm). 5 × 10 ¹⁸ cm ^-3 )
SiGe layer 12 made of SiGe doped with boron
Is formed (see FIG. 2A).

Subsequently, a CVD oxide film 13 having a thickness of about 200 nm is applied to the entire surface of the substrate by using the CVD method, and is etched using reactive ion etching to thereby form the CVD oxide film 13 only on the side surfaces of the opening 9. (See FIG. 2B). Thereafter, a polysilicon film 14 having a thickness of about 200 nm is formed.
Arsenic is applied to the polysilicon film 14 at a dose of 5
By implanting ions under the conditions of 0 KeV and 1.0 × 10 ¹⁶ cm ⁻² and further performing a desired heat treatment, the polysilicon film 1
The arsenic added to 4 is diffused into the epitaxial layer 12, thereby forming the N-type emitter region 15 and the internal base region (see FIG. 2C). Subsequently, after a metal film made of, for example, aluminum is deposited on the entire surface of the substrate, patterning is performed to form a wiring layer, thereby forming a bipolar transistor (not shown).

In the bipolar transistor thus formed, the average distance between the polysilicon layer 6 and the silicon epitaxial layer 11 is longer than that of the conventional bipolar transistor. Is hardly formed, whereby the collector-base junction capacitance is greatly reduced, the cutoff frequency of the transistor is greatly improved, and a high-speed and high-performance bipolar transistor can be obtained.

The external base and the polysilicon film 6
And the internal base are linked by the SiGe layer 12 to which boron is added at a high concentration.

Although the epitaxial layer 12 is formed of a material made of SiGe in the above-described reference example, a hetero material having a smaller band gap than silicon may be used.

Next, a sectional view of a reference example of a semiconductor device according to the present invention is shown in FIG. The semiconductor device of this reference example is
On a P-type silicon substrate 1, an N-type high-concentration impurity layer 2 and a trench region 4 as element isolation are formed.
Then, a CVD oxide film 5, a boron-doped polysilicon film 6, and a CVD oxide film 7 are sequentially laminated.
An opening is provided in these stacked films for connection to the high-concentration impurity layer 2, and the opening width of the opening is larger in the polysilicon film 6 than in the CVD oxide film 5. And
In the opening of the CVD oxide film 5, an epitaxial layer 11 of single-crystal silicon doped with a low concentration of N-type impurity is formed. Then, a semiconductor layer 12 made of SiGe doped with boron at a high concentration is formed on the epitaxial layer 11 and on the side surface of the polysilicon film 6, and a side wall 13 made of a CVD oxide film is formed on the side surface of the opening. ing. Then, the CVD oxide films 7, 13 and Si
A polysilicon layer 14 heavily doped with arsenic is formed so as to cover the Ge layer 12.
Then, an emitter region is formed by diffusing arsenic, which is an impurity, into the SiGe layer 12.

Next, one embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 3 and 4 are cross-sectional views showing the steps of manufacturing the semiconductor device manufactured according to the present embodiment.

First, a high-concentration impurity layer 22 containing an N-type high-concentration impurity is formed on a P-type silicon substrate 21, and an N-type relatively low-concentration layer (approximately 1.0 × 10 ¹⁶ cm) is further formed thereon. ^-3
After the epitaxial layer 23 is formed by using a vapor phase growth method, a trench region 24 for element isolation and an oxide film 24a are formed by using a trench technique and an oxide film selective embedding technique (FIG. 3A). )reference). The isolation oxide film 24a is formed in an inter-electrode isolation region that separates the intrinsic element region 23a from a collector contact portion (not shown). Since the high concentration impurity layer 22 is connected to a collector contact (not shown), the epitaxial layer 23 forms a part of the collector.

Next, a high-concentration (approximately 5.times.
SiGe layer 25 with boron added to about 10 ¹⁸ cm ^-3 )
Is formed thereon, and a CVD oxide film 26 having a thickness of about 50 nm is formed thereon as an insulating film by using a CVD method, and a silicon nitride film (Si ₃₎ having a thickness of about 100 nm is formed as an oxidation-resistant insulating film.
N ₄ film) 9 is formed. Next, the nitride film 27 in a region other than the intrinsic element region 23a is formed by using reactive plasma etching.
Is removed until the underlying CVD oxide film 26 is exposed. At this time, the remaining nitride film 27 covers the intrinsic element region 23a. Next, using the remaining nitride film 27 as a mask, an oxide film in a region other than the intrinsic element region 23a is etched and removed using, for example, an NH ₄ F solution until the underlying SiGe layer 25 is exposed. Thereafter, a polysilicon film 28 having a thickness of about 400 nm is formed on the entire surface (see FIG. 3A). Then, boron is dosed to the polysilicon film 28 at a dose of 50 KeV.
Ion implantation under conditions of 1 × 10 ¹⁶ cm ⁻² (FIG. 3
(A)).

Next, a CVD oxide film 29 having a thickness of about 300 nm is formed on the polysilicon film 28 by a CVD method, and then a CV oxide film 29 on a region corresponding to the emitter diffusion region is formed.
The D oxide film 29, the polysilicon film 28, the nitride film 27, and the CVD oxide film 26 are removed by anisotropic etching until the underlying SiGe layer 25 is exposed, and the opening 30 having an opening width of about 1 μm is removed. Is formed (see FIG. 3B).

Subsequently, after a CVD oxide film 31 is entirely deposited by the CVD method, another portion of the CVD oxide film 31 is anisotropically etched so that the CVD oxide film 31 remains only on the side surfaces of the opening 30. It is removed by etching (see FIG. 4A). Next, a polysilicon film 32 having a thickness of about 200 nm is deposited on the entire surface, and arsenic is ion-implanted into the polysilicon film 32 under the conditions of a dose of 50 KeV and 1 × 10 ¹⁶ cm ⁻² , and a desired heat treatment is performed. By applying the polysilicon film 32
The arsenic implanted into the substrate is diffused into an epitaxial layer 25 made of SiGe to form an N-type emitter region and an internal base region (see FIG. 4B). Thereafter, a metal film made of, for example, aluminum is formed on the entire surface of the substrate. Then, the metal film is patterned and a wiring layer is formed to form a bipolar transistor (not shown).

In the bipolar transistor formed as described above, the nitride film 27 and the CVD oxide film 2
Since 6 completely covers intrinsic element region 23a, the diffusion of boron from polysilicon film 28 to intrinsic element region 23a due to the subsequent heat treatment is eliminated, and no external base diffusion layer is formed. That is, the nitride film 27 serving as an etching stopper has a role of further preventing the diffusion of boron. As a result, the collector-base junction capacitance is greatly reduced, so that the cutoff frequency of the bipolar transistor can be greatly improved, and a high-speed bipolar transistor can be obtained.

The external base polysilicon film 28 and the internal base link are formed by the epitaxial layer 25 to which boron is added at a high concentration. In general, when the co-doped non-selective epitaxial technique is used, the impurity (boron in this embodiment) tends to have a higher concentration on an oxide film than on silicon. If they are fitted together just below the opening 30), a sufficient link with the external base can be secured. Conversely, in order to secure a link, it is not necessary to dope boron with a high concentration as the transistor characteristics deteriorate.

In the above embodiment, the epitaxial layer 25 is made of a material made of SiGe to which boron is added at a high concentration, but a hetero material having a smaller band gap than silicon may be used.

Next, FIG. 4B is a sectional view of one embodiment of the semiconductor device according to the present invention. In the semiconductor device of this embodiment, an N-type high-concentration impurity layer 2 is formed on a P-type silicon substrate 21.
2. An N-type relatively low-concentration epitaxial layer 23 is formed, and an element isolation region 24 made of an oxide film is formed.
In addition, an inter-electrode separation region 24a is formed. The inter-electrode separation region 24a separates the intrinsic element region 23a from a collector contact portion (not shown).

Further, SiGe doped with boron at a high concentration
The layer 25 is formed so as to cover the intrinsic element region 23a, the element isolation region 24, and the inter-electrode isolation region 24a. Then, the stacked body composed of the CVD oxide film 26 and the Si ₃ N ₄ film 27 is covered with the SiGe layer 2 so as to cover the intrinsic element region 23a.
5, a polysilicon film 28 to which boron is added, and a CVD oxide film 29 are further laminated so as to cover the laminate and the SiGe layer 25. And SiGe
CVD on the intrinsic element region 23a until the layer 25 is exposed.
Oxide film 29, polysilicon film 28, Si ₃ N ₄ film 27,
An opening is provided in the CVD oxide film 26, and a side wall 31 made of a CVD oxide film is provided on a side surface of the opening. Further, an N-type emitter region 33 is formed in the SiGe layer 25 on the bottom surface of the opening, and an N-type polysilicon film 32 serving as an emitter electrode connected to the emitter region 33 is formed so as to fill the opening. Have been.

It goes without saying that the semiconductor device of this embodiment has the same effect as the semiconductor device manufactured by the manufacturing method of the present invention.

In the above-described embodiment, an NPN-type bipolar transistor has been described. However, a high-speed and high-performance PNP-type bipolar transistor can be similarly obtained.

[0033]

According to the present invention, a high-speed and high-performance semiconductor device can be obtained.

[Brief description of the drawings]

FIG. 1 is a process sectional view of a semiconductor device manufactured according to a reference example of the present invention.

FIG. 2 is a process sectional view of a semiconductor device manufactured according to a reference example of the present invention.

FIG. 3 is a process sectional view of a semiconductor device manufactured according to the embodiment of the present invention.

FIG. 4 is a process sectional view of the semiconductor device manufactured according to the embodiment of the present invention;

FIG. 5 is a process sectional view showing a conventional manufacturing method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate (P type) 2 High concentration impurity layer (N type) 4 Element isolation region 5 CVD oxide film 6 Polysilicon film (P type) 7 CVD oxide film 9 Opening 11 Epitaxial layer (N type) 12 SiGe layer ( (P type) 13 CVD oxide film 14 Polysilicon film (N type) 15 Emitter region

Claims (3)

(57) [Claims] An element isolation region is formed by embedding a first insulating film in a region where an element isolation is to be formed and a region where an interelectrode isolation is to be formed on a semiconductor substrate on which a collector layer made of a semiconductor layer of a first conductivity type is formed. Forming an inter-electrode isolation region and an intrinsic element region; and forming a base layer made of a second conductivity type semiconductor layer on the entire surface of the substrate on which the element isolation region, inter-electrode isolation region and the intrinsic element region are formed. Forming a second insulating film on the base layer so as to cover the intrinsic element region and a boundary between the first conductive type semiconductor layer and the first insulating film, which form the intrinsic element region; Forming a first conductive film of a second conductivity type covering the base layer and the second insulating film; and forming a third insulating film on the first conductive film, Work to provide an opening on the element area Forming a second conductive film of the first conductivity type with a side wall insulating the first conductive film from the first conductive film in the opening; Forming a first conductivity type emitter region in the base layer by diffusing a first conductivity type impurity into the layer. 2. A semiconductor substrate on which a first conductivity type intrinsic element region and an element isolation region are formed; a base layer made of a second conductivity type semiconductor layer formed on the semiconductor substrate; A first insulating film formed on the base layer to cover the region and a boundary between the intrinsic element region and the element isolation region; and a first insulating film formed to cover the first insulating film and the base layer. A first conductive film of a second conductivity type; a second insulating film formed on the first conductive film; and an opening provided on the intrinsic element region and having a bottom surface reaching the base layer. A second conductor formed in the opening; a side wall made of a third insulating film that insulates the first conductor and the second conductor in the opening; A first conductivity type emitter region formed in the base layer on the bottom surface of A semiconductor device characterized by comprising. 3. The semiconductor device according to claim 2, wherein the first insulating film covers a boundary between the intrinsic element region and the element isolation region via the base layer extending over the element isolation region. 13. The semiconductor device according to claim 1.