JPS62120040A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent between elements from shortcircuiting or parasitic capacity therebetween from increasing by depositing a film along the inner surface of a groove, then reducing the thickness of a film on the bottom of the groove or removing the film by anisotropic etching, implanting the first conductivity type impurity on the substrate in the bottom of the groove to form a channel stopper region. CONSTITUTION:After an n-type epitaxial layer 22 is formed on a substrate 21, a thermal oxide film 23 is formed on the surface. Then, a silicon nitride film 24 and a CVD oxide film 25 are sequentially deposited. Then, a photoresist pattern 26 is formed, and a groove 27 having a depth deeper than the bonding depth of the layer 22 is formed by anisotropically etching. Then, a thermal oxide film 28 is formed on the inner surface of the groove 27, and a silicon nitride film 29 is deposited on the entire surface. Thereafter, the substrate 21 is exposed in the bottom of the groove 27 by etching by RIE method. As a result, a silico nitride film 29' remain on the side of the groove 27. Then, boron ions are implanted to form a p<-> channel stopper region 30 on the substrate 21 in the bottom of the groove 27.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a method for manufacturing a bipolar semiconductor device or the like using trench isolation technology.

[Technical background of the invention]

In recent years, as an element isolation technique for semiconductor devices, a groove isolation technique has been used in which a groove is formed in a substrate and an element isolation material is buried in the groove. This trench isolation technology has the advantage that it can reduce parasitic capacitance compared to pn junction isolation technology, and can also reduce the area of the element isolation region and improve the degree of integration compared to selective oxidation. be.

A case in which the conventional trench isolation technique is applied to, for example, the manufacture of a bipolar semiconductor device will be described with reference to FIGS. 2(a) to 2(f).

First, for example, an n-type epitaxial layer 2 is formed on a p-type silicon substrate 1, and then a thermal oxidation layer 3 is formed on the surface of the epitaxial layer 2. Next, silicon nitride 11 was applied to the entire surface.
4 and cvom film 5 are sequentially deposited. Next, CV
D oxidation! ! A photoresist pattern 6 is formed on J5 in which a hole is formed in a portion where a groove isolation region is to be formed (see FIG. 2(a)).
(Illustrated). Next, using photoresist 1-pattern 6 as an etching-resistant mask, anisotropic etching was performed to form CVDIII.
8!5, the silicon nitride film 4 and the thermal oxidation 113 are sequentially etched, and the epitaxial layer 2 and a part of the substrate 1 are further etched to form a trench 7 deeper than the junction depth of the epitaxial layer 2. During this anisotropic etching process, the photoresist pattern 6 is removed (as shown in FIG. 2B).

Next, thermal oxidation is performed to form a thermal oxide film 8 on the inner surface of the groove 7. Subsequently, by implanting boron ions, a p-type channel stopper region 9 is formed in the substrate 1 at the bottom (as shown in FIG. 3C). Next, a polycrystalline silicon film 10 is deposited over the entire surface to a thickness of 1/2 or more of the width of the trench 7 so as to completely fill the inside of the trench 7 (as shown in FIG. 4(d)).

Next, polycrystalline silicon ##1 is etched by anisotropic etching.
0 that II! Polycrystalline silicon i! is etched more than the thickness and only inside the groove 7! Bury io-.

Next, the remaining CVD! i! The chemical film 5 is removed (as shown in the same figure (e)). Next, thermal oxidation is performed using the remaining silicon nitride m4 as an oxidation-resistant mask, resulting in polycrystalline silicon! 110--A thick thermal oxide film 11 is formed on the surface (as shown in FIG. 3(f)).

After removing the remaining silicon nitride film 4 and thermal oxide film 3, the epitaxial process is performed according to a normal bipolar process. A p-type base region, an n+ type emitter region, etc. (not shown) are formed in I2, and a bipolar semiconductor device is manufactured.

[Problems with background technology]

However, in the conventional method described above, the channel stopper is removed in the process shown in FIG. 2(C). [Impurity ( to form 9)
When ion-implanting boron), impurities are introduced not only through the thermal oxidation 18 on the bottom surface of the groove 7 but also into the epitaxial layer 2 and the substrate 1 through the thermal oxide film 8 on the side surface of the groove 7, and the p-type diffusion layer 9
' is formed.

For example, as shown in FIG. 3, if p-type diffusion layers 12 and 13 of the same conductivity type as the substrate 1 are formed across the element isolation wAl, both of them are connected to the epitaxial layer 2 and the substrate 1 around the groove 7. There is a drawback that an electrical short circuit occurs through the formed p-type diffusion layer 9- and channel stopper region 9.

Furthermore, if a sufficiently high concentration diffusion layer of the same conductivity type as the epitaxial layer 112 (for example, an n1 type buried region) is formed between the substrate 1 and the epitaxial layer 2, the side surface of the trench 7 may be formed as described above. Even if impurities are introduced into the epitaxial layer 2 and the substrate 1, it is possible to prevent the two p-type diffusion layers 12.13 from short-circuiting. A problem arises in that the size becomes large.

The above-mentioned problem occurs not only in the case of the bipolar type semiconductor device as described above (but also in the case of the complementary type (0MO8) semiconductor device).

[Purpose of the invention]

The present invention has been made to solve the above-mentioned drawbacks, and when the semiconductor layer of the second conductivity type formed on the semiconductor substrate of the first conductivity type is separated into elements by trench isolation technology, short circuits between the elements may occur. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can form a channel stopper region without increasing parasitic capacitance by 4 (1).

[Summary of the invention]

The method for manufacturing a semiconductor device of the present invention includes the steps of forming a semiconductor layer of a second conductivity type on a semiconductor substrate of a first conductivity type, and selectively forming a part of the semiconductor layer and the semiconductor substrate by anisotropic etching. etching to form a trench with substantially vertical sides and deeper than the junction depth of the semiconductor layer; depositing a film along the inner surface of the trench; and etching the film by anisotropic etching. a step of thinning or removing the film at the bottom of the groove to expose the substrate; a step of introducing an impurity of a first conductivity type only into the substrate at the bottom of the groove; The method is characterized by comprising a step of embedding an element isolation material.

In the method of the present invention, a film is deposited along the inner surface of the groove, and then the film is etched by anisotropic etching to thin the film at the bottom of the groove, or the film at the bottom of the groove is removed to remove the substrate. Then, a channel stopper region is formed by introducing impurities of the first conductivity type into the substrate at the bottom of the trench, with the film remaining on the side surfaces of the trench. Therefore, the second
The impurity of the first conductivity type is not introduced into the semiconductor layer of the conductivity type and the semiconductor substrate of the first conductivity type, but the impurity of the first conductivity type is introduced only into the substrate at the bottom of the groove. Therefore, even if the first conductivity type diffusion layer is formed in the second conductivity type semiconductor layer with the element isolation region in between, there will be no short circuit between elements or an increase in parasitic capacitance.

[Embodiments of the invention]

Hereinafter, an embodiment in which the method of the present invention is applied to the manufacture of a bipolar semiconductor device will be described with reference to FIGS. 1(a) to 1(l).

First, for example, after forming an n-type epitaxial layer 22 on a p-type silicon substrate 21, the surface of the epitaxial layer 22 is thermally oxidized. form 23. Next, a silicon nitride film 24 and a CVD oxide film 25 are sequentially deposited over the entire surface. Next, CVD oxidation! A photorenost pattern 26 is formed on the 1g 25 in which a hole is formed in a portion where a groove separation region is to be formed (as shown in FIG. 1(a)). Next, a photoresist pattern 26
C by anisotropic etching using as an etching-resistant mask.
VD oxidation 11!25, silicon nitride film 24, thermal oxide film 2
3 is sequentially etched, and then the epitaxial layer 22 and a part of the substrate 21 are further etched to form a groove 27 deeper than the junction depth of the epitaxial layer 22. During this anisotropic etching process, the photoresist pattern 26 is removed (as shown in FIG. 2B). Next, thermal oxidation is performed to form groove 2.
A thermal oxide film 28 having a thickness of approximately 1,000 wafers is formed on the inner surface of the substrate 7. Subsequently, a silicon nitride film 29 having a thickness of 1/2 or less of the width of the trench 27, for example, about 2000 silicon nitride film 29, is deposited over the entire surface along the inner surface of the trench 27 (as shown in FIG. 2C). Then,
Silicon nitride B! by reactive ion etching method (RIE method)! 29 is etched to a thickness greater than that, and further etched to a depth of 27.
Thermal oxidation [128] exposed on the bottom surface is removed to expose the substrate 21.

As a result, 1 t of thermal oxidation was applied to the side surface of the groove 27! The silicon nitride film 29- remains through the l 28 (as shown in the same figure (d)).
. Next, boron is subjected to an acceleration energy of 35 keV, for example.
ion implantation into the substrate 21 at the bottom of the trench 27.
A - type channel stopper region 30 is formed. On this occasion,
Under the above acceleration energy conditions, the film thickness on the side surface of the groove 27 is 2000, the silicon nitride film is 1!1129- and the film thickness is 1.
Since the implantation of boron ions can be sufficiently blocked by the thermal oxide film 28 of 1,000 yen, no boron is introduced into the epitaxial layer 22 and the substrate 21 on the side surface of the groove 27 (as shown in FIG. 2(e)). Then the remaining CVO
After removing the a-oxide film 125, thermal oxidation is performed to form a thermal oxide film 31 on the surface of the channel stopper region 30. Subsequently, polycrystalline silicon 1I32 is deposited over the entire surface to a thickness of 1/2 or more of the width of the groove 27 so as to completely fill the inside of the groove 27 (as shown in FIG. 2(f)). Next, the polycrystalline silicon film 32 is etched by anisotropic etching to a thickness greater than that of the polycrystalline silicon film 32, and the polycrystalline silicon film 32' is buried only in the interior of the film 27 (as shown in FIG. 12(Q)). Next, thermal oxidation is performed using the remaining silicon nitride film 24 as an oxidation-resistant mask,
A thick thermal oxide film 33 is formed on the surface of the polycrystalline silicon film 32 (as shown in FIG. 3(h)).

Below is the remaining silicon nitride! After removing 124 and the thermal oxide film 23, according to the normal bipolar process,
a p-type base region not shown in the epitaxial layer 822;
An n+ type emitter gA region and the like are formed to manufacture a bipolar semiconductor device.

In the method of the above embodiment, after the n-type epitaxial layer 22 is formed on the p-type silicon substrate 21 in the step shown in FIG. 1(a), the groove 27 is formed in the step shown in FIG. In the steps C) and (d), the substrate 21 at the bottom of the groove 27 is exposed, and the side surfaces of the groove 27 are silicon nitrided via thermal oxidation 1128! l
The channel stopper region IAt 30 is formed by leaving 1129- and implanting boron ions in the step shown in FIG. Therefore, the implantation of boron ions can be sufficiently blocked by the silicon nitride M29- and the thermal oxide film 28 on the side surface of the trench 27.
No boron is introduced into the epitaxial layer 22 and the substrate 21 on the sides of the groove 27. Therefore, even if a p-type diffusion layer (for example, the base A region) is formed in the epitaxial layer 22 with the element isolation region in between, there will be no short circuit between elements or an increase in parasitic capacitance.

In the above embodiment, a silicon nitride film was used as the film left on all 27 sides in the step of FIG. 1(d), but the present invention is not limited to this, and a CVD oxide film or a polycrystalline silicon film may also be used. In addition, in the step of FIG. 1(d), the substrate 2 at the bottom of the groove 27 is
1 is exposed, but if the film at the bottom of the trench 27 is thinner than the film remaining on the copper surface, it is possible to selectively dope only the substrate 21 at the bottom of the trench 27 with impurities by ion implantation. . In addition, when the substrate 21 with 27 bottoms is exposed as in the above embodiment, it is possible to perform BSGI on the entire surface in addition to the ion implantation method. After I@ deposition, the channel stopper region 30 may be formed by diffusing boron by thermal diffusion.

Further, in the above embodiment, polycrystalline silicon was used as the element isolation material buried in the trench 27, but an insulating film such as a CVD oxide film or a silicon nitride film may also be used.

Furthermore, in the above explanation, the method of the present invention is applied to the manufacturing of bipolar type semiconductor devices, but the method of the present invention can be similarly applied as an element isolation method for semiconductor devices such as complementary type (0MO8) semiconductor devices. Of course it can be done.

〔Effect of the invention〕

As detailed above, according to the method of the present invention, when a semiconductor layer of a second conductivity type formed on a semiconductor substrate of a first conductivity type is subjected to element isolation using trench isolation technology, short circuits between elements and parasitic capacitances can be prevented. It is possible to form a channel stopper region without causing an increase, and effects such as a reduction in parasitic capacitance and an improvement in the degree of integration can be obtained.

[Brief explanation of drawings]

FIGS. 1(a) to (h) are cross-sectional views showing a method for manufacturing a bipolar semiconductor device using trench isolation technology according to an embodiment of the present invention, and FIGS. A cross-sectional view showing a method for manufacturing a bipolar semiconductor device using technology,
FIG. 3 is a cross-sectional view showing the drawbacks of the conventional method. 21...p-type silicon substrate, 22...n-type epitaxial layer, 23.28.31...thermal oxide film, 24.2
9.29-...Silicon nitride film, 25...CVD1
II film, 26... Photoresist pattern, 27...
- Groove, 30...p-type channel stopper region, 32
．． 32-... Polycrystalline silicon film, 33... Thick thermal oxide film. Applicant's agent Patent attorney Takehiko Suzue Figure 1

Claims (1)

[Claims] forming a semiconductor layer of a second conductivity type on a semiconductor substrate of a first conductivity type; selectively etching the semiconductor layer and a part of the semiconductor substrate by anisotropic etching to form substantially vertical side surfaces; a step of forming a groove deeper than the junction depth of the semiconductor layer; a step of depositing a film along the inner surface of the groove; and etching the film by anisotropic etching.
A step of exposing the substrate by thinning the coating at the bottom of the groove or removing the coating at the bottom of the groove;
1. A method for manufacturing a semiconductor device, comprising the steps of introducing a conductivity type impurity and burying an element isolation material inside the trench.