JPS62120040A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62120040A
JPS62120040A JP26045185A JP26045185A JPS62120040A JP S62120040 A JPS62120040 A JP S62120040A JP 26045185 A JP26045185 A JP 26045185A JP 26045185 A JP26045185 A JP 26045185A JP S62120040 A JPS62120040 A JP S62120040A
Authority
JP
Japan
Prior art keywords
groove
film
substrate
oxide film
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26045185A
Other languages
Japanese (ja)
Inventor
Takao Ito
隆夫 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP26045185A priority Critical patent/JPS62120040A/en
Publication of JPS62120040A publication Critical patent/JPS62120040A/en
Pending legal-status Critical Current

Links

Landscapes

  • Element Separation (AREA)

Abstract

PURPOSE:To prevent between elements from shortcircuiting or parasitic capacity therebetween from increasing by depositing a film along the inner surface of a groove, then reducing the thickness of a film on the bottom of the groove or removing the film by anisotropic etching, implanting the first conductivity type impurity on the substrate in the bottom of the groove to form a channel stopper region. CONSTITUTION:After an n-type epitaxial layer 22 is formed on a substrate 21, a thermal oxide film 23 is formed on the surface. Then, a silicon nitride film 24 and a CVD oxide film 25 are sequentially deposited. Then, a photoresist pattern 26 is formed, and a groove 27 having a depth deeper than the bonding depth of the layer 22 is formed by anisotropically etching. Then, a thermal oxide film 28 is formed on the inner surface of the groove 27, and a silicon nitride film 29 is deposited on the entire surface. Thereafter, the substrate 21 is exposed in the bottom of the groove 27 by etching by RIE method. As a result, a silico nitride film 29' remain on the side of the groove 27. Then, boron ions are implanted to form a p<-> channel stopper region 30 on the substrate 21 in the bottom of the groove 27.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体装置の製造方法に関し、特に溝分離技術
を用いてバイポーラ型半導体装置等を製造する方法の改
良に係る。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a method for manufacturing a bipolar semiconductor device or the like using trench isolation technology.

〔発明の技術的背景〕[Technical background of the invention]

近年、半導体装置の素子分離技術として、基板に溝を形
成し、この溝内に素子分離材料を埋設する溝分離技術が
用いられている。この溝分離技術は、pn接合分離技術
と比較して奇生容量を小さくすることができ、しかも選
択酸化法よりも素子分離領域の面積を縮小して集積度を
向上することができるという利点がある。
In recent years, as an element isolation technique for semiconductor devices, a groove isolation technique has been used in which a groove is formed in a substrate and an element isolation material is buried in the groove. This trench isolation technology has the advantage that it can reduce parasitic capacitance compared to pn junction isolation technology, and can also reduce the area of the element isolation region and improve the degree of integration compared to selective oxidation. be.

従来の溝分離技術を例えばバイポーラ型半導体装置の製
造に適用した場合について、第2図(a)〜(f)を参
照して説明する。
A case in which the conventional trench isolation technique is applied to, for example, the manufacture of a bipolar semiconductor device will be described with reference to FIGS. 2(a) to 2(f).

まず、例えばp型シリコン基板1上にn型エピタキシャ
ル層2を形成した後、エピタキシャル層2の表面に熱酸
化lll3を形成する。次に、全面にシリコン窒化11
4及びcvom化膜5を順次堆積する。つづいて、CV
D酸化!!J5上に溝分離領域を形成すべき部分が開孔
したホトレジストパターン6を形成する(第2図(a)
図示)。次いで、ホトレジス1−パターン6を耐エツチ
ングマスクとして異方性エツチングによりCVDIII
化8!5、シリコン窒化膜4、熱酸化113を順次エツ
チングし、更にエピタキシャル層2、基板1の一部をエ
ツチングしてエピタキシャル層2の接合深さよりも深い
溝7を型底する。この異方性エツチング工程時に、ホト
レジストパターン6は除去される(同図(b)図示)。
First, for example, an n-type epitaxial layer 2 is formed on a p-type silicon substrate 1, and then a thermal oxidation layer 3 is formed on the surface of the epitaxial layer 2. Next, silicon nitride 11 was applied to the entire surface.
4 and cvom film 5 are sequentially deposited. Next, CV
D oxidation! ! A photoresist pattern 6 is formed on J5 in which a hole is formed in a portion where a groove isolation region is to be formed (see FIG. 2(a)).
(Illustrated). Next, using photoresist 1-pattern 6 as an etching-resistant mask, anisotropic etching was performed to form CVDIII.
8!5, the silicon nitride film 4 and the thermal oxidation 113 are sequentially etched, and the epitaxial layer 2 and a part of the substrate 1 are further etched to form a trench 7 deeper than the junction depth of the epitaxial layer 2. During this anisotropic etching process, the photoresist pattern 6 is removed (as shown in FIG. 2B).

次いで、熱酸化を行ない、溝7の内面に熱酸化膜8を形
成する。つづいて、ボロンをイオン注入することにより
満7底部の基板1にp−型チャネルストッパー領域9を
形成する(同図(C)図示)。次いで、溝7内部を完全
に埋めるように、溝7の幅の1/2以上の膜厚で全面に
多結晶シリコン膜10を堆積する(同図(d)図示)。
Next, thermal oxidation is performed to form a thermal oxide film 8 on the inner surface of the groove 7. Subsequently, by implanting boron ions, a p-type channel stopper region 9 is formed in the substrate 1 at the bottom (as shown in FIG. 3C). Next, a polycrystalline silicon film 10 is deposited over the entire surface to a thickness of 1/2 or more of the width of the trench 7 so as to completely fill the inside of the trench 7 (as shown in FIG. 4(d)).

次いで、異方性エツチングにより多結晶シリコン##1
0をそのII!厚以上エツチングして、溝7内部にのみ
多結晶シリコンi!io−を埋設する。
Next, polycrystalline silicon ##1 is etched by anisotropic etching.
0 that II! Polycrystalline silicon i! is etched more than the thickness and only inside the groove 7! Bury io-.

つづいて、残存しているCVD!i!化膜5を除去する
(同図(e)図示)。次いで、残存しているシリコン窒
化m4を耐酸化性マスクとして熱酸化を行ない、多結晶
シリコン!110−表面に厚い熱酸化膜11を形成する
(同図(f)図示)。
Next, the remaining CVD! i! The chemical film 5 is removed (as shown in the same figure (e)). Next, thermal oxidation is performed using the remaining silicon nitride m4 as an oxidation-resistant mask, resulting in polycrystalline silicon! 110--A thick thermal oxide film 11 is formed on the surface (as shown in FIG. 3(f)).

以下、残存しているシリコン窒化膜4及び熱酸化膜3を
除去した後、通常のバイポーラプロセスに従い、エピタ
キシャル!I2内に図示しないp型ベース領域、n+型
エミッタ領域等を形成し、バイポーラ型半導体装置を製
造する。
After removing the remaining silicon nitride film 4 and thermal oxide film 3, the epitaxial process is performed according to a normal bipolar process. A p-type base region, an n+ type emitter region, etc. (not shown) are formed in I2, and a bipolar semiconductor device is manufactured.

〔背景技術の問題点〕[Problems with background technology]

しかし、上述した従来の方法では、第2図(C)の工程
でチャネルストッパー![9を形成するために不純物(
ボロン)をイオン注入する際、溝7底面の熱酸化18だ
けでなく、溝7側面の熱酸化膜8を通して不純物がエピ
タキシャル層2、基板1にも導入され、p−型拡散層9
′が形成される。
However, in the conventional method described above, the channel stopper is removed in the process shown in FIG. 2(C). [Impurity ( to form 9)
When ion-implanting boron), impurities are introduced not only through the thermal oxidation 18 on the bottom surface of the groove 7 but also into the epitaxial layer 2 and the substrate 1 through the thermal oxide film 8 on the side surface of the groove 7, and the p-type diffusion layer 9
' is formed.

そして、例えば第3図に示すように素子分離wAlを挟
んで基板1と同導電型のp型拡散層12.13が形成さ
れていた場合、両者が溝7周囲のエピタキシャル層2及
び基板1に形成されるp−型拡散層9−及びチャネルス
トッパー領域9を介して電気的に短絡してしまうという
欠点がある。
For example, as shown in FIG. 3, if p-type diffusion layers 12 and 13 of the same conductivity type as the substrate 1 are formed across the element isolation wAl, both of them are connected to the epitaxial layer 2 and the substrate 1 around the groove 7. There is a drawback that an electrical short circuit occurs through the formed p-type diffusion layer 9- and channel stopper region 9.

また、基板1とエピタキシャル層2との間に、エピタキ
シャル112と同導電型の十分高濃度の拡散層く例えば
n1型埋込領域)が形成されている場合には、上記のよ
うに溝7側面のエピタキシャル層2及び基板1に不純物
が導入されても、2つのp型拡散層12.13の短絡を
防止することができるが、p型拡散層12.13とエピ
タキシャル層2との奇生客間が大きくなってしまうとい
う問題が生じる。
Furthermore, if a sufficiently high concentration diffusion layer of the same conductivity type as the epitaxial layer 112 (for example, an n1 type buried region) is formed between the substrate 1 and the epitaxial layer 2, the side surface of the trench 7 may be formed as described above. Even if impurities are introduced into the epitaxial layer 2 and the substrate 1, it is possible to prevent the two p-type diffusion layers 12.13 from short-circuiting. A problem arises in that the size becomes large.

上記のような問題は上述したようなバイポーラ型半導体
装置の場合だけでな(、相補型(0MO8)半導体装置
の場合でも同様に生じるものである。
The above-mentioned problem occurs not only in the case of the bipolar type semiconductor device as described above (but also in the case of the complementary type (0MO8) semiconductor device).

〔発明の目的〕[Purpose of the invention]

本発明は上記欠点を解消するためになされたものであり
、第1導電型の半導体基板上に形成された第2導電型の
半導体層を溝分離技術により素子分離を行なう場合、素
子間の短絡や寄生容量の増大を4(1<ことなくチャネ
ルストッパー領域を形成することができる半導体装置の
製造方法を提供しようとするものである。
The present invention has been made to solve the above-mentioned drawbacks, and when the semiconductor layer of the second conductivity type formed on the semiconductor substrate of the first conductivity type is separated into elements by trench isolation technology, short circuits between the elements may occur. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can form a channel stopper region without increasing parasitic capacitance by 4 (1).

〔発明の概要〕[Summary of the invention]

本発明の半導体装置の製造方法は、第1導電型の半導体
基板上に第2導電型の半導体層を形成する工程と、異方
性エツチングにより該半導体層及び半導体基板の一部を
選択的にエツチングして、ほぼ垂直な側面を有し、半導
体層の接合深さより深い溝を形成する工程と、該溝の内
面に沿うように被膜を堆積する工程と、異方性エツチン
グにより該被膜をエツチングして、溝底部の被膜を薄く
するか又は溝底部の被膜を除去して基板を露出させる工
程と、前記溝底部の基板にのみ第1導電型の不純物を導
入する工程と、前記溝内部に素子分離材料を埋設する工
程とを具備したことを特徴とするものである。
The method for manufacturing a semiconductor device of the present invention includes the steps of forming a semiconductor layer of a second conductivity type on a semiconductor substrate of a first conductivity type, and selectively forming a part of the semiconductor layer and the semiconductor substrate by anisotropic etching. etching to form a trench with substantially vertical sides and deeper than the junction depth of the semiconductor layer; depositing a film along the inner surface of the trench; and etching the film by anisotropic etching. a step of thinning or removing the film at the bottom of the groove to expose the substrate; a step of introducing an impurity of a first conductivity type only into the substrate at the bottom of the groove; The method is characterized by comprising a step of embedding an element isolation material.

本発明方法では、溝の内面に沿うように被膜を堆積した
後、異方性エツチングにより被膜をエツチングして、溝
底部の被膜を薄くするか又は溝底部の被膜を除去して基
板をn出させ、溝側面には被膜を残存させた状態で、溝
底部の基板に第1導電型の不純物を導入してチャネルス
トッパー領域を形成している。このため、溝側面の第2
導電型の半導体層及び第1導電型の半導体基板に第1導
電型の不純物が導入されることはなく、溝底面の基板に
のみ第1導電型の不純物が導入される。したがって、素
子分離領域を挟んで第2導電型の半導体層内に第1導電
型の拡散層が形成されていても、素子間の短絡や寄生容
量の増大をIR<ことがない。
In the method of the present invention, a film is deposited along the inner surface of the groove, and then the film is etched by anisotropic etching to thin the film at the bottom of the groove, or the film at the bottom of the groove is removed to remove the substrate. Then, a channel stopper region is formed by introducing impurities of the first conductivity type into the substrate at the bottom of the trench, with the film remaining on the side surfaces of the trench. Therefore, the second
The impurity of the first conductivity type is not introduced into the semiconductor layer of the conductivity type and the semiconductor substrate of the first conductivity type, but the impurity of the first conductivity type is introduced only into the substrate at the bottom of the groove. Therefore, even if the first conductivity type diffusion layer is formed in the second conductivity type semiconductor layer with the element isolation region in between, there will be no short circuit between elements or an increase in parasitic capacitance.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明方法をバイポーラ型半導体装置の製造に適
用した実施例を第1図(a)〜l)を参照して説明する
Hereinafter, an embodiment in which the method of the present invention is applied to the manufacture of a bipolar semiconductor device will be described with reference to FIGS. 1(a) to 1(l).

まず、例えばp型シリコン基板21上にn型エピタキシ
ャル層22を形成した後、エピタキシャル層22の表面
に熱酸化!23を形成する。次に、全面にシリコン窒化
膜24及びCVD酸化膜25を順次堆積する。つづいて
、CVD酸化!1g25上に溝分離領域を形成すべき部
分が開孔したホトレノストパターン26を形成する(第
1図(a)図示)。次いで、ホトレジストパターン26
を耐エツチングマスクとして異方性エツチングによりC
VD酸化11!25、シリコン窒化膜24、熱酸化膜2
3を順次エツチングし、更にエピタキシャル層22、基
板21の一部をエツチングしてエピタキシャル層22の
接合深さよりも深い満27を形成する。この異方性エツ
チング工程時に、ホトレジストパターン26は除去され
る(同図(b)図示)。次いで、熱酸化を行ない、溝2
7の内面に膜厚約1000人の熱酸化膜28を形成する
。つづいて、溝27の内面に沿うように、溝27の幅の
1/2以下の膜厚、例えば約2000人のシリコン窒化
膜29を全面に堆積する(同図(C)図示)。次いで、
反応性イオンエツチング法(RIE法)によりシリコン
窒化B!29をその膜厚以上エツチングし、更に満27
底面で露出する熱酸化[128を除去して基板21を露
出させる。
First, for example, after forming an n-type epitaxial layer 22 on a p-type silicon substrate 21, the surface of the epitaxial layer 22 is thermally oxidized. form 23. Next, a silicon nitride film 24 and a CVD oxide film 25 are sequentially deposited over the entire surface. Next, CVD oxidation! A photorenost pattern 26 is formed on the 1g 25 in which a hole is formed in a portion where a groove separation region is to be formed (as shown in FIG. 1(a)). Next, a photoresist pattern 26
C by anisotropic etching using as an etching-resistant mask.
VD oxidation 11!25, silicon nitride film 24, thermal oxide film 2
3 is sequentially etched, and then the epitaxial layer 22 and a part of the substrate 21 are further etched to form a groove 27 deeper than the junction depth of the epitaxial layer 22. During this anisotropic etching process, the photoresist pattern 26 is removed (as shown in FIG. 2B). Next, thermal oxidation is performed to form groove 2.
A thermal oxide film 28 having a thickness of approximately 1,000 wafers is formed on the inner surface of the substrate 7. Subsequently, a silicon nitride film 29 having a thickness of 1/2 or less of the width of the trench 27, for example, about 2000 silicon nitride film 29, is deposited over the entire surface along the inner surface of the trench 27 (as shown in FIG. 2C). Then,
Silicon nitride B! by reactive ion etching method (RIE method)! 29 is etched to a thickness greater than that, and further etched to a depth of 27.
Thermal oxidation [128] exposed on the bottom surface is removed to expose the substrate 21.

この結果、溝27側面には熱酸化1t!l 28を介し
てシリコン窒化膜29−が残存する(同図(d)図示)
。次いで、ボロンを例えば加速エネルギー35 keV
でイオン注入することにより溝27底部の基板21にp
−型チャネルストッパー領域30を形成する。この際、
上記のような加速エネルギー条件では、溝27側面の膜
厚2000人のシリコン窒化1!1129−及び膜厚1
000人の熱酸化膜28によりボロンイオンの注入°を
十分にブロックすることができるので、溝27側面のエ
ピタキシャル層22及び基板21にはボロンは導入され
ない(同図(e)図示)。次いで、残存しているcvo
a化125を除去した後、熱酸化を行ない、チャネルス
トッパー領域30表面に熱酸化膜31を形成する。つづ
いて、溝27内部を完全に埋めるように、溝27の幅の
1/2以上の膜厚で全面に多結晶シリコン1I32を堆
積する(同図(f)図示)。次いで、異方性エツチング
により多結晶シリコン躾32をその膜厚以上エツチング
して、満27内部にのみ多結晶シリコン膜32′を埋設
する(同図(Q)図示)。次いで、残存しているシリコ
ン窒化膜24を耐酸化性マスクとして熱酸化を行ない、
多結晶シリコン膜32−表面に厚い熱酸化膜33を形成
する(同図(h)図示)。
As a result, 1 t of thermal oxidation was applied to the side surface of the groove 27! The silicon nitride film 29- remains through the l 28 (as shown in the same figure (d)).
. Next, boron is subjected to an acceleration energy of 35 keV, for example.
ion implantation into the substrate 21 at the bottom of the trench 27.
A - type channel stopper region 30 is formed. On this occasion,
Under the above acceleration energy conditions, the film thickness on the side surface of the groove 27 is 2000, the silicon nitride film is 1!1129- and the film thickness is 1.
Since the implantation of boron ions can be sufficiently blocked by the thermal oxide film 28 of 1,000 yen, no boron is introduced into the epitaxial layer 22 and the substrate 21 on the side surface of the groove 27 (as shown in FIG. 2(e)). Then the remaining CVO
After removing the a-oxide film 125, thermal oxidation is performed to form a thermal oxide film 31 on the surface of the channel stopper region 30. Subsequently, polycrystalline silicon 1I32 is deposited over the entire surface to a thickness of 1/2 or more of the width of the groove 27 so as to completely fill the inside of the groove 27 (as shown in FIG. 2(f)). Next, the polycrystalline silicon film 32 is etched by anisotropic etching to a thickness greater than that of the polycrystalline silicon film 32, and the polycrystalline silicon film 32' is buried only in the interior of the film 27 (as shown in FIG. 12(Q)). Next, thermal oxidation is performed using the remaining silicon nitride film 24 as an oxidation-resistant mask,
A thick thermal oxide film 33 is formed on the surface of the polycrystalline silicon film 32 (as shown in FIG. 3(h)).

以下、残存しているシリコン窒化!124及び熱酸化膜
23を除去した後、通常のバイポーラプロセスに従い、
エピタキシャル822内に図示しないp型ベース領域、
n+型エミッタgA域等を形成し、バイポーラ型半導体
装置を製造する。
Below is the remaining silicon nitride! After removing 124 and the thermal oxide film 23, according to the normal bipolar process,
a p-type base region not shown in the epitaxial layer 822;
An n+ type emitter gA region and the like are formed to manufacture a bipolar semiconductor device.

上記実施例の方法では、第1図(a)の工程でp型シリ
コン基板21上にn型エピタキシャル層22を形成した
後、同図(b)の工程で溝27を形成し、同図(C)及
び(d)の工程で溝27底面の基板21を露出させ、溝
27側面には熱酸化1128を介してシリコン窒化!l
1129−を残存させた状態とし、同図(e)の工程で
ボロンをイオン注入することによりチャネルストッパー
領IAt 30を形成している。このため、溝27側面
のシリコン窒化M29−及び熱酸化膜28によりボロン
イオンの注入を十分にブロックすることができるので、
溝27側面のエピタキシャル層22及び基板21にはボ
ロンは導入されない。したがって、素子分離領域を挟ん
でエピタキシャル層22内にp型拡散層(例えばベース
A域)が形成されていても、素子間の短絡や奇生容量の
増大をf& <ことがない。
In the method of the above embodiment, after the n-type epitaxial layer 22 is formed on the p-type silicon substrate 21 in the step shown in FIG. 1(a), the groove 27 is formed in the step shown in FIG. In the steps C) and (d), the substrate 21 at the bottom of the groove 27 is exposed, and the side surfaces of the groove 27 are silicon nitrided via thermal oxidation 1128! l
The channel stopper region IAt 30 is formed by leaving 1129- and implanting boron ions in the step shown in FIG. Therefore, the implantation of boron ions can be sufficiently blocked by the silicon nitride M29- and the thermal oxide film 28 on the side surface of the trench 27.
No boron is introduced into the epitaxial layer 22 and the substrate 21 on the sides of the groove 27. Therefore, even if a p-type diffusion layer (for example, the base A region) is formed in the epitaxial layer 22 with the element isolation region in between, there will be no short circuit between elements or an increase in parasitic capacitance.

なお、上記実施例では第1図(d)の工程で満27側面
に残存させる被膜としてシリコン窒化膜を用いたが、こ
れに限らすCVD酸化膜や多結晶シリコン膜を用いても
よい。また、第1図(d)の工程で溝27底面の基板2
1を露出させたが、満27銅面に残存している被膜より
も溝27底面の被膜が薄ければ、イオン注入により選択
的に溝27底面の基板21にのみ不純物をドープするこ
とができる。また、上記実施例のように満27底面の基
板21を露出させた場合にはイオン注入法以外にも例え
ば全面にBSGI!I@堆積した後、熱拡散によりボロ
ンを拡散させてチャネルストッパー領域30を形成して
もよい。
In the above embodiment, a silicon nitride film was used as the film left on all 27 sides in the step of FIG. 1(d), but the present invention is not limited to this, and a CVD oxide film or a polycrystalline silicon film may also be used. In addition, in the step of FIG. 1(d), the substrate 2 at the bottom of the groove 27 is
1 is exposed, but if the film at the bottom of the trench 27 is thinner than the film remaining on the copper surface, it is possible to selectively dope only the substrate 21 at the bottom of the trench 27 with impurities by ion implantation. . In addition, when the substrate 21 with 27 bottoms is exposed as in the above embodiment, it is possible to perform BSGI on the entire surface in addition to the ion implantation method. After I@ deposition, the channel stopper region 30 may be formed by diffusing boron by thermal diffusion.

また、上記実施例では溝27内に埋設する素子分離材料
として多結晶シリコン躾を用いたが、CVD酸化膜、シ
リコン窒化膜等の絶縁膜を用いてもよい。
Further, in the above embodiment, polycrystalline silicon was used as the element isolation material buried in the trench 27, but an insulating film such as a CVD oxide film or a silicon nitride film may also be used.

更に、以上の説明では本発明方法をバイポーラ型半導体
装置の製造に適用した場合について述べたが、本発明方
法は相補型(0MO8)半導体装置等地の半導体装置の
素子分離法としても同様に適用できることは勿論である
Furthermore, in the above explanation, the method of the present invention is applied to the manufacturing of bipolar type semiconductor devices, but the method of the present invention can be similarly applied as an element isolation method for semiconductor devices such as complementary type (0MO8) semiconductor devices. Of course it can be done.

〔発明の効果〕〔Effect of the invention〕

以上詳述した如く本発明方法によれば、第1導電型の半
導体基板上に形成された第2導電型の半導体層を溝分離
技術により素子分離を行なう場合、素子間の短絡や寄生
容量の増大を招くことなくチャネルストッパー領域を形
成することができ、寄生容量の低下、集積度の向上等の
効果が得られるものである。
As detailed above, according to the method of the present invention, when a semiconductor layer of a second conductivity type formed on a semiconductor substrate of a first conductivity type is subjected to element isolation using trench isolation technology, short circuits between elements and parasitic capacitances can be prevented. It is possible to form a channel stopper region without causing an increase, and effects such as a reduction in parasitic capacitance and an improvement in the degree of integration can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(h)は本発明の実施例における溝分離
技術を用いたバイポーラ型半導体装置の製造方法を示す
断面図、第2図(a)〜(f)は従来の溝分離技術を用
いたバイポーラ型半導体装置の製造方法を示す断面図、
第3図は従来の方法の欠点を示す断面図である。 21・・・p型シリコン基板、22・・・n型エピタキ
シャル層、23.28.31・・・熱酸化膜、24.2
9.29−・・・シリコン窒化膜、25・・・CVD1
iI化膜、26・・・ホトレジストパターン、27・・
・溝、30・・・p−型チャネルストッパー領域、32
.32−・・・多結晶シリコン膜、33・・・厚い熱酸
化膜。 出願人代理人 弁理士 鈴江武彦 第1図
FIGS. 1(a) to (h) are cross-sectional views showing a method for manufacturing a bipolar semiconductor device using trench isolation technology according to an embodiment of the present invention, and FIGS. A cross-sectional view showing a method for manufacturing a bipolar semiconductor device using technology,
FIG. 3 is a cross-sectional view showing the drawbacks of the conventional method. 21...p-type silicon substrate, 22...n-type epitaxial layer, 23.28.31...thermal oxide film, 24.2
9.29-...Silicon nitride film, 25...CVD1
II film, 26... Photoresist pattern, 27...
- Groove, 30...p-type channel stopper region, 32
.. 32-... Polycrystalline silicon film, 33... Thick thermal oxide film. Applicant's agent Patent attorney Takehiko Suzue Figure 1

Claims (1)

【特許請求の範囲】[Claims] 第1導電型の半導体基板上に第2導電型の半導体層を形
成する工程と、異方性エッチングにより該半導体層及び
半導体基板の一部を選択的にエッチングして、ほぼ垂直
な側面を有し、半導体層の接合深さより深い溝を形成す
る工程と、該溝の内面に沿うように被膜を堆積する工程
と、異方性エッチングにより該被膜をエッチングして、
溝底部の被膜を薄くするか又は溝底部の被膜を除去して
基板を露出させる工程と、前記溝底部の基板にのみ第1
導電型の不純物を導入する工程と、前記溝内部に素子分
離材料を埋設する工程とを具備したことを特徴とする半
導体装置の製造方法。
forming a semiconductor layer of a second conductivity type on a semiconductor substrate of a first conductivity type; selectively etching the semiconductor layer and a part of the semiconductor substrate by anisotropic etching to form substantially vertical side surfaces; a step of forming a groove deeper than the junction depth of the semiconductor layer; a step of depositing a film along the inner surface of the groove; and etching the film by anisotropic etching.
A step of exposing the substrate by thinning the coating at the bottom of the groove or removing the coating at the bottom of the groove;
1. A method for manufacturing a semiconductor device, comprising the steps of introducing a conductivity type impurity and burying an element isolation material inside the trench.
JP26045185A 1985-11-20 1985-11-20 Manufacture of semiconductor device Pending JPS62120040A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26045185A JPS62120040A (en) 1985-11-20 1985-11-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26045185A JPS62120040A (en) 1985-11-20 1985-11-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62120040A true JPS62120040A (en) 1987-06-01

Family

ID=17348121

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26045185A Pending JPS62120040A (en) 1985-11-20 1985-11-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62120040A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62247541A (en) * 1986-04-18 1987-10-28 Nippon Telegr & Teleph Corp <Ntt> Interelement isolation structure of integrated circuit and manufacture thereof
JPH0212941A (en) * 1988-06-30 1990-01-17 Nec Corp Manufacture of semiconductor device
JPH02209747A (en) * 1989-02-09 1990-08-21 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62247541A (en) * 1986-04-18 1987-10-28 Nippon Telegr & Teleph Corp <Ntt> Interelement isolation structure of integrated circuit and manufacture thereof
JPH0212941A (en) * 1988-06-30 1990-01-17 Nec Corp Manufacture of semiconductor device
JPH02209747A (en) * 1989-02-09 1990-08-21 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device

Similar Documents

Publication Publication Date Title
US4982266A (en) Integrated circuit with metal interconnecting layers above and below active circuitry
US4889832A (en) Method of fabricating an integrated circuit with metal interconnecting layers above and below active circuitry
JPH0355984B2 (en)
JPS6039846A (en) Manufacture of semiconductor integrated circuit device
JPH07106412A (en) Semiconductor device and fabrication thereof
JP3022714B2 (en) Semiconductor device and manufacturing method thereof
JP3142336B2 (en) Semiconductor device and manufacturing method thereof
JPS62120040A (en) Manufacture of semiconductor device
JPH1145890A (en) Manufacture of semiconductor device
JPS5984435A (en) Semiconductor integrated circuit and manufacture thereof
JPH0729971A (en) Manufacture of semiconductor device
KR100194691B1 (en) Semiconductor device and manufacturing method thereof
JP3207561B2 (en) Semiconductor integrated circuit and method of manufacturing the same
JPS60244036A (en) Semiconductor device and manufacture thereof
JP2615641B2 (en) Semiconductor device and manufacturing method thereof
TWI550864B (en) Trench-gate metal oxide semiconductor device and fabricating method thereof
JPS59217363A (en) Manufacture of bi-polar type semiconductor device
JPS5919374A (en) Manufacture of semiconductor device
JPH02203533A (en) Bipolar transistor
JPH02304931A (en) Semiconductor device and manufacture thereof
JPH11340326A (en) Manufacture of semiconductor device
JPH03175639A (en) Semiconductor device
JPH05347312A (en) Manufacture of semiconductor device
JPH11204667A (en) Semiconductor device and manufacture thereof
JPS63205953A (en) Manufacture of semiconductor device