JPH0212941A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0212941A JPH0212941A JP16432088A JP16432088A JPH0212941A JP H0212941 A JPH0212941 A JP H0212941A JP 16432088 A JP16432088 A JP 16432088A JP 16432088 A JP16432088 A JP 16432088A JP H0212941 A JPH0212941 A JP H0212941A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- film
- boron
- silicon oxide
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 229910052796 boron Inorganic materials 0.000 claims abstract description 19
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000002955 isolation Methods 0.000 claims abstract description 8
- 238000009413 insulation Methods 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 17
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 17
- 239000012535 impurity Substances 0.000 abstract description 13
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 5
- 230000001590 oxidative effect Effects 0.000 abstract description 4
- 238000001020 plasma etching Methods 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 4
- -1 boron ions Chemical class 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に絶縁分離溝
の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an isolation trench.
従来、この種の半導体装置の製造方法は、まず第3図(
a)に示すように、例えば表面にN型不純物層2と、イ
オン注入時のマスクとして用いる窒化シリコン膜5の上
下面に酸化シリコン膜4を形成した絶縁膜を有するシリ
コンからなるP型半導体基板1に、所定パターンの溝3
を形成する。Conventionally, the manufacturing method for this type of semiconductor device first began with the method shown in Fig. 3 (
As shown in a), for example, a P-type semiconductor substrate made of silicon has an N-type impurity layer 2 on the surface and an insulating film formed with a silicon oxide film 4 on the upper and lower surfaces of a silicon nitride film 5 used as a mask during ion implantation. 1, a predetermined pattern of grooves 3
form.
次に第3図(b)に示すように、ホウ素をイオン注入し
、溝の底面にチャネルストッパーとしてのP型不純物層
6を形成する。Next, as shown in FIG. 3(b), boron ions are implanted to form a P-type impurity layer 6 as a channel stopper at the bottom of the trench.
次に第3図(c)に示すように、熱酸化又はCVD法で
酸化シリコン膜4Aを形成したのち、溝の内部に多結晶
シリコン膜7を成長させることにより絶縁分離溝を形成
していた。Next, as shown in FIG. 3(c), after forming a silicon oxide film 4A by thermal oxidation or CVD, a polycrystalline silicon film 7 is grown inside the trench to form an insulating isolation trench. .
上述した従来の半導体装置の製造方法は、溝形成後にチ
ャネルストッパー用のホウ素をイオン注入しているので
、シリコン表面を酸化する時の酸化条件によってホウ素
がアウトデイフュージョンする。この為、fi3の側壁
にホウ素が拡散されて側壁にP型不純物層が形成され、
易くなり、トランジスタの特性が悪化するという欠点が
ある。In the conventional semiconductor device manufacturing method described above, boron ions for a channel stopper are ion-implanted after trench formation, so that boron out-diffusions depending on the oxidation conditions when oxidizing the silicon surface. Therefore, boron is diffused into the sidewall of fi3 and a P-type impurity layer is formed on the sidewall.
This has the disadvantage that the characteristics of the transistor deteriorate.
本発明の半導体装置の製造方法は、半導体基板に絶縁分
離用の溝を形成する工程と、前記溝の表面に絶縁膜を形
成したのち溝底部の該絶縁膜を除去する工程と、絶縁膜
が除去された前記溝の底部にホウ素を導入しチャネルス
トッパー層を形成する工程とを含んで構成される。The method for manufacturing a semiconductor device of the present invention includes the steps of forming a groove for insulation isolation in a semiconductor substrate, forming an insulating film on the surface of the groove and then removing the insulating film at the bottom of the groove, and removing the insulating film from the bottom of the groove. The method includes a step of introducing boron into the bottom of the removed groove to form a channel stopper layer.
次に本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第1図(a)〜(d)は本発明の第1の実施例を説明す
るための工程順に配置した半導体チップの断面図である
。FIGS. 1(a) to 1(d) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining a first embodiment of the present invention.
まず、第1図(a)に示すように、P型半導体基板1の
表面にN型不純物N2をエピタキシャル成長法により形
成し、しかる後にその上に酸化シリコン膜4.窒化シリ
コン膜5.酸化シリコン膜4の3層−構造からなる絶縁
膜を形成する。次に幅1μmでP型半導体基板1内に達
する絶縁分離用の溝3をホトリソグラフィー技術とエツ
チング技術を用いて形成する。First, as shown in FIG. 1(a), an N-type impurity N2 is formed on the surface of a P-type semiconductor substrate 1 by epitaxial growth, and then a silicon oxide film 4. Silicon nitride film 5. An insulating film having a three-layer structure of silicon oxide film 4 is formed. Next, a groove 3 for insulation isolation reaching the inside of the P-type semiconductor substrate 1 and having a width of 1 μm is formed using photolithography and etching techniques.
次に第1図(b)に示すように、熱酸化により溝3の表
面に薄い酸化シリコン膜4Aを形成する。Next, as shown in FIG. 1(b), a thin silicon oxide film 4A is formed on the surface of the groove 3 by thermal oxidation.
次に第1図(c)に示すように、リアクティブイオンエ
ツチング法を用いて溝3の底部の薄い酸化シリコン膜4
Aをエツチングし除去する。Next, as shown in FIG. 1(c), a thin silicon oxide film 4 at the bottom of the groove 3 is etched using a reactive ion etching method.
Etch and remove A.
次に第1図(d)に示すように、ホウ素をイオン注入し
、しかる後に酸化性雰囲気中で温度900℃〜1000
℃で熱処理を行ない、溝の底面に薄い酸化シリコン膜と
チャネルストッパーであるP型不純物層6を形成する。Next, as shown in FIG. 1(d), boron ions are implanted, and then the temperature is 900°C to 1000°C in an oxidizing atmosphere.
A heat treatment is performed at .degree. C. to form a thin silicon oxide film and a P-type impurity layer 6 serving as a channel stopper on the bottom surface of the trench.
次で溝3を埋込むために多結晶シリコン膜7を成長させ
絶縁分離溝を完成させる。Next, a polycrystalline silicon film 7 is grown to fill the trench 3, thereby completing the insulation isolation trench.
このように第1の実施例によれば、?s3の側面に酸化
シリコン膜4Aを形成したのちホウ素のイオン注入法に
よりP型不純物層6を形成するなめ、溝3の側面のシリ
コン層にホウ素が拡散されることはなくなる。According to the first embodiment, ? Since the P-type impurity layer 6 is formed by boron ion implantation after forming the silicon oxide film 4A on the side surface of the trench s3, boron is not diffused into the silicon layer on the side surface of the groove 3.
第2図は本発明の第2の実施例を説明するための工程順
に示した半導体チップの断面図である。FIG. 2 is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining a second embodiment of the present invention.
まず第2図(a)に示すように、第1の実施例と同様に
処理し、P型半導体基板1上にN型不純物層2と酸化シ
リコン膜4と窒化シリコン膜5を形成したのち溝3を形
成する。次で溝3内に薄い酸化シリコン膜4Aを形成し
たのち、溝の底面部の酸化シリコン膜4Aを除去する。First, as shown in FIG. 2(a), an N-type impurity layer 2, a silicon oxide film 4, and a silicon nitride film 5 are formed on a P-type semiconductor substrate 1 by the same process as in the first embodiment, and then trenches are formed. form 3. Next, after forming a thin silicon oxide film 4A in the trench 3, the silicon oxide film 4A at the bottom of the trench is removed.
次に第2図(b)に示すように、拡散法を用いてホウ素
を拡散し、P型不純物層6とホウ素含有の硝子M8を形
成する。Next, as shown in FIG. 2(b), boron is diffused using a diffusion method to form a P-type impurity layer 6 and a boron-containing glass M8.
次に第2図(C)に示すように、拡散法で形成されたホ
ウ素含有の硝子層8を弗酸水溶液でエツチングして除去
し、しかる後に酸化性雰囲気中で900〜1000℃で
熱処理を行ない、溝3の底面に薄い酸化シリコン膜を形
成する。Next, as shown in FIG. 2(C), the boron-containing glass layer 8 formed by the diffusion method is removed by etching with a hydrofluoric acid aqueous solution, and then heat treated at 900 to 1000°C in an oxidizing atmosphere. Then, a thin silicon oxide film is formed on the bottom surface of the groove 3.
次に第2図(d)に示すように、溝3を埋込むために多
結晶シリコン膜7を成長させ絶縁分離溝を完成させる。Next, as shown in FIG. 2(d), a polycrystalline silicon film 7 is grown to fill the trench 3, thereby completing the insulation isolation trench.
本第2の実施例によれば、チャネルストッパーとしての
P型不純物N6を拡散法により形成しているため、第1
の実施例のイオン注入法い比ベシリコン結晶層に与える
損傷を少くできるという利点がある。According to the second embodiment, since the P-type impurity N6 as a channel stopper is formed by the diffusion method, the first
This method has the advantage that damage to the silicon crystal layer can be reduced compared to the ion implantation method of the embodiment.
以上説明したように本発明は、半導体基板に形成した溝
の表面に絶縁膜を形成し、溝底面部の絶縁膜を除去した
のちホウ素を導入してチャネルストッパ層を形成するこ
とにより、溝の壁側にホウ素が拡散するのを防ぐことが
出来る。従ってトランジスタの特性を安定にすることが
できるため、品質及び歩留の向上した半導体装置が得ら
れる。As explained above, the present invention forms an insulating film on the surface of a trench formed in a semiconductor substrate, removes the insulating film at the bottom of the trench, and then introduces boron to form a channel stopper layer. This can prevent boron from diffusing into the wall. Therefore, since the characteristics of the transistor can be stabilized, a semiconductor device with improved quality and yield can be obtained.
第1図(a)〜(d)及び第2図(a)〜(d)は本発
明の第1及び第2の実施例を説明するための工程手順に
配置した半導体チップの断面図、第3図(a)〜(c)
は従来の半導体装置の製造方法を説明するための半導体
チップの断面図である。
1・・・P型半導体基板、2・・・N型不純物層、3・
・・溝、4,4A・・・酸化シリコン膜、5・・・窒化
シリコン膜、
6・・・P型不純物層、
7・・・多結晶シリ
コン
膜、
8・・・ホウ素含有の硝子層。1(a)-(d) and FIG. 2(a)-(d) are cross-sectional views of semiconductor chips arranged in process steps for explaining the first and second embodiments of the present invention. Figure 3 (a) to (c)
1 is a cross-sectional view of a semiconductor chip for explaining a conventional method of manufacturing a semiconductor device. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... N-type impurity layer, 3...
... Groove, 4, 4A... Silicon oxide film, 5... Silicon nitride film, 6... P-type impurity layer, 7... Polycrystalline silicon film, 8... Boron-containing glass layer.
Claims (1)
の表面に絶縁膜を形成したのち溝底部の該絶縁膜を除去
する工程と、絶縁膜が除去された前記溝の底部にホウ素
を導入しチャネルストッパー層を形成する工程とを含む
ことを特徴とする半導体装置の製造方法。A step of forming a trench for insulation isolation in a semiconductor substrate, a step of forming an insulating film on the surface of the trench and then removing the insulating film at the bottom of the trench, and a step of applying boron to the bottom of the trench from which the insulating film has been removed. A method for manufacturing a semiconductor device, comprising the step of forming a channel stopper layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16432088A JPH0212941A (en) | 1988-06-30 | 1988-06-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16432088A JPH0212941A (en) | 1988-06-30 | 1988-06-30 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0212941A true JPH0212941A (en) | 1990-01-17 |
Family
ID=15790913
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16432088A Pending JPH0212941A (en) | 1988-06-30 | 1988-06-30 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0212941A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20010004674A (en) * | 1999-06-29 | 2001-01-15 | 김영환 | Manufacturing method for semiconductor device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5544741A (en) * | 1978-09-26 | 1980-03-29 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS62120040A (en) * | 1985-11-20 | 1987-06-01 | Toshiba Corp | Manufacture of semiconductor device |
JPS62213142A (en) * | 1986-03-13 | 1987-09-19 | Seiko Epson Corp | Manufacture of semiconductor device |
-
1988
- 1988-06-30 JP JP16432088A patent/JPH0212941A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5544741A (en) * | 1978-09-26 | 1980-03-29 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS62120040A (en) * | 1985-11-20 | 1987-06-01 | Toshiba Corp | Manufacture of semiconductor device |
JPS62213142A (en) * | 1986-03-13 | 1987-09-19 | Seiko Epson Corp | Manufacture of semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20010004674A (en) * | 1999-06-29 | 2001-01-15 | 김영환 | Manufacturing method for semiconductor device |
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